KR20030056465A - Bit line sense amplifier of a semiconductor memory device - Google Patents

Abstract

The semiconductor memory device including the sense amplifier reduces the offset voltage between the input terminal and the output terminal of the sense amplifier to improve the sensing sensitivity, thereby increasing the cell density of the semiconductor memory device and stably operating at low voltage power supply. It is characterized in that it comprises a plurality of switching elements controlled by a plurality of switching control signals to sequentially sense the amplification scheme of the amplifier to quickly sense the data carried on the bit line, and amplify sufficiently.

Description

Bit line sense amplifier of a semiconductor memory device

The present invention relates to a bit line sense amplifier for sensing and amplifying and outputting data of a memory cell in a semiconductor memory device. More particularly, the amplification method of a sense amplifier is sequentially performed using a switching element controlled by a switching control signal. The present invention relates to a bit line sense amplifier of a semiconductor memory device that is deformed to compensate for an offset voltage between an input terminal and an output terminal, and is sensed and amplified and output.

In general, the bit line sense amplifier senses and amplifies data loaded on a bit line and outputs the data to the data bus, and the data bus sense amplifier senses and amplifies data amplified by the bit line sense amplifier again and outputs the data to the data output buffer.

The operation of a general bit line sense amplifier is as follows. Here, the bit line sense amplifier uses a cross-coupled latched amplifier.

First, the bit line is precharged with a precharge voltage (for example, half of the internal power supply voltage VDD), and the two bit lines are removed to eliminate the voltage difference between the bit line to which the selected memory cell is connected and the bit line to which it is not. Equalize.

The row decoder analyzes an externally input row address and selects a word line corresponding to the row address, and a cell transistor connected to the selected word line is turned on to generate charge distribution between the cell capacitance and the bit line capacitance. A potential difference occurs between the bit line to which the memory cell is connected and the bit line to which the memory cell is not connected.

At this time, when the sense amplifier control signals RTO and / S are enabled, that is, the sense amplifier control signal RTO becomes the high level VDD, and the sense amplifier control signal / S becomes the low level VSS so that the bit line sense amplifier operates to select the selected memory cell. The potential difference between the connected bit line and the unconnected bit line is sensed and amplified.

For example, assuming that the data stored in the selected memory cell is low-level data, the potential of the bit line to which the selected cell is connected is lower than the precharge voltage, and the potential of the bit line to which the selected cell is not connected is precharged. Since the voltage is maintained, a potential difference occurs between the two bit lines.

Thus, the bit line sense amplifier, a cross coupled coupled latch type amplifier, makes the bit line to which the selected memory cell is connected to the low level VSS by the sense amplifier control signal / S, and the bit line that is not high by the sense amplifier control signal RTO. Make it to level VDD.

Then, when the column address is analyzed by the column decoder and the column control signal YI corresponding to the column address is enabled at a high level, the amplified data carried on the bit line by the bit line sense amplifier is transmitted to the data bus.

However, when the sense amplifier of the conventional semiconductor memory device operates at a low voltage, the sense amplifier may not operate stably when sensing data loaded on the bit line by the offset voltage between the bit line and the sense amplifier. Therefore, there is a problem that it takes a considerable time to fully amplify the data carried on the bit line.

This is because, when operating at a low voltage, the capacitance of the bit line becomes larger than the cell capacitance, and thus the potential difference between the bit line to which the selected memory cell is connected and the bit line to which the selected memory cell is not connected becomes small during charge distribution.

Therefore, when the bit line sense amplifier senses a small voltage difference between the bit line to which the selected memory cell is connected and the bit line to which the selected memory cell is not connected, the operation of the sense amplifier is slow because the voltage difference is less than the offset voltage. If it is small, there is a problem that a data error occurs due to incorrect sensing of data.

Accordingly, an object of the present invention is to increase the sensing sensitivity and sufficiently amplify data loaded on a bit line by a bit line sense amplifier of a semiconductor memory device.

Still another object of the present invention is to stably operate a bit line sense amplifier of a semiconductor memory device by compensating an offset voltage between an input terminal and an output terminal of a sense amplifier.

1 is a circuit diagram illustrating a sense amplifier of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is an operation timing diagram when data is loaded on the left bit line in the circuit diagram of FIG.

3A to 3D are conceptual views illustrating a form in which the circuit diagram of FIG. 1 is modified according to each operation section of the operation timing diagram of FIG. 2.

4 is an operation timing diagram when data is loaded on the right bit line in the circuit diagram of FIG.

5A to 5D are conceptual views illustrating a circuit diagram of FIG. 1 modified according to each operation section of the operation timing diagram of FIG. 2.

<Description of Symbols for Main Parts of Drawings>

PM1, PM2: PMOS transistor

NM1-NM9: NMOS transistor

CONA, CONB, CONC, COND, CONE, CONF, CONG: Switching control signal

To achieve the above object, a bit line sense amplifier of a semiconductor memory device of the present invention includes: PMOS transistors having a common source connected thereto and a power supply voltage applied thereto; NMOS transistors each having a drain connected to a drain of the PMOS transistors, a source connected in common, a sense amplifier control signal applied thereto, and a gate connected to each bit line pair; First switching means controlled by a first switching signal and connected between gates of the PMOS transistors; Second switching means and third switching means respectively controlled by a second switching signal and a third switching signal and connected between each of the drain of the PMOS transistors and the bit line pair; And a plurality of fourth switching means which are controlled by a plurality of control signals and deform with a plurality of amplification schemes while the bit line sense amplifier is enabled.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram illustrating a bit line sense amplifier of a semiconductor memory device according to an embodiment of the present invention.

As shown therein, the bit line sense amplifier of the semiconductor memory device includes PMOS transistors PM1 and PM2 and NMOS transistors NM1 to NM9.

Sources of the PMOS transistors PM1 and PM2 are commonly connected, and an internal power supply voltage VDD is applied.

The NMOS transistors NM1 and NM2 have drains connected to drains of the PMOS transistors PM1 and PM2, gates are respectively connected to the bit lines BL and / BL, and the source is connected in common, so that the sense amplifier control signal / S is applied. do.

The switching control signal CONA is applied to the gate of the NMOS transistor NM3, and is connected between the drain of the PMOS transistor PM1 and the gate of the PMOS transistor PM2.

The NMOS transistor NM4 is supplied with a switching control signal CONB to its gate, and is connected between the gate of the PMOS transistor PM1 and the drain of the PMOS transistor PM2.

The NMOS transistor NM5 is applied with a switching control signal CONC at its gate, and is connected between the drain of the NMOS transistor NM2 and the gate of the NMOS transistor NM1.

The NMOS transistor NM6 is applied with a switching control signal COND to its gate, and is connected between the drain of the NMOS transistor NM1 and the gate of the NMOS transistor NM2.

The NMOS transistor NM7 receives a switching control signal CONE at its gate and is connected between the drain of the PMOS transistor PM1 and the left bit line BLL.

The NMOS transistor NM8 receives a switching control signal CONF at its gate and is connected between the drain of the PMOS transistor PM2 and the right bit line BLR.

The NMOS transistor NM9 receives a switching control signal CONG at its gate and is connected between the gates of the PMOS transistors PM1 and PM2.

Here, PMOS transistors PM1 and PM2 and NMOS transistors NM1 and NM2 are basic components of a bit line sense amplifier, and are controlled by switching control signals CONA, CONB, CONC, COND, CONE, CONF, and CONG. The MOS transistors NM3-NM9 are switching elements that sequentially convert the amplification scheme of the bit line sense amplifier into a negative feedback differential amplification, a normal differential amplification, a positive feedback differential amplification, and a cross coupled latched amplification scheme. In particular, the NMOS transistors NM5-NM8 are also used as switching elements to reduce the offset voltage between the input terminal and the output terminal of the bit line sense amplifier.

The operation of the bit line sense amplifier of the semiconductor memory device will be described below with reference to an operation timing chart.

First, when a memory cell connected to the left bit line BLL is selected and data is loaded, the operation timing diagram of FIG. 2 and the conceptual diagrams of FIGS. 3A to 3D will be described.

Here, the T1-T4 section in the operation timing diagram of FIG. 2 is a section in which the bit line sense amplifier is enabled.

The bit line sense amplifier is a negative feedback amplification method in the T1 section, a normal differential amplification method in the T2 section, a positive feedback differential amplification method in the T3 section, and a cross-coupled latch amplification method in the T4 section by the switching control signals CONA-CONG. Are sequentially modified.

In the T1 section, the sense amplifier control signal / S is enabled at a low level so that the sense amplifier operates.

At this time, since the switching control signals CONA and CONG become high levels, the NMOS transistors NM3 and NM9 are turned on so that the gates of the PMOS transistors PM1 and PM2 are commonly connected, and the common gate is connected to the drain of the PMOS transistor PM1. Because of this connection, the bit line sense amplifiers form a differential amplifier.

In addition, since the switching control signal CONF is turned high and the NMOS transistor NM8 is turned on, the right bit line BLR, which is an inverting input terminal of a bit line sense amplifier having a differential amplifier type, and the PMOS transistor PM2, which is a non-inverting output terminal, Since the common connected drain of the MOS transistor NM2 is connected, it forms a negative feedback differential amplifier type as shown in FIG. 3A.

Thus, the potential of the right bit line BLR is adjusted to a voltage that compensates for the offset voltage between the inverting input terminals of the bit line sense amplifier.

Subsequently, in the T2 period, the switching control signal CONF becomes low and the NMOS transistor NM8 is turned off, thereby forming a bit line sense amplifier as shown in FIG. 3B to form a normal differential amplifier.

At this time, the word line WL is enabled to carry data stored in the selected memory cell in the left bit line BLL. Thus, the data carried on the left bit line BLL is sensed and amplified by a bit line sense amplifier in the form of a normal differential amplifier.

Here, since the switching control signals CONC and COND are at the low level, the NMOS transistors NM5 and NM6 are turned off. Accordingly, the output terminal of the bit line sense amplifier is separated from the bit lines BLL and BLR which are input terminals so that the output terminal of the bit line sense amplifier is not affected by the offset voltage between the input terminal and the output terminal of the bit line sense amplifier.

In the T3 section, the switching control signal CONC goes high and the NMOS transistor NM5 turns on. The switching control signal COND goes low and the NMOS transistor NM6 turns off so that the left bit, the non-inverting input terminal of the bit line sense amplifier, is turned on. Since the line BLL and the non-inverting output terminal PMOS transistor PM2 and the common connected drain of the NMOS transistor NM2 are connected, the bit line sense amplifier forms a positive feedback differential amplifier as shown in FIG. 3C. .

Therefore, the data contained in the left bit line BLL is a common connected drain and non-inverting input terminal of the PMOS transistor PM2 and the NMOS transistor NM2 which are the non-inverting output terminals of the bit line sense amplifier having the form of a positive feedback differential amplifier. It is sensed and amplified while compensating the offset voltage between them.

Subsequently, in the period T4, the switching control signals CONA, CONB, CONC, and COND become high level, so that the NMOS transistors NM3-NM6 are turned on, and the switching control signals CONE, CONF, and CONG become low level. Since the NM7-NM9 is turned off, the bit line sense amplifier forms a cross-coupled latch form as shown in FIG. 3D. Therefore, the data amplified in the previous step is quickly latched.

FIG. 4 illustrates an operation timing diagram when a memory cell connected to the right bit line BLR is selected and data is loaded in the circuit diagram of FIG. 1.

An operation when a memory cell connected to the right bit line BLR is selected and data is loaded will be described with reference to the conceptual diagrams shown in FIGS. 5A to 5D.

The bit line sense amplifier is a negative feedback amplification method in the T1 section, a normal differential amplification method in the T2 section, a positive feedback differential amplification method in the T3 section, and a cross-coupled latch amplification method in the T4 section by the switching control signals CONA-CONG. Are sequentially modified.

In the T1 section, the sense amplifier control signal / S is enabled at a low level so that the sense amplifier operates.

At this time, since the switching control signals CONA and CONG become high levels, the NMOS transistors NM3 and NM9 are turned on so that the gates of the PMOS transistors PM1 and PM2 are commonly connected, and the common gate is connected to the drain of the PMOS transistor PM2. Because of this connection, the bit line sense amplifiers form a differential amplifier.

In addition, since the switching control signal CONE becomes high and the NMOS transistor NM7 is turned on, the left bit line BLL, which is an inverting input terminal of a bit line sense amplifier having a differential amplifier type, and the PMOS transistor PM1, which is a non-inverting output terminal, and the NMOS transistor NM7 are turned on. Since the common connected drain of the MOS transistor NM1 is connected, it forms a negative feedback differential amplifier type as shown in FIG. 5A.

Thus, the potential of the left bit line BLL is adjusted to a voltage that compensates for the offset voltage between the inverting input terminals of the bit line sense amplifier.

Subsequently, in the T2 period, the switching control signal CONE becomes low and the NMOS transistor NM7 is turned off to form a normal differential amplifier, as shown in FIG. 5B.

At this time, the word line WL is enabled so that data stored in the selected memory cell is loaded on the right bit line BLR. Thus, the data carried on the right bit line BLR is sensed and amplified by a bit line sense amplifier in the form of a normal differential amplifier.

Here, since the switching control signals CONC and COND are at the low level, the NMOS transistors NM5 and NM6 are turned off. Accordingly, the output terminal of the bit line sense amplifier is separated from the bit lines BLL and BLR which are input terminals so that the output terminal of the bit line sense amplifier is not affected by the offset voltage between the input terminal and the output terminal of the bit line sense amplifier.

In the T3 section, the switching control signal CONC is turned low to turn off the NMOS transistor NM5, and the switching control signal COND is turned to high to turn the NMOS transistor NM6 to turn on so that the right bit of the non-inverting input terminal of the bit line sense amplifier is turned on. The bit line sense amplifier forms a positive feedback differential amplifier as shown in FIG. 5C because the line BLR, the PMOS transistor PM1 which is a non-inverting output terminal, and the common connected drain of the NMOS transistor NM1 are connected. .

Therefore, the data loaded on the right bit line BLR is a common connected drain and non-inverting input terminal of PMOS transistor PM1 and NMOS transistor NM1, which are non-inverted output terminals of a bit line sense amplifier having a positive feedback differential amplifier type, and right bit line BLR. It is sensed and amplified while compensating the offset voltage between them.

Subsequently, in the period T4, the switching control signals CONA, CONB, CONC, and COND become high level, so that the NMOS transistors NM3-NM6 are turned on, and the switching control signals CONE, CONF, and CONG become low level. Since the NM7-NM9 is turned off, the bit line sense amplifier forms a cross coupled connected latch shape as shown in FIG. 5D. Therefore, the data amplified in the previous step is quickly latched.

As described above, the bit line sense amplifier of the present invention controls the NMOS transistors NM3-NM9 which are switching means by switching control signals CONA, CONB, CONC, COND, CONE, CONF, and CONG to sequentially amplify the bit line sense amplifier. Modifications can be made to efficiently sense and amplify the data on the bit line BLL or BLR while compensating for the offset voltage.

Here, the bit line sense amplifier senses and sufficiently amplifies the data carried on the bit line BLL or BLR in the state where the offset voltage is compensated, so that the circuit itself is not sensitive to the offset voltage. The offset voltage is not large because PM2, NM1 and NM2 are deformed in stages.

In addition, since the internal power supply voltage VDD is applied to the common source of the PMOS transistors PM1 and PM2, a circuit (not shown) for generating the sense amplifier control signal RTO used in the sense amplifier of the prior art is not required, thereby reducing the chip size. .

The present invention can improve the sensing sensitivity of the sense amplifier by reducing the influence of the offset voltage, thereby increasing the memory cell density and stable operation even at low voltage.

As described above with reference to the drawings illustrating a sense amplifier of a semiconductor memory device according to the present invention, the present invention is not limited by the embodiments and drawings posted herein, the scope does not depart from the spirit of the present invention Various substitutions, modifications and variations will be possible within the scope.

Claims (6)

In a bit line sense amplifier of a semiconductor memory device which is enabled by a sense amplifier control signal and senses and amplifies data carried on a bit line by applying a constant power supply voltage, The bit line sense amplifier, And a plurality of switching means which are controlled by a plurality of switching control signals and deform with a plurality of amplification schemes while the sense amplifier is enabled. The method of claim 1, The bit line sense amplifier, A plurality of PMOS transistors having a common source connected thereto, to which the constant power supply voltage is applied; A plurality of NMOS transistors each having a drain connected to a drain of the plurality of PMOS transistors, a source connected in common, a sense amplifier control signal applied thereto, and a gate connected to each of a pair of bit lines; First switching means controlled by a first switching signal and connected between gates of the plurality of PMOS transistors; Second switching means and third switching means, respectively controlled by a second switching signal and a third switching signal, connected between the drain of the plurality of PMOS transistors and each of the bit line pairs; And And a plurality of fourth switching means which are controlled by a plurality of control signals and deform with a plurality of amplification methods while the bit line sense amplifier is enabled. The method of claim 2, The second switching means and the third switching means, And a sense amplifier, when the bit line sense amplifier operates in a negative feedback differential amplification scheme, the bit line sense amplifier is turned on to compensate for an offset voltage between an input terminal and an output terminal of the sense amplifier. The method of claim 2, At least one switching means of the plurality of fourth switching means, And the sense amplifier is turned on to compensate for offset voltage between an input terminal and an output terminal of the sense amplifier when the sense amplifier operates in a positive feedback differential amplification scheme. The method of claim 1, The second switching means and the third switching means, And a sense amplifier, wherein the sense amplifier is turned off when the sense amplifier is operated in a normal differential amplification scheme to separate an output terminal and a bit line of the sense amplifier. The method of claim 1, The bit line sense amplifier, A semiconductor memory device comprising a sense amplifier, characterized in that the amplification method is sequentially changed into a negative feedback differential amplification method, a normal differential amplification method, a positive feedback differential amplification method and a cross-coupled latch type amplification method while being enabled.