KR20030053085A - Method for fabricating silicon wafer - Google Patents
Method for fabricating silicon wafer Download PDFInfo
- Publication number
- KR20030053085A KR20030053085A KR1020010083120A KR20010083120A KR20030053085A KR 20030053085 A KR20030053085 A KR 20030053085A KR 1020010083120 A KR1020010083120 A KR 1020010083120A KR 20010083120 A KR20010083120 A KR 20010083120A KR 20030053085 A KR20030053085 A KR 20030053085A
- Authority
- KR
- South Korea
- Prior art keywords
- bare wafer
- edge
- double
- cleaning
- notch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 29
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 29
- 239000010703 silicon Substances 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000007517 polishing process Methods 0.000 claims abstract description 36
- 238000004140 cleaning Methods 0.000 claims abstract description 23
- 238000005498 polishing Methods 0.000 claims abstract description 20
- 238000010438 heat treatment Methods 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 9
- 230000007547 defect Effects 0.000 claims abstract description 5
- 239000013078 crystal Substances 0.000 claims abstract description 4
- 238000005520 cutting process Methods 0.000 claims abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 21
- 235000012431 wafers Nutrition 0.000 description 54
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 238000002109 crystal growth method Methods 0.000 description 4
- 238000005406 washing Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 238000007518 final polishing process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02013—Grinding, lapping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02016—Backside treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02024—Mirror polishing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
본 발명은 300밀리미터 실리콘 웨이퍼의 제조방법으로 실리콘 단결정 잉곳을 얇게 절단하여 형성한 베어 웨이퍼의 가장자리의 형상을 일정하게 하기 위한 가장자리 연삭 공정과; 상기 가장자리 연삭공정 후 상기 베어 웨이퍼의 평탄도를 향상시키기 위한 양면 연삭공정과; 상기 양면 연삭공정 후 가장자리 노치부의 거칠기를 감소시키기 위한 노치부 연마공정과; 상기 노치부 연마공정 후 상기 베어 웨이퍼 내부의 결함을 제거하기 위한 열처리 공정과; 상기 열처리 공정 후 상기 베어 웨이퍼의 표면을 경면화하기 위한 양면 연마 공정과; 상기 양면 연마공정 후 불순물을 제거하고 상기 베어 웨이퍼의 표면에 산화막을 형성하기 위한 제1차 세정과; 상기 제1차 세정 후 상기 가장자리 라운드부의 거칠기를 감소시키기 위한 라운드부 연마공정과; 상기 라운드부 연마공정 후 상기 베어 웨이퍼의 불순물을 제거하기 위한 제2차 세정 공정과; 상기 제2차 세정공정 후 상기 베어 웨이퍼 표면의 미소거칠기를 감소시키기 위한 마무리 연마공정을 포함하여 이루어진다.The present invention provides an edge grinding process for making a shape of an edge of a bare wafer formed by thinly cutting a silicon single crystal ingot by a method of manufacturing a 300 mm silicon wafer; A double-sided grinding step for improving flatness of the bare wafer after the edge grinding step; A notch part polishing step for reducing roughness of the edge notch part after the double-sided grinding step; A heat treatment process for removing defects in the bare wafer after the notch polishing step; A double-side polishing step for mirror-mirroring the surface of the bare wafer after the heat treatment step; First cleaning to remove impurities after the double-side polishing process and to form an oxide film on the surface of the bare wafer; A round part polishing step for reducing roughness of the edge round part after the first cleaning; A second cleaning step for removing impurities of the bare wafer after the round part polishing step; And finishing polishing to reduce the micro roughness of the bare wafer surface after the second cleaning process.
따라서 노치부 연마시 형성되는 패드 마크가 후속공정에서 제거되어 고품질의 실리콘 웨이퍼를 제조할 수 있다.Therefore, the pad mark formed when the notch is polished may be removed in a subsequent process to manufacture a high quality silicon wafer.
Description
본 발명은 실리콘 웨이퍼의 제조방법에 관한 것으로, 특히 300밀리미터 실리콘 웨이퍼의 제조공정 중 노치부와 라운드부의 연마공정을 양면 연마공정 전, 후에 각각 구분하여 실시함으로써 고품질의 실리콘 웨이퍼를 생산하는 300밀리미터 실리콘 웨이퍼의 제조방법이다.The present invention relates to a method of manufacturing a silicon wafer, and in particular, a 300 mm silicon for producing a high quality silicon wafer by performing the grinding process of the notch part and the round part separately before and after the two-side polishing process in the manufacturing process of the 300 mm silicon wafer. It is a manufacturing method of a wafer.
도1은 종래기술에 따른 실리콘 웨이퍼를 제조하는 방법을 도시한 공정도이다. 도1에 도시된 바와같이, 현재 반도체 소자에 사용되는 300밀리미터(mm) 실리콘 웨이퍼의 생산 공정을 상세히 설명하면 다음과 같다.1 is a process diagram showing a method of manufacturing a silicon wafer according to the prior art. As shown in FIG. 1, the production process of a 300 mm (mm) silicon wafer currently used in semiconductor devices will be described in detail.
먼저 초크랄스키(Czochrakski) 결정성장법 또는 플로트존(Float zone) 결정 성장법에 의해서 형성된 단결정 실리콘 봉을 와이어 소우, I.D 소우, O.D 소우등을 사용하여 얇게 슬라이싱하는 공정을 실시하여 베어 웨이퍼를 형성한 후, 베어 웨이퍼의 가장자리가 일정한 형상을 가지도록 가장자리 연삭공정을 실시한다(S1).First, a bare wafer is formed by thinly slicing single crystal silicon rods formed by Czochrakski crystal growth method or Float zone crystal growth method using wire saws, ID saws, and OD saws. After that, the edge grinding step is performed such that the edge of the bare wafer has a constant shape (S1).
그리고 베어 웨이퍼의 전, 후면(이하, 양면 또는 표면이라 칭함)을 평탄화하기 위해서 양면 연삭(Grinding) 공정을 실시한다(S2).Then, in order to planarize the front and rear surfaces (hereinafter, referred to as both surfaces or surfaces) of the bare wafer, a double-sided grinding process is performed (S2).
이후 베어 웨이퍼의 가장자리의 거칠기(Roughness)를 감소시키기 위해서 가장자리 연마 공정을 실시한다(S3).Thereafter, the edge polishing process is performed to reduce the roughness of the edge of the bare wafer (S3).
가장자리 연마 공정이 완료된 후, SC-1세정액, SC-2세정액, 불산을 이용한 세정을 순차적으로 실시하여 가장자리 연마 공정 시 발생된 불순물을 제거한다(S4).After the edge polishing process is completed, washing with SC-1 cleaning solution, SC-2 cleaning solution, and hydrofluoric acid is sequentially performed to remove impurities generated during the edge polishing process (S4).
그리고 세정공정 후 열처리를 실시하여 베어 웨이퍼 내부에 존재하는 결함을 제거한다(S5).After the cleaning process, heat treatment is performed to remove defects existing in the bare wafer (S5).
상기 열처리는 실리콘 웨이퍼를 제조하는 공정에서 일반적으로 실시되는 열처리로 본 발명에서 그에 대한 상세한 설명은 생략한다.The heat treatment is a heat treatment generally performed in the process of manufacturing a silicon wafer, and a detailed description thereof is omitted in the present invention.
열처리 후 베어 웨이퍼의 양면을 경면화하기 위한 양면 연마 공정을 실시한다(S6).After the heat treatment, a double-side polishing process is performed to mirror both surfaces of the bare wafer (S6).
그리고 SC-1세정액, 불산을 사용하여 순차적으로 세정한다(S7).Subsequently, washing is performed using SC-1 cleaning solution and hydrofluoric acid (S7).
마지막으로 마무리 연마공정을 실시하여 베어 웨이퍼의 표면의 미소 거칠기를 더욱 감소시켜 실리콘 웨이퍼를 완성한다.Finally, a finish polishing process is performed to further reduce the micro roughness of the bare wafer surface to complete the silicon wafer.
이렇게 형성된 실리콘 웨이퍼는 양면 연마공정시 사용되는 캐리어(carrier)와의 접촉으로 인해 실리콘 웨이퍼의 가장자리에 디그라데이션(degradation)이 발생하는 문제점이 있었다.The silicon wafer thus formed has a problem in that degradation occurs at the edge of the silicon wafer due to contact with a carrier used in a double-side polishing process.
그래서 이를 보완한 방법으로 양면 연마공정 후에 가장자리 연마 공정을 실시하는방법이 제안되었다. 그러나 이는 가장자리 연마공정 중 노치부를 연마할 때 패드마크가 형성되는 문제점이 있었다.Therefore, as a complementary method, a method of performing an edge polishing process after a double-side polishing process has been proposed. However, this has a problem in that a pad mark is formed when the notch portion is polished during the edge polishing process.
따라서 본 발명은 상기한 종래문제점을 해결하기 위한 것으로, 특히 가장자리 노치부 연마공정을 양면 연마공정 전에 실시하고 가장자리 라운드부 연마공정을 양면 연마공정 후에 실시하여 고품질의 실리콘 웨이퍼를 제조하는 방법을 제공함을 목적으로 한다.Accordingly, the present invention is to solve the above-mentioned problems, in particular, the edge notch polishing process is performed before the double-side polishing process and the edge round portion polishing process is carried out after the double-side polishing process to provide a method for producing a high quality silicon wafer. The purpose.
상기한 목적을 달성하기 위한 본 발명에 따른 실리콘 웨이퍼의 제조방법은 실리콘 단결정 잉곳을 얇게 절단하여 형성한 베어 웨이퍼의 가장자리의 형상을 일정하게 하기 위한 가장자리 연삭 공정과; 상기 가장자리 연삭공정 후 상기 베어 웨이퍼의 평탄도를 향상시키기 위한 양면 연삭공정과; 상기 양면 연삭공정 후 가장자리 노치부의 거칠기를 감소시키기 위한 노치부 연마공정과; 상기 노치부 연마공정 후 상기 베어 웨이퍼 내부의 결함을 제거하기 위한 열처리 공정과; 상기 열처리 공정 후 상기 베어 웨이퍼의 표면을 경면화하기 위한 양면 연마 공정과; 상기 양면 연마공정 후 불순물을 제거하고 상기 베어 웨이퍼의 표면에 산화막을 형성하기 위한 제1차 세정과; 상기 제1차 세정 후 상기 가장자리 라운드부의 거칠기를 감소시키기 위한 라운드부 연마공정과; 상기 라운드부 연마공정 후 상기 베어 웨이퍼의 불순물을 제거하기 위한 제2차 세정 공정과; 상기 제2차 세정공정 후 상기 베어 웨이퍼 표면의 미세거칠기를 감소시키기 위한 마무리 연마공정을 포함하여 이루어진다.According to an aspect of the present invention, there is provided a method of fabricating a silicon wafer, the method comprising: an edge grinding process for making a shape of an edge of a bare wafer formed by thinly cutting a silicon single crystal ingot; A double-sided grinding step for improving flatness of the bare wafer after the edge grinding step; A notch part polishing step for reducing roughness of the edge notch part after the double-sided grinding step; A heat treatment process for removing defects in the bare wafer after the notch polishing step; A double-side polishing step for mirror-mirroring the surface of the bare wafer after the heat treatment step; First cleaning to remove impurities after the double-side polishing process and to form an oxide film on the surface of the bare wafer; A round part polishing step for reducing roughness of the edge round part after the first cleaning; A second cleaning step for removing impurities of the bare wafer after the round part polishing step; And a final polishing process for reducing the fine roughness of the bare wafer surface after the second cleaning process.
도1은 종래기술에 따른 300밀리미터 실리콘 웨이퍼의 제조방법을 도시한 공정 흐름도.1 is a process flow diagram illustrating a method for manufacturing a 300 millimeter silicon wafer according to the prior art.
도2는 본 발명에 따른 300밀리미터 실리콘 웨이퍼의 제조방법을 도시한 공정 흐름도.2 is a process flow diagram illustrating a method of manufacturing a 300 millimeter silicon wafer in accordance with the present invention.
본 발명에 따른 실리콘 웨이퍼 제조방법은 실리콘 웨이퍼에 양면 연삭공정, 가장자리 노치부 연마공정, 열처리공정, 양면 연마공정, 세정공정, 가장자리 라운드부 연마공정, 세정, 마무리 연마공정을 순차적으로 실시하여 이루어진다.The silicon wafer manufacturing method according to the present invention is performed by sequentially performing a double-side grinding process, an edge notch polishing process, a heat treatment process, a double-side polishing process, a cleaning process, an edge round polishing process, a cleaning and a finish polishing process on the silicon wafer.
이하 첨부된 도면을 참조하여 본 발명에 따른 일 실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도2는 본 발명에 따른 실리콘 웨이퍼의 제조방법을 개략적으로 도시한 흐름도이다.2 is a flow chart schematically showing a method of manufacturing a silicon wafer according to the present invention.
도2에 도시된 바와같이, 초크랄스키 결정성장법 또는 플롯트존 결정성장법으로 실리콘 단결정 잉곳을 성장시킨 후, 잉곳을 얇게 절단하여 베어 웨이퍼를 제조한 후 가장자리가 일정한 형상을 가지도록 가장자리 연삭공정을 실시한다(S101). 여기서 가장자리(14)는 도3에서와 같이 가장자리 노치부(10)와 가장자리 라운드부(12)를 포함한다.As shown in Figure 2, after growing the silicon single crystal ingot by Czochralski crystal growth method or plot zone crystal growth method, after cutting the ingot thinly to produce a bare wafer edge grinding process so that the edge has a constant shape (S101). The edge 14 here comprises an edge notch 10 and an edge round 12 as in FIG.
그리고 본 발명에 따른 제조공정이 완료된 웨이퍼와 완료되지 않은 웨이퍼를 구분하기 위해 편의상 본 발명에 따른 제조공정이 완료된 웨이퍼를 실리콘 웨이퍼라 하고 제조공정이 완료되지 않은 웨이퍼를 베어 웨이퍼(bare wafer)라 한다.In addition, in order to distinguish between wafers in which the manufacturing process according to the present invention is completed and incomplete wafers, wafers in which the manufacturing process according to the present invention is completed are called silicon wafers, and wafers in which the manufacturing process is not completed are referred to as bare wafers. .
이후 베어 웨이퍼의 평탄도를 향상시키기 위해 베어 웨이퍼의 양면을 동시에 연삭하는 양면 연삭공정을 실시한다(S102).Thereafter, in order to improve the flatness of the bare wafer, a double-sided grinding process of simultaneously grinding both sides of the bare wafer is performed (S102).
양면 연삭공정 후 베어 웨이퍼의 가장자리 노치부를 다듬기 위한 노치부 연마공정을 실시한다(S013).After the double-sided grinding step, the notch part polishing step for trimming the edge notch of the bare wafer is performed (S013).
다음으로 노치부 연마공정이 완료된 베어 웨이퍼 내부에 존재하는 결함을 제거하기 위한 열처리를 실시한다(S104). 여기서 실시되는 열처리는 통상의 실리콘 웨이퍼를 제조하기 위해서 실시되는 열처리로서 상세한 설명은 생략한다.Next, a heat treatment is performed to remove defects existing in the bare wafer where the notch portion polishing process is completed (S104). The heat treatment carried out here is a heat treatment carried out to manufacture a normal silicon wafer, and detailed description thereof will be omitted.
그리고 열처리 공정이 완료된 베어 웨이퍼의 양면을 반도체 소자가 형성될 경면으로 만들기 위한 양면 연마공정을 실시한다(S105). 여기서 노치부 연마 공정시 형성되는 노치패드 마크가 제거된다.Then, a double-side polishing process is performed to make both surfaces of the bare wafer on which the heat treatment process is completed become a mirror surface on which the semiconductor element is to be formed (S105). Here, the notch pad mark formed during the notch part polishing process is removed.
양면 연마공정 후 양면 연삭공정 및 양면 연마공정으로 인해 발생된 불순물을 제거하고, 베어웨이퍼 표면에 산화막을 형성하기 위한 제1차 세정을 실시한다(S106).After the double-sided polishing process, impurities generated by the double-sided grinding process and the double-sided polishing process are removed, and first cleaning is performed to form an oxide film on the bare wafer surface (S106).
상기의 SC-1 세정액은 암모니아(NH4OH)와 과산화수소(H2O2)혼합액으로 암모니아 : 과산화수소를 1:1의 비율로 혼합하여 형성한다. 여기서 SC-1 세정액에 포함된 과산화수소로 인해 산화막이 형성된다.The SC-1 cleaning solution is a mixture of ammonia (NH 4 OH) and hydrogen peroxide (H 2 O 2), which is formed by mixing ammonia: hydrogen peroxide in a ratio of 1: 1. Here, an oxide film is formed due to hydrogen peroxide contained in the SC-1 cleaning liquid.
이렇게 형성된 산화막은 베어 웨이퍼의 보호막으로 사용되어 라운드부 연마시 사용되는 슬러리가 베어 웨이퍼의 표면에 흡착되는 것을 방지하고, 라운드부 연마 공정 후 베어 웨이퍼 표면에 얼룩(stain)이 남지 않도록 한다.The oxide film thus formed is used as a protective film of the bare wafer to prevent the slurry used in polishing the round part from being adsorbed on the surface of the bare wafer, and to prevent stains on the bare wafer surface after the round part polishing process.
또한, 이후 진행되는 라운드부 연마공정에 사용되는 각종 척으로 인해 베어 웨이퍼의 양면에 척마크가 형성되는 것을 방지할 수 있으며, 후면에 로봇 척마크 및 정렬기 척마크는 미약하게 형성되도록 한다.In addition, chuck marks may be prevented from being formed on both sides of the bare wafer due to various chucks used in the round part polishing process, and the robot chuck marks and the aligner chuck marks may be weakly formed on the rear surface.
다음으로 제1차 세정이 완료된 베어 웨이퍼 가장자리의 라운드부 거칠기를 감소시키기 위한 라운드부 연마공정을 실시한다(S107).Next, the round part polishing process is performed to reduce the roughness of the round part of the bare wafer edge where the first cleaning is completed (S107).
라운드부 연마공정 후 발생된 불순물을 제거하기 위해 SC-1세정액으로 세정하고 연속하여 불산으로 세정하는 제2차 세정공정을 실시한다(S108).In order to remove impurities generated after the round part polishing process, a second washing process of washing with SC-1 cleaning solution and subsequently with hydrofluoric acid is performed (S108).
마지막으로 가장자리 연마 공정 시 베어 웨이퍼 후면에 미약하게 형성된 로봇 척마크 및 정렬기 척마크를 제거하기 위해서 마무리 연마 공정(final polishing)을 실시한다(S109).Finally, in order to remove the robot chuck mark and the aligner chuck mark that are weakly formed on the back surface of the bare wafer during the edge polishing process, a final polishing process is performed (S109).
이때 마무리 연마 공정은 로봇 척마크 및 정렬 척마크가 형성된 면을 2㎛ 두께 만큼 제거하여 로봇 척마크 및 정렬 척마크가 완전히 제거되도록 하여 실리콘 웨이퍼의 제조를 완료한다.At this time, the finishing polishing process removes the surface on which the robot chuck mark and the alignment chuck mark are formed by 2 μm thickness to completely remove the robot chuck mark and the alignment chuck mark to complete the manufacture of the silicon wafer.
이상 기술된 본 발명에 따른 실리콘 웨이퍼의 제조방법은 종래기술의 가장자리 연마공정을 가장자리 노치부와 가장자리 라운드부로 구분하여 양면 연마 공전 전에 노치부 연마공정을 실시하고, 양면 연마공정 후에 라운드부 연마공정을 실시하여 노치부 가공시 발생되는 패드마크가 제거하여 고품질의 실리콘 웨이퍼를 제조할 수 있다.The method for manufacturing a silicon wafer according to the present invention described above divides the edge polishing process of the prior art into an edge notch and an edge round portion, and performs a notch polishing process before double-side polishing, and performs a round polishing process after a double-side polishing process. By removing the pad mark generated during notch processing, it is possible to manufacture a high quality silicon wafer.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010083120A KR20030053085A (en) | 2001-12-22 | 2001-12-22 | Method for fabricating silicon wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010083120A KR20030053085A (en) | 2001-12-22 | 2001-12-22 | Method for fabricating silicon wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20030053085A true KR20030053085A (en) | 2003-06-28 |
Family
ID=29577698
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020010083120A Abandoned KR20030053085A (en) | 2001-12-22 | 2001-12-22 | Method for fabricating silicon wafer |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20030053085A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100816198B1 (en) * | 2006-08-24 | 2008-03-21 | 동부일렉트로닉스 주식회사 | Wafers for Semiconductor Devices |
| US9293318B2 (en) | 2012-06-12 | 2016-03-22 | Sumco Techxiv Corporation | Semiconductor wafer manufacturing method |
| KR20180073451A (en) * | 2016-12-22 | 2018-07-02 | 호야 가부시키가이샤 | Mask blank substrate for manufacturing display device, mask blank and mask, and manufacturing method thereof |
| CN113178386A (en) * | 2021-04-22 | 2021-07-27 | 上海新昇半导体科技有限公司 | Chemical mechanical polishing method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10249689A (en) * | 1997-03-10 | 1998-09-22 | Tokyo Seimitsu Co Ltd | Wafer chamfering method and device |
| KR19990083128A (en) * | 1998-04-13 | 1999-11-25 | 다구마시로오 | Method for chamfering a wafer |
| KR20000047734A (en) * | 1998-11-27 | 2000-07-25 | 오하라 히로시 | Method for notch polishing by notch-polishing unit of edge polisher |
| JP2001044084A (en) * | 1999-07-30 | 2001-02-16 | Hitachi Cable Ltd | Semiconductor wafer |
| JP2002001636A (en) * | 2000-06-23 | 2002-01-08 | Memc Japan Ltd | Chamfering method for wafer |
-
2001
- 2001-12-22 KR KR1020010083120A patent/KR20030053085A/en not_active Abandoned
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10249689A (en) * | 1997-03-10 | 1998-09-22 | Tokyo Seimitsu Co Ltd | Wafer chamfering method and device |
| KR19990083128A (en) * | 1998-04-13 | 1999-11-25 | 다구마시로오 | Method for chamfering a wafer |
| KR20000047734A (en) * | 1998-11-27 | 2000-07-25 | 오하라 히로시 | Method for notch polishing by notch-polishing unit of edge polisher |
| JP2001044084A (en) * | 1999-07-30 | 2001-02-16 | Hitachi Cable Ltd | Semiconductor wafer |
| JP2002001636A (en) * | 2000-06-23 | 2002-01-08 | Memc Japan Ltd | Chamfering method for wafer |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100816198B1 (en) * | 2006-08-24 | 2008-03-21 | 동부일렉트로닉스 주식회사 | Wafers for Semiconductor Devices |
| US9293318B2 (en) | 2012-06-12 | 2016-03-22 | Sumco Techxiv Corporation | Semiconductor wafer manufacturing method |
| KR20180073451A (en) * | 2016-12-22 | 2018-07-02 | 호야 가부시키가이샤 | Mask blank substrate for manufacturing display device, mask blank and mask, and manufacturing method thereof |
| CN113178386A (en) * | 2021-04-22 | 2021-07-27 | 上海新昇半导体科技有限公司 | Chemical mechanical polishing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100394972B1 (en) | Epitaxially coated semiconductor wafer and process for producing it | |
| US5756399A (en) | Process for making semiconductor wafer | |
| US7829467B2 (en) | Method for producing a polished semiconductor | |
| KR100504098B1 (en) | silicon semiconductor wafer, and process for producing a multiplicity of semiconductor wafers | |
| TWI567811B (en) | Verfahren zum beidseitigen polieren einer halbleiterscheibe | |
| EP1852899A1 (en) | Method for manufacturing semiconductor wafer and method for mirror chamfering semiconductor wafer | |
| KR20190057394A (en) | Polishing method of silicon wafer and method of manufacturing silicon wafer | |
| JPH1092777A (en) | Manufacture of semiconductor wafer | |
| KR19990087978A (en) | Ultraflat silicon semiconductor wafer and process for the production of semiconductor wafers | |
| JP3943869B2 (en) | Semiconductor wafer processing method and semiconductor wafer | |
| EP0813931B1 (en) | Method of manufacturing semiconductor wafer | |
| US5904568A (en) | Method of manufacturing a semiconductor wafer | |
| KR20030053085A (en) | Method for fabricating silicon wafer | |
| US6211088B1 (en) | Manufacturing method for semiconductor gas-phase epitaxial wafer | |
| KR20040060990A (en) | Method for producing cemented wafer | |
| KR101062254B1 (en) | Manufacturing Method of Semiconductor Wafer | |
| JP3551300B2 (en) | Manufacturing method of high flatness wafer | |
| JP2003142434A (en) | Method of manufacturing mirror-surface wafer | |
| KR20030052465A (en) | Method for fabricating of silicon wafer | |
| KR20030047493A (en) | Method for cleaning of silicon wafer after grinding process | |
| KR100844435B1 (en) | Epitaxial Wafer Manufacturing Method | |
| KR20030053084A (en) | Method for fabricating silicon wafer | |
| KR980011977A (en) | Mirror-polished wafer manufacturing method | |
| KR20000060602A (en) | A methode of fabricating semiconductor wafer | |
| KR20020034475A (en) | Production method of semiconductor wafer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 20011222 |
|
| PA0201 | Request for examination | ||
| PG1501 | Laying open of application | ||
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 20030809 |
|
| NORF | Unpaid initial registration fee | ||
| PC1904 | Unpaid initial registration fee |