KR20030045547A - Error protection circuit in write signal of non destructive readout ferroelectric random access memory device and its application to the method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write signal error prevention circuit and a prevention method of a non-destructive readout non-ferroelectric random access memory (hereinafter referred to as "NDRO-FRAM"). Read / write signal error prevention circuit and prevention method of a non-destructive read type nonvolatile ferroelectric memory that includes a discharge nMOSFET for discharging a voltage applied to a write bit line connected to a gate of a read type nonvolatile ferroelectric memory to eliminate a write error of the memory It is about.

The write signal error protection circuit of the non-destructive read nonvolatile ferroelectric memory of the present invention includes a switch for receiving an address signal and outputting different voltages; A discharge nMOSFET which discharges the charge of the write bit line in accordance with the voltage.

Description

ERROR PROTECTION CIRCUIT IN WRITE SIGNAL OF NON DESTRUCTIVE READOUT FERROELECTRIC RANDOM ACCESS MEMORY DEVICE AND ITS APPLICATION TO THE METHOD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write signal error prevention circuit and a prevention method of a non-destructive readout non-ferroelectric random access memory (hereinafter referred to as "NDRO-FRAM"). A write signal error prevention circuit and a prevention method of a non-destructive read nonvolatile ferroelectric memory having a discharge nMOSFET for discharging a voltage applied to a write bit line connected to a gate of a read nonvolatile ferroelectric memory to eliminate a write error of the memory will be.

Fig. 1 shows symbols of NDRO-FRAM cells of one transistor type. Table 1 below shows operating characteristics of the NDRO-FRAM cell.

Gate (WBL) Drain (RWL) Source (RBL) Bulk (WWL) read Fluoring Vdd GND Fluoring Write ('1' / '0') + Vdd / -Vdd Fluoring Fluoring GND Standby Fluoring Fluoring Fluoring Fluoring

The gate is connected to a write bit line (WBL), the drain is connected to a read word line (RWL), the source is connected to a read bit line (RBL), and The bulk is connected to a write word line (WWL). In the standby state, all terminals are floating, in the write signal, the bit line of the selected cell is + Vdd or -Vdd, and the bulk is ground (GND). The bulk of the unselected cells remains fluorinated.

Fig. 2A shows a circuit diagram of a single transistor type NDRO-FRAM drive device, which includes a word line control circuit 20 for controlling read / write word lines, a bit line control circuit 21 for controlling write bit lines, and And a sensing circuit 22 for sensing a signal of each of the cells. The word line control circuit 20 and the bit line control circuit 21 receive column / row address signals from the outside and transmit data (0 or 1) to a cell at a specific position through a predetermined write driver (not shown). ), And the read operation of the data written on the cell at the specific position is performed through the sensing circuit 22.

FIG. 2B illustrates a circuit diagram of a single transistor type NDRO-FRAM cell array, and describes an error occurring in the circuit diagram. Assume that data '0' is written in the cells 2 and 2 once. In this state, data '1' is recorded in the cells 3 and 2. After the data '1' is written, the WBL2 is in a fluorinated state charged with a positive high voltage (+ Vdd). If the write operation is performed in the cells 2 and 3 before the charged voltage is discharged, the voltage applied to the terminals of the cells 2 and 2 is in the same state as when the '1' is written. That is, since the WBL2 becomes high and the bulk becomes ground, the data '0' previously written in the cells 2 and 2 is changed to '1'.

As such, circuits of conventional cell arrays do not have means and methods for discharging the voltage once charged to the bit lines, resulting in errors that alter the data values of other cells.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and unlike the driving of a general memory in performing a write operation on a single transistor type ferroelectric memory cell array, a signal must be applied in the fluorine state, and thus the write operation is performed. An object of the present invention is to provide a circuit and a method for effectively eliminating a write error caused by a bit line charged by a write operation before an operation. In particular, when different data values (0 or 1) are respectively written to memory cells connected to the same write bit line, the data operation of a specific memory cell writes the data value of another memory cell which writes different data values. It is an object of the present invention to provide a circuit and a method for preventing the change by

1 is a symbol of an NDRO-FRAM cell of one transistor type.

Fig. 2A is a circuit diagram of a single transistor type NDRO-FRAM cell driver.

Fig. 2B is a circuit diagram of an NDRO-FRAM cell array of one transistor type.

3 is a block diagram of a write signal error prevention circuit of an NDRO-FRAM cell array according to the present invention;

4A is a circuit diagram of one embodiment of a pulse generation circuit that is part of the switch in FIG.

4B is a circuit diagram of one embodiment of a level shifter that is part of the switch in FIG.

5A is a graph showing an embodiment of the operation result of the signal error prevention circuit according to the present invention;

5B is a graph showing another embodiment of the operation result of the signal error prevention circuit according to the present invention;

The write signal error prevention circuit of the non-destructive read nonvolatile ferroelectric memory of the present invention discharges a voltage applied to a write bit line connected to a gate of the non-destructive read nonvolatile ferroelectric memory according to a change of an address signal, and receives an address signal. A switch for outputting different voltages; A discharge nMOSFET which discharges the charge of the write bit line in accordance with the voltage.

The write signal error prevention method of the non-destructive read type nonvolatile ferroelectric memory of the present invention is a method of discharging a voltage applied to a write bit line connected to a gate of the non-destructive read type nonvolatile ferroelectric memory according to an address signal. Outputting different voltages; Discharging the charge of the write bit line according to the voltage.

3 is a block diagram illustrating a write signal error prevention circuit of an NDRO-FRAM cell array according to an exemplary embodiment of the present invention, wherein the switch 30 receives an address signal from an external source and is turned on / off by the switch. Is composed of a discharge nMOSFET 31. The switch 30 receives the address signal and applies predetermined voltages (+ Vdd / −Vdd) to the discharge nMOSFET 31. That is, according to the address signal, the switch 30 applies -Vdd to the gate of the discharge nMOSFET 31 to turn off the discharge nMOSFET 31, and thus has no effect on the WBL. Alternatively, the switch 30 applies + Vdd to the gate of the discharge nMOSFET 31 to turn on the nMOSFET 31 according to the address signal, thereby reducing the voltage of the WBL connected to the source of the discharge nMOSFET 31. It will be grounded. Therefore, the applied voltage of the WBL is discharged. The switch 30 may operate as a predetermined switch, particularly when there is a change in the address signal, that is, when there is a change from a low signal to a high signal or a high signal to a low signal.

FIG. 4A shows a circuit diagram of one embodiment of the pulse generation circuit of the signal error prevention circuit in FIG. 3, which includes inverters 410 to 413 and 415, and a NAND gate 414. When the write operation is completed at the address where the write is selected, the pulse generation circuit 41 applies a delayed address signal and a non-delayed signal to the NAND gate 414 to generate a short pulse corresponding to the delayed time. It is. In detail, the address signal is applied to the inverter 410 so that the inverted address signal is input to one terminal of the NAND gate 414 without delay, and the inverted address signal is the inverters 411 to 413. Is applied to the other terminal of the NAND gate 414 after being delayed by a predetermined time. When the address signal is the same signal (high or low), the same signal (high or low) is input to the NAND gate 414 so that a constant signal (high or low) is output. However, when the address signal is changed from high to low, that is, at the end of the write operation, high is directly input to one end of the NAND gate 414 and high is input to the other terminal, and a predetermined time is delayed. The row is entered later. Thus, a signal in which the output of the NAND gate 414 is low only for the predetermined time is output, and a signal, ie, a pulse, is generated by the inverter 415 only high for the predetermined time. In addition, while the signals at both ends are high, the output of the NAND gate 414 goes low and then goes high through the inverter 415. If the total number of the inverters 411 to 413 is an odd number, the configuration according to the present invention is satisfied. Alternatively, the pulse generating circuit 41 may be configured to generate a predetermined pulse not only by an address signal that changes from a high signal to a low signal but also by an address signal that changes from a low signal to a high signal by appropriate modification. It is extremely easy for a person skilled in the art.

FIG. 4B shows a circuit diagram of one embodiment of a level shifter of the signal error prevention circuit in FIG. 3, comprising: a first pMOS 421A receiving a pulse and having a drain connected to + Vdd; A third inverter (420) for inverting the pulse; A second pMOS 421B having a gate connected to the output of the third inverter 420 and having a drain connected to + Vdd; A first nMOSFET 422A connected to a source of the first pMOS 421A, a gate connected to the second pMOS 421B, and a bulk and a drain connected to -Vdd; A source is connected to the second pMOS 421B, a gate is connected to the source of the first pMOS 421A, and the bulk and drain are composed of a second nMOSFET 422B connected to -Vdd.

In addition, the gate of the discharge nMOSFET 43 is connected to the source of the second pMOS 421B, the drain is grounded, the bulk is connected to -Vdd, and the source is connected to a specific write bit line WBL. In general, WBL should be applied with both + Vdd and -Vdd due to the operating conditions of the memory cell.In this case, if -Vdd is applied with a general nMOSFET whose bulk is connected with the source to ground (GND) for discharge, This does not become -Vdd and falls to GND. To prevent this, the bulk of the discharge nMOSFET 43 is separated from the source and connected to -Vdd.

Referring to the operation of the level shifter 42, first, when the output from the pulse generation circuit 41 is high (+ Vdd), + Vdd is input to the gate of the first pMOS 421A to be turned off. The signal is inverted by the inverter 420 to the gate of the second pMOS 421B, whereby a low (-Vdd) signal is input. Therefore, since a high signal is input to the gate of the first nMOSFET 422A and the drain of the first nMOSFET 422A is connected to -Vdd, -Vdd is applied to the gate of the second nMOSFET 422B. Is turned off. Thus, + Vdd is applied to the gate of the discharge nMOSFET 43.

As described above, after performing a write operation of '0' or '1' to the memory cell selected by the address signal, the input of the gate of the discharge nMOSFET 43 is set at -Vdd at the instant the address signal falls low. By changing to + Vdd, the discharge nMOSFET 43 is turned on for a predetermined time of the pulse to discharge the charge of WBL.

When the output from the pulse generator 41 is low (-Vdd), a low signal is input to the gate of the first pMOS 421A, and the inverter (g) is applied to the gate of the second pMOS 422B. As the signal is inverted by 420, the high signal is input and turned off. The drain of the first pMOS 421A is connected to + Vdd so that + Vdd is input to the drain of the second nMOSFET 422B, and is connected to -Vdd of the gate of the second nMOSFET 422B. -Vdd is applied to the gate of the first nMOSFET 422A so that the first nMOSFET 422A is turned off. Therefore, -Vdd is applied to the gate of the discharge nMOSFET 43.

In this manner, the discharge nMOSFET 43 is kept in the off state in the state where the pulse is low, so that the input signal remains as selected even if the input signal (+ Vdd or -Vdd) is applied to the WBL for writing. To the cell. In addition, even in a standby state, the discharge nMOSFET 43 always maintains an off state to enable the WBL to maintain a fluorating state.

Figure 5a shows a graph showing an embodiment of the operation result of the signal error protection circuit according to the present invention. The upper graph of FIG. 5A shows the operation of the conventional memory cell array, and the lower graph of FIG. 5A shows the operation result of the signal error prevention circuit according to the present invention when writing '0' to the cells 2 and 2. . Referring to the upper graph, the section A is an operation of writing '0' to the cells 2 and 2, where RWL2 is fluorinated, WWL2 is grounded, and WBL2 is -Vdd. The interval B is an operation of writing '1' to the cells 3 and 2, and indicates that + Vdd is applied to WBL2. It also shows that WBL2 is fluorinated in a high state after writing the cells 3,2. Interval C is an operation of writing '1' to cells 2 and 3, where RWL2 is fluorinated, WWL2 is grounded, and WBL2 is charged high, and at this time, cells 2 and 2 The condition of writing '1' is established, indicating that an error occurs that changes the previously written information of '0' to '1'. Next, the lower graph will be described. The section A is the same as the upper graph, and in the section B, after performing a '1' write operation to the cells 3 and 2 (around 230 ns), the switch A pulse is generated through 30, and at this time, the discharge nMOSFET 31 is turned on to discharge all of the electric charges present in the WBL2, and the WBL2 continues continuously in the remaining sections B and C. Fluorides to zero volts. That is, in the period C, the cells 2 and 2 are fluorinated in the state in which RWL2 is fluorinated and WWL2 is grounded, and also in the state in which WWL2 is discharged, thereby not affecting the previously written information of '0'.

Figure 5b shows a graph showing another embodiment of the operation result of the signal error protection circuit according to the present invention. The upper graph of FIG. 5B shows the operation of the conventional memory cell array, and the lower graph of FIG. 5B shows the operation result of the signal error prevention circuit according to the present invention when writing '1' to the cells 2 and 2. . First, the upper graph will be described. An interval A is an operation of writing '1' to cells 2 and 2, where RWL2 is fluorinated, WWL2 is grounded, and WBL2 is + Vdd. The interval B is an operation of writing '0' to the cells 3 and 2, indicating that + Vdd is applied to the WBL2. It also shows that WBL2 is fluorinated in a low state after writing the cells 3,2. Interval C is an operation of writing '0' to cells 2 and 3, where RWL2 is fluorinated, WWL2 is grounded, and WBL2 is charged low. A condition that writes '0' is established, indicating that an error occurs that changes the information of the previously written '1' to '0'. Next, the lower graph will be described. The section A is the same as the upper graph, and after the '0' writing operation to the cells 3 and 2 in the section B (around 230 ns), the switch A pulse is generated through 30, and at this time, the discharge nMOSFET 31 is turned on to discharge all of the electric charges present in the WBL2, and the WBL2 continues continuously in the remaining sections B and C. Fluorides to zero volts. That is, in the section C, the cells 2 and 2 are fluorinated in the state in which RWL2 is fluorinated and WWL2 is grounded, and in the state in which WWL2 is discharged, so that the cells 2 and 2 do not affect the previously written information of '1'.

Through the above-described configuration of the present invention, since a signal must be applied in the fluorine state, unlike the driving of a general memory in performing a write operation on a single transistor type ferroelectric memory cell array, the write operation before the write operation is performed. There is an effect of effectively eliminating the write error caused by the bit line charged by using the change of the address signal. In particular, in the case of writing different data values (0 or 1) to memory cells connected to the same write bit line, respectively, the data value of a specific memory cell is the data value of another memory cell which writes different data values. There is an effect of preventing the interference between the memory cells, which is changed by the write operation.

Claims (12)

A switch configured to receive an address signal and output different voltages; And a discharge nMOSFET which discharges the charge of the write bit line in accordance with the voltage. The write signal error preventing circuit of the non-destructive read-type nonvolatile ferroelectric memory characterized by the above-mentioned. 2. The apparatus of claim 1, wherein the switch comprises: a pulse generation circuit for outputting a pulse in accordance with the address signal; And a level shifter for outputting different voltages according to the value of the pulse. 3. The write signal error protection circuit of claim 1 or 2, wherein the switch outputs the voltages according to the change of the address signal. 3. The method of claim 1 or 2, wherein the gate of the discharge nMOSFET is connected to the output of the level shifter, the drain is grounded, the bulk is connected to -Vdd, and the source is connected to the write bit line. A write signal error protection circuit of a non-destructive read nonvolatile ferroelectric memory. A write signal error prevention circuit of a non-destructive read type nonvolatile ferroelectric memory, comprising: a discharge element for discharging a write bit line in response to a change in an address signal. The method of claim 5, wherein the discharge circuit is a switch for outputting a predetermined voltage according to the change of the address signal, the gate is connected to the switch, the drain is grounded, the bulk is connected to -Vdd, the source is the write A write signal error protection circuit of a non-destructive read-type nonvolatile ferroelectric memory, which is connected to a bit line. Outputting different voltages according to the address signal; And discharging a charge of a write bit line according to the voltage. 8. The method of claim 7, wherein said outputting step comprises: generating a pulse in accordance with said address; And outputting different voltages according to the value of the pulse. The method of claim 7 or 8, wherein the outputting of the output voltage outputs different voltages according to a change of the address signal. 9. The discharging step of claim 7 or 8, wherein the discharging step is performed by a discharge nMOSFET whose gate is input with the different voltages, a drain is grounded, a bulk is connected to -Vdd, and a source is connected to a specific write bit line. And when the different voltage is + Vdd, the nMOSFET is turned on to discharge the charge of the write bit line, and when the different voltage is -Vdd, the nMOSFET is turned off to stop the discharge operation. To prevent write signal errors. And discharging the write bit line in response to a change in the address signal when the one discharge element is constituted by the cell elements of the memory array. 12. The method of claim 11, wherein the discharging step comprises: outputting a predetermined voltage according to a change in an address signal, a gate is connected to the output voltage, a drain is grounded, a bulk is connected to -Vdd, and a source is And a discharge element connected to the write bit line, wherein the write signal error prevention method of the non-destructive read nonvolatile ferroelectric memory is performed.