KR20030034638A - Power amplitude module - Google Patents

Abstract

The present invention relates to a power-saving power amplification module, comprising: a basic amplifier for amplifying the power of a signal input from the outside, a low power amplifier for amplifying the amplified signal of the basic amplifier to a desired size, and a plurality of transistors. When the signal input to the amplification unit is less than a predetermined set value is configured to operate simultaneously with the low power amplification unit and a high power amplification unit for amplifying the amplified signal of the basic amplification unit to a desired size,

The high power amplifier can be selectively operated by turning on / off the high power amplifier according to the size of the signal input to the basic amplifier. If the signal inputted to the basic amplifier is above a predetermined value, the power amplification can be reduced by turning off the high power amplifier to reduce power consumption. There is an effect that can increase the efficiency of the module.

Description

Power saving module

The present invention relates to a power-saving power amplification module, and in particular, when amplifying a signal input from the outside, it is possible to turn on / off the amplification unit operated according to the magnitude of the input signal, thereby reducing the current consumed to operate the amplification unit and thereby The present invention relates to a power saving power amplifier module with increased efficiency.

As the demand for terminals and communication devices increases due to the expansion of the communication market, there is a demand for communication devices that are small, lightweight, low power consumption, and can be used for a long time. There is a need for a technique for improving performance.

1 is a circuit diagram showing the configuration of a power amplifier according to the prior art.

The power amplification module according to the related art amplifies the basic amplification unit 10 to which a signal is input and amplified through the input terminal 11 from the outside, and amplifies the signal amplified by the basic amplification unit 10 to a signal having a desired size. An expansion amplifier 20, and a bias unit 30 for applying a bias current for setting the operating point so that the signal input to the basic amplifier 10 and the expansion amplifier 20 is amplified and transmitted. It is composed.

The basic amplifier 10 includes a first transistor Q1 for amplifying a signal input through the input terminal 11, a power supply terminal 13 for inputting operating power to the first transistor Q1, and the input terminal. The first matching unit 12 performs impedance matching between the first transistor Q11 and the first transistor Q1.

The expansion amplifier 20 may include second to fifth transistors Q2 to Q5 connected in parallel to amplify the amplified signal of the basic amplifier 10 to a signal having a desired size, and the second to fifth transistors Q2. A second matching unit 21 which performs impedance matching between the power supply terminal 22 to which the operating power is supplied to ˜Q5, and the second to fifth transistors Q2 to Q5 and the basic amplifier 10. ) And an output terminal 24 through which the signals amplified by the second to fifth transistors Q2 to Q5 are output, and between the second to fifth transistors Q2 to Q5 and the output terminal 24. A third matching unit 23 further performs impedance matching.

Meanwhile, the bias unit 30 includes a first bias unit 31 for supplying a bias current to the basic amplifier 10, and a second bias unit 32 for supplying a bias current to the expansion amplifier 20. It is composed of

FIG. 2 is a circuit diagram showing the configuration of the first bias portion of FIG.

The first bias unit 31 includes a plurality of transistors Q6 to Q8 and a plurality of resistors R1 to R4 to receive an operation signal through a reference signal input terminal 31a, and to supply the plurality of transistors Q6 to Q8. ) And the plurality of resistors R1 to R4 generate a bias current to supply a bias current to the first transistor Q1 of the basic amplifier 10 through a bias current output terminal 31b.

FIG. 3 is a circuit diagram showing the configuration of the second bias portion of FIG.

The second bias unit 32 includes a current mirror 33 including a plurality of transistors Q9 and Q10 and a resistor R5, a plurality of transistors Q11 to Q13, and resistors R6 to R9. The bias current is generated by the signal input through the operation signal input terminal 32a and the input is controlled to the current control terminal 32b according to the magnitude of the signal of the output terminal 24, wherein the magnitude of the output signal is one. Below the stationary, the current mirror 33 is operated, thereby reducing the bias current output through the bias current output terminal 32c.

When the size of the output terminal 24 is less than or equal to a predetermined value, the second bias unit 32 may reduce the bias current output through the bias current output terminal 32c to increase the amplification ratio of the expansion amplifier 20. When the output terminal 24 is reduced and the size of the output terminal 24 is greater than or equal to a predetermined value, the bias current output through the bias current output terminal 32c increases to increase the amplification ratio of the expansion expansion amplifier 20.

Referring to the operation of the power amplifier according to the prior art configured as described above are as follows.

First, power is supplied from the power supply terminals 13 and 22 of the basic amplifier 10 and the expansion amplifier 20 to operate the plurality of transistors Q1 to Q5, and the first An operation signal is input from the operation signal input terminals 31a and 32a of the bias unit 31 and the second bias unit 32 to generate a bias current in the first bias unit 31 and the second bias unit 32. .

When a signal is input from the outside through the input terminal 11, the impedance is matched by the first matching unit 12, amplified by the first transistor Q1, and input to the expansion amplifier 20.

The amplified signal input to the expansion amplifier 20 is input to the second to fifth transistors Q2 to Q5 by the second matching unit 21.

At this time, the bias current supplied to the second to fifth transistors Q2 to Q5 is controlled according to the magnitude of the signal output from the current control terminal 32b of the second bias unit 32 to the output terminal 24. Signal is inputted, the current supplied to the second to fifth transistors Q2 to Q5 is reduced to reduce the amplification rate, and when the signal output to the output terminal 24 is equal to or greater than a set value, the second to fifth The amplification factor is increased by increasing the bias current supplied to the transistors Q2 to Q5.

Signals amplified by the second to fifth transistors Q2 to Q5 are impedance-matched at the output terminal 24 and the third matching unit 23 output to the outside and are output to the outside.

However, in the operation of the power amplifier module according to the prior art, since the basic amplification unit and the entire amplification unit are operated before the signal is input to the basic amplification unit, the expansion amplifier is turned on and consumed until the signal is input to the basic amplification unit. There is a problem that the current is increased to reduce the efficiency of the power amplification module.

The present invention has been made to solve the above-mentioned problems of the prior art, the object of which is to control the plurality of transistors in the expansion amplifier for amplifying the amplified signal of the basic amplifier to be turned on / off according to the size of the external input signal By reducing the bias current consumed in the amplification of the signal, thereby increasing the efficiency of the power amplification module.

1 is a circuit diagram showing the configuration of a power amplification module according to the prior art;

FIG. 2 is a circuit diagram showing the configuration of the first bias portion of FIG. 1; FIG.

FIG. 3 is a circuit diagram showing the configuration of the second bias portion of FIG. 1;

4 is a circuit diagram showing the configuration of a power saving type power amplification module according to the present invention;

5 is a circuit diagram showing the configuration of a power saving type power amplification module according to the present invention;

6 is a circuit diagram showing a configuration of a bias unit according to the present invention;

7 is a graph showing the operation of the power amplification module of FIG.

8 is a graph illustrating the operation of the power amplification module of FIG.

<Explanation of symbols on main parts of the drawings>

40: basic amplifier Q14: first transistor

42: input stage matching section 44: intermediate matching section

45: basic bias unit 45a: operation signal input terminal

45b: bias current output stage 50: low power amplifier

Q15: second transistor 51: operating power supply stage

60: high power amplification unit C1: blocking unit

C2 to C4: matching capacitors Q16 to Q18: third, fourth and fifth transistors

61, 62: expansion bias unit 61a, 62a: operation signal input terminal

61b, 62b: bias current output stage

According to a feature of the power-saving power amplification module according to the present invention for solving the above problems, a basic amplifier for amplifying the power of the signal input from the outside, and a low power amplification for amplifying the amplified signal to a desired size And a high power amplifier configured to amplify the amplified signal of the basic amplifier by operating simultaneously with the low power amplifier, when the signal of the output terminal is formed of a plurality of transistors or more than a set value.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a circuit diagram showing the configuration of a power saving type power amplification module according to the present invention.

Power-saving power amplification module according to the present invention is a first transistor (Q14) that is amplified from the outside through the input terminal 41 and the basic bias unit 45 for supplying a bias current to the first transistor (Q14) The low power amplifier 50 comprising the basic amplifier 40 and the second transistor Q15 to which the output signal of the basic amplifier 40 is input and amplified, and the output signal of the output unit 64. When the size is more than a predetermined value, the high power amplifier 60 is configured to operate simultaneously with the low power amplifier 50 to amplify the output signal of the basic amplifier 40, wherein the high power amplifier 60 3 to 5 transistors Q16 to Q18.

The basic amplifier 40 includes a first matching unit 42 that performs impedance matching between the input terminal 41 and the first transistor Q14, the first transistor Q14, and the low power amplifier unit ( A second matching unit 44 which performs impedance matching of the second transistor Q15 of 50, and a basic bias unit which supplies a bias current to the first transistor Q14 and the second transistor Q15 ( 45, and the basic bias unit 45 is provided with an operation signal input terminal 44a through which a signal for determining whether the basic bias unit 45 is operated is input.

The low power amplifier 50 further includes a power supply terminal 51 to which operating power of the second to fifth transistors Q15 to Q18 is input.

On the other hand, the high power amplifying unit 60 is connected in parallel with the basic amplifying unit 40 when the signal output to the output terminal 64 is more than a predetermined value third to third simultaneously operating with the low power amplifying unit 50 5 transistors Q16 to Q18 and an expansion bias unit 61 for supplying bias currents of the third to fifth transistors Q16 to Q18. The expansion bias unit 61 is connected to the output terminal 64. When the output signal is greater than or equal to a predetermined value, the operation signal input terminal 61a to which a bias current is supplied to the third to fifth transistors Q16 to Q18 is input, the expansion bias unit 61 and the first Inductors L1 are formed between the third to fifth transistors Q16 to Q18 to perform impedance matching, and a plurality of inductors L1 are formed at the input terminals of the third to fifth transistors Q16 to Q18 to perform impedance matching. More capacitors (C2 to C5) It should.

In addition, the high power amplifier 60 has an output terminal 64 and the output terminal 64 and the low power and high power amplification unit to output the signal amplified by the low power amplification unit 50 and the high power amplification unit 60 A third matching unit 63 for impedance matching between 50 and 60 is further included.

For reference, when the plurality of expansion bias units 61 and 62 are used in the expansion amplifier unit 60, as shown in FIG. 5, bias currents are applied to the fourth and fifth transistors Q17 and Q18. A first expansion bias unit 61 for supplying and a second expansion bias unit 62 for supplying a bias current to the third transistor Q16 are formed, and the first and second expansion bias units 61 and 62 are provided. Operation signal input terminals 61a and 6b to which an operation signal is input are formed.

In addition, the third transistor Q16 and the fourth and fifth transistors Q17 are prevented from mutual interference due to the bias current supplied by the second expansion bias unit 62 and the first expansion bias unit 61, respectively. Blocking portion C5 made of a capacitor is formed.

FIG. 6 is a circuit diagram showing the configuration of the basic bias portion of FIG.

The basic and expansion bias units 45 may include a plurality of transistors Q19 to Q21 and a plurality of resistors R10 to R13 to determine whether the operation is performed by a signal input to the operation signal input terminal 45a. When the basic bias unit 45 is operated, a bias current is supplied to the first to fifth transistors Q14 to Q18 of the basic, low power and high power amplifiers 40, 50, and 60 by a bias current output terminal 45b. Done.

The basic bias unit 45 configured as described above has the same configuration as the first expansion bias unit 61 or the second expansion bias unit 62, so that the operation signal input terminal 45a of the basic bias unit 45 is The same function as the operation signal input terminal 61a, 62a of the first or second expansion bias unit 61, 62, and the bias current output terminal 45b of the basic amplifier 45 is the first or second 2 plays the same role as the bias current output terminals 61b and 62b of the expansion bias units 61 and 62.

Referring to the operation of the power amplification module according to the present invention configured as described above are as follows.

In the operation of the power saving type power amplification module according to the present invention, a bias current is supplied from the basic bias unit 45 to the basic amplifier 40 and the low power amplifier 50.

When an external signal is input through the input terminal 40, the first matching unit 42 amplifies an impedance with the first transistor Q14 and then amplifies and outputs the first transistor Q14.

The output signal is the low power amplifier 50 and the second matching unit 44 and

The impedance is matched with the expansion amplifier 60.

At this time, it is determined whether the expansion amplifier 60 is operated according to the magnitude of the signal of the output terminal 64. When a signal having a predetermined value P1 or less is input as shown in FIG. 61 is turned off, and the impedance matched signal in the second matching unit 44 is amplified by the second transistor Q15, thereby reducing the bias current consumed.

In addition, when the signal input through the output terminal 64 is greater than or equal to a predetermined set value P1, the expansion bias unit 61 is operated to consume the bias current in the expansion bias unit 61.

If a plurality of bias portions are formed in the high power amplifier 60 as shown in FIG. 6, as shown in FIG. 8, a plurality of predetermined set values P2 and P3 are formed and the output terminal 64 is formed. It is determined whether the second expansion bias unit 62 is operated by comparing the signal output through the first set value P2, and comparing the signal input through the input terminal 41 with the second set value P3. The operation of the first expansion bias unit 61 and the second expansion bias unit 62 is determined.

Finally, the signals amplified by the low power amplifier 50 and the high power amplifier 60 are matched to the output terminal 64 by the impedance of the third matching unit 63 and output through the output terminal 64.

Since the power-saving power amplification module of the present invention configured as described above can be selectively operated by turning on / off the high power amplification unit according to the magnitude of the signal input to the basic amplification unit, the high power amplifying unit is turned off when the output signal of the output stage is less than a predetermined value. This can reduce the bias current consumed.

In addition, since a plurality of bias units are formed in the high power amplifier unit to control the transistors according to the signals input to the basic amplifier unit, the power amplifier module can be easily manufactured and the bias current consumed can be reduced. This is effective to increase.

Claims (5)

A basic amplifier for amplifying the power of a signal input from the outside; A low power amplifier for amplifying the amplified signal to a desired size with the basic amplifier; And a high power amplifying unit configured to operate simultaneously with the low power amplifying unit to amplify the amplified signal of the basic amplifying unit to a desired size when the signal output to the output terminal is formed by a plurality of transistors. The method of claim 1, The power amplification module includes: a basic bias unit supplying a bias current to the basic amplifier and the low power amplifier; At least one expansion bias unit supplying a bias current to the plurality of transistors constituting the high power amplifier; And an operation signal input terminal to which a signal for determining whether to operate the basic and expansion bias units is input. The method of claim 2, The low power amplification unit and the high power amplification unit power saving power amplification module, characterized in that the blocking portion is formed to prevent mutual interference by the bias current supplied by the basic and expansion bias unit. The method according to claim 1 or 2, The plurality of transistors may be controlled by supplying a plurality of bias currents, and the power saving type power amplification module, characterized in that the blocking portion is formed between each transistor to prevent mutual interference by the bias current. The method of claim 2, And a matching capacitor configured to perform an impedance matching function at each input terminal of the plurality of transistors.