KR20030019823A - Apparatus and method for interfacing between block in ATM system - Google Patents

Abstract

PURPOSE: An interface method between blocks in an ATM(Asynchronous Transfer Mode) system and a device therefor are provided to implement a common hardware function part, like a rear card commonly using a cell-bus system and processing a physical layer, and to implement a common routine in a firmware driver, so as to solve problems of timing error and jitter generated by an interface with other blocks. CONSTITUTION: A CPU processor initializes and clears memories, such as a ROM(Read Only Memory), a local memory and a system memory, and initializes a buffer, an ATM multiplexer function part, a cell-bus interface function part and a rear card function part(ST11). Common cards divided into a system ID, a self ID and a card ID prepare for an initialization process to be performed by blocks(ST12,ST13). An ATM VP/VC(Virtual Path/Virtual Channel) table is managed by each block for the initialization of ATM SAR(Segmentation And Reassembly)(ST14). A load request is delivered to a loading block with an inherent VP/VC, and the loading block responds to the load request and performs loading for corresponding application(ST15). And the common cards accepting the corresponding application start OS(Operating System) while performing the application to be performed by each block and providing inherent functions of each block(ST16).

Description

Apparatus and method for interfacing between block in ATM system in ATM system

The present invention relates to a common card in a control station implemented as a CDMA ATM network and an algorithm thereof. In particular, the cell-bus scheme is commonly used as an internal block bus and a physical layer is used. Timing errors that can be generated by the interface with other blocks by implementing common hardware functions such as rear cards that handle layers, and by implementing common routines in the firmware driver The present invention relates to an inter-block interface device and an method thereof in an ATM system that can solve jitter.

1 is a reference model for Interoperability Specification (IOS) 4.0, which is being standardized in a general 3rd Generation Partnership Project (3GPP) 2 TSG-A, and includes Layer 1 (Physical Layer) and Layer 2 (Data link). Layer (Data Link Layer) is shown as a network configured in Asynchronous Transfer Mode (ATM), wherein the IOS is not defined for Layer 1 (Physical Layer) and Layer 2 (Data link Layer).

Briefly, the network configured in FIG. 1 includes a mobile station (MS) 10, a base station (BTS) 20, a control station (BSC) 30, and PDSN (Packet Data). Service Node (Packet Data Service Node) 40, and the switching center (MSC, Mobile Switching Center) (50), the operation principle thereof will be described as follows.

First, the mobile station 10 is a mobile subscriber station and has a wireless connection with a base station, and is characterized by mobility.

The base station 20 performs a wired / wireless connection function between the mobile station 10 and the control station 30, code division multiple access (CDMA) signal processing, a wireless connection function with the mobile station 10, and the like.

The control station 30 performs mobile call control, handoff control for voice calls, channel allocation and power control functions for CDMA voice data processing.

When there is a packet service request from the mobile station 10, the PDSN (packet data service node) 40 performs packet service by a procedure defined with the mobile station 10. That is, an IP (Internet Protocol) address is assigned to the mobile station 10 to provide a packet data service, and packet handoff is performed according to a change in the location of the mobile station 10.

Next, the switching center 50 performs functions such as handoff, paging, roaming, and subscriber authentication of the circuit switching method based on the circuit switching between the mobile subscribers and the incoming and outgoing relay call processing functions.

In this network configuration, the voice communication output through the mobile station during communication in the network is matched with the PSTN network through the base station, the control station, and the switching station, and the data communication is performed through the base station, the control station, the PDSN, and its own data network. It is matched with internet network or other packet network.

On the other hand, in the conventional mobile communication network as described above, various types of cards are mounted to perform various functions in the control station, and the mounting of the cards is implemented by the designer's personality and diversity when the designer implements the interface. Therefore, implementing a block-to-block interface requires a lot of time and effort, and because the hardware format is different for each designer, it is difficult to understand each block unless the person in charge is responsible for it, and thus it is very inefficient in operation. Have problems.

Accordingly, the present invention is proposed to solve the above problems of the prior art,

An object of the present invention is to implement a common hardware function such as a rear card (Rear Card) that uses the cell-bus (Common-Bus) method as an internal block bus in common and processes the physical layer (Firmware) By implementing a common routine in the driver, an inter-block interface device in an ATM system that can solve timing errors and jitter that may be caused by an interface with another block. To provide that method.

The present invention for achieving the above object,

A CPU module comprising a central processing unit (CPU), a memory, an ATM, and an Ethernet matching unit and performing ATM segmentation and reassembly (SAR) and various applications;

Universal Test and Operations PHY Interface for ATM (UTOPIA) Level 1 interface is a multiplexing function of the CPU module and other matching units of the Cell-Bus interface processing unit and rear card described below. An ATM multiplexer (MUX) responsible for

A cell-bus interface processing unit which communicates with other cards and serves as an ATM switch,

The ATM system is configured to process the physical layer (Physical Layer) through the other block and cable (cable) to perform the ATM communication at various speeds comprising a rear card (Rear Card) unit, characterized in that it is configured as an inter-block interface device Configured is characterized by its structural configuration.

In addition, the present invention for achieving the above object,

The CPU processing unit initializes and clears memories such as ROM (Local Only), System Memory (System Memory), and buffer initialization and ATM MUX functions. Starting initialization of the secondary, cell-bus interface function, and rear card function;

After the initialization, distinguishing a system ID from a self ID and a card ID, and performing an initialization process to be executed for each block of the distinguished common cards;

After the initialization, performing ATM segmentation and reassembly (SAR) initialization to manage an ATM VP / VC (Virtual Path / Virtual Channel) table to be performed by each block in a state in which each block is recognized;

After the ATM SAR initialization is completed, requesting a load to a loading block with a unique VP / VC;

Giving a response to the load request in the loading block receiving the loading request and loading the corresponding application;

The method is characterized in that it comprises a step of operating an operating system (OS Start) in the common card loaded with the corresponding application to perform the application to be performed by each block and the unique function of each block.

1 is a diagram showing a network configuration of a general ATM system,

2 is a block diagram of a card used as a common card according to the present invention;

3 is a diagram showing a mounting state of a common card in the control station system according to the present invention;

4 is a view showing an example of a planar configuration diagram of a common card according to the present invention,

5 is a diagram illustrating a process of performing an application corresponding to a block recognition in a common card according to the present invention.

<Explanation of symbols for the main parts of the drawings>

100 ..... CPU Module

200 ..... ATM Multiplexer

300 ..... Cell-Bus Interface Unit

400 ..... Rear Card

500 ..... Other Card

Hereinafter, preferred embodiments of the "inter-block interface device and method thereof in the ATM system" according to the present invention will be described in detail with reference to the accompanying drawings.

2 shows a block diagram of a card used as a common card according to the present invention.

As shown therein, the CPU module 100 includes a central processing unit (CPU), a memory, an ATM, and an Ethernet matching unit, and segmentation and reassembly (ATMASAR); The lower sublayer of the ATM Adaptation Layer (AAL) of the AAL, which divides the data unit from the Convergence Sublayer (CS), which is the upper AAL sublayer, into multiple cells, passes the data unit to the ATM layer, or, conversely, a cell received from the ATM layer to the original data unit. Assemble and hand it to CS).

The ATM multiplexer (MUX) 200 is a Universal Test and Operations PHY Interface for ATM (UTOPIA) Level 1 interface, and the CPU module 100, the Cell-Bus interface processing unit 300, and the rear, which will be described later. It is responsible for the multiplexing function with other matching units such as a card (Rear Card) 400.

The cell-bus interface processor 300 communicates with another card 500 by using a chip called Transbit Co., Ltd., as a chip inside a block called cell-bus, and serves as a kind of ATM switch.

The rear card unit 400 processes ATM physical layers and performs ATM communication at various speeds through different blocks and cables (OC-3 (155Mbps), OC-12 ( 622 Mbps).

Other Card 500 is a card used in the same block, and is configured with a function unit that performs the same function as the above-described block.

3 is a diagram showing a mounting state of a common card in the control station system according to the present invention.

First, the vocoder / selector block, the clock interface block, the base station interface block, and the ATM switch blocks each use a dedicated hardware processor to perform a unique function. For example, the vocoder and the selector block use a digital signal processor (DSP) for speech processing.

Other Common Cards available blocks include: Call Control Processor (CCP), Selector for Data Service, Packet Control Function, PCF Processor, and Base Station Interface As such, the blocks do not need a dedicated hardware function, and represent blocks according to application performance. In addition, the processor recognizes each block in initialization, and receives an application for performing a function from a loading block to start an operating system (OS).

As shown in FIG. 3, a CCP block is a block in which an ATM interface is a main dedicated hardware processor and performs call control for voice or data services, and a selector block for the data service is connected to an ATM interface. The clock input unit is used as the main dedicated hardware processing unit, and serves as an interface between the base station and the PCF block.

Next, the PCF block is a block that uses an ATM interface and a LAN interface as main dedicated hardware processing units and processes a protocol for data service processing.

Next, the PCF processor block uses the ATM interface as the main dedicated hardware processing unit, and plays a role of call control and resource allocation for data services.

Next, the base station interface block uses the ATM interface as the main dedicated hardware processing unit, and plays a role of control and resource allocation on the interface between the base station and the control station.

Meanwhile, a block used as a common card is configured to use an internal bus called a cell bus in the 'Mid Plane' as shown in the common card plan view of FIG. Use the same rear card.

When the common card is mounted in the system as shown in FIG. 3 or powered up, the respective cards are recognized and the corresponding application is executed. The procedure will be described with reference to FIG. 5. Is as follows.

5 is a diagram illustrating a process of performing an application corresponding to a block recognition in a common card according to the present invention.

As shown therein, an operation (ST11) of initializing input / output of a memory and a buffer and determining whether a system ID or a self ID is used to distinguish the common card after the initialization is performed. Steps ST12 and ST13, if the determination result is a self ID, performing ATM segmentation and reassembly (SAR) initialization (ST14), and requesting a load to the loading block after the initialization (Load Request). Step ST15, and driving the operating system after the load request (ST16).

A block recognition procedure having such a configuration will be described in more detail as follows.

First, the CPU processing unit initializes and clears memories such as read only memory (ROM), local memory, and system memory, and also initializes buffers and buffers. Initialization of the ATM multiplexer (MUX) function, the cell-bus interface function, and the rear card function is started (ST11).

Here, each of the blocks can be distinguished by a combination of a system ID, a self ID, and a card ID. For example, the difference between the CCP block and the PCF block may be different from each other by the system ID. Each PCF may be distinguished by the system ID but the self ID and the card ID. The system ID and the self ID can be artificially distinguished by installing a switch in the attached Mid Plane of FIG. 4, and the card ID is fixed by a circuit to the Mid Plane of FIG. Make sure the ID is recognized.

Meanwhile, common cards distinguished by the system ID, the self ID, and the card ID prepare for an initialization process to be executed for each block (ST12, ST13).

Next, the ATM segmentation and reassembly (SAR) initialization is performed. In the process, the ATM VP / VC (virtual path / virtual channel) table to be performed by each block is already managed in a state where blocks have been recognized (ST14).

Next, when the initialization of the ATM SAR is completed, a load request is made to the loading block with a unique VP / VC. In this case, the loading block gives a response to the load request and loads a corresponding application. To perform (ST15).

Next, the common card loaded with the corresponding application performs an application to be performed by each block while operating an operating system (OS Start), and performs a unique function of each block (ST16).

According to the above-described "inter-block interface device and method in the ATM system" described above, the same firmware driver using a common bus using the same hardware, such as a cell-bus interface function unit, ATM multiplexer function unit, etc. By performing the driver initialization of the routine, there is an advantage in that timing errors due to the use of different clock drivers / buffer drivers, which may be generated by the interface with other blocks, may be solved.

In addition, in ATM communication generated by different firmware drivers, that is, differences between parameters (Peak Cell Rate (SCR), Sustain Cell Rate (SCR), and Cell Delay Variance Tolerance (CVT)) used for UPC (Usage Parameter Control) It has the advantage of solving problems such as jitter (how much each bit has moved forward or backward in the time position where it should be in digital transmission).

In addition, the development time due to the reduction of the card type, test and debugging (debugging), and the development cost reduction due to the efficient staffing in operation, the ease of material acquisition and ease of quality control in using the same material It has the advantage of managing additional economic effects and efficient personnel / quality.

Claims (2)

In an inter-block interface device in an ATM system, A CPU module comprising a central processing unit (CPU), a memory, an ATM, and an Ethernet matching unit, and performing ATM segmentation and reassembly (SAR) and various applications; Universal Test and Operations PHY Interface for ATM (UTOPIA) Level 1 interface is a multiplexing function of the CPU module and other matching units of the Cell-Bus interface processing unit and rear card described below. An ATM multiplexer (MUX) in charge of; A cell-bus interface processing unit communicating with another card and serving as an ATM switch; An inter-block interface device in an ATM system, comprising a rear card unit that processes ATM physical layers and performs ATM communication at various speeds through different blocks and cables. In the ATM system, the corresponding application execution method after recognizing each block, The CPU processing unit initializes and clears memories such as ROM (Read Only Memory), Local Memory, and System Memory, and buffer initialization and ATM MUX functions. Starting initialization of the unit, the cell-bus interface function unit and the rear card function unit; After the initialization, distinguishing a system ID from a self ID and a card ID, and then performing an initialization process to be executed for each of the distinguished common cards; After the initialization, performing ATM segmentation and reassembly (SAR) initialization to manage an ATM VP / VC (Virtual Path / Virtual Channel) table to be performed by each block in a state where the block-by-block recognition is completed; After the ATM SAR initialization is completed, requesting a load to a loading block with a unique VP / VC; Giving a response to the load request in the loading block receiving the loading request and loading the corresponding application; Inter-block interface in an AMT system, comprising: operating an operating system from a common card loaded with the corresponding application to perform an application to be performed by each block and a unique function of each block Way.