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KR20030012192A - A window chip scale package having stacked dies - Google Patents

A window chip scale package having stacked dies Download PDF

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Publication number
KR20030012192A
KR20030012192A KR1020010046109A KR20010046109A KR20030012192A KR 20030012192 A KR20030012192 A KR 20030012192A KR 1020010046109 A KR1020010046109 A KR 1020010046109A KR 20010046109 A KR20010046109 A KR 20010046109A KR 20030012192 A KR20030012192 A KR 20030012192A
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South Korea
Prior art keywords
die
bonding
substrate
bonding pad
dies
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KR1020010046109A
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Korean (ko)
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조중찬
차상석
이수남
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주식회사 심텍
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    • H—ELECTRICITY
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    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
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    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0652—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명의 목적은 기판의 다이접착면상에 센터본딩패드를 갖는 제1다이를 접착시키고, 상기 제1다이상에 에지본딩패드를 갖는 제2다이를 접착시켜 구성함으로써, 몰딩공정시 상기 제1 및 제2다이의 본딩와이어의 단락을 방지하고 반도체 칩의 점유면적을 감소시킨 다이 적층형 윈도우 칩 스케일 패키지를 제공하는데 있다.An object of the present invention is to bond a first die having a center bonding pad to a die bonding surface of a substrate, and to bond a second die having an edge bonding pad to the first die, thereby forming the first and second dies during the molding process. The present invention provides a die stacked window chip scale package which prevents shorting of a bonding wire of a second die and reduces an occupied area of a semiconductor chip.

본 발명은 인쇄회로기판(21); 상기 기판(21)상의 다이접착면에 다이접착필름(22)에 의해 본딩패드가 하부로 향하도록 접착된 센터본딩패드를 갖는 제1다이(23); 상기 제1다이상에 본딩패드가 상부로 향하도록 접착된 에지본딩패드를 갖는 제2다이(24); 상기 제1다이(23)의 본딩패드와 기판(21)하부의 회로배선 패턴을 전기적으로 연결시키는 제1본딩와이어(25); 상기 제2다이(24)의 본딩패드와 기판(21)상부의 회로배선 패턴을 전기적으로 연결시키는 제2본딩와이어(26); 외부로부터의 오염을 막기 위해 상기 제1 및 제2다이(23, 24)와 제2본딩와이어(26)를 일체적으로 몰딩하고, 상기 기판(21)하부의 윈도우(31)부분을 몰딩하는 EMC(27); 외부와의 전기적 접속을 위해 상기 솔더볼 랜드(28)상에 부착되어 있는 솔더볼(29)을 포함한 것을 특징으로 한다.The present invention is a printed circuit board 21; A first die 23 having a center bonding pad bonded to the die bonding surface on the substrate 21 so that the bonding pad faces downward by a die bonding film 22; A second die 24 having an edge bonding pad bonded on the first die with the bonding pad facing upwards; A first bonding wire 25 electrically connecting the bonding pad of the first die 23 to the circuit wiring pattern under the substrate 21; A second bonding wire 26 electrically connecting a bonding pad of the second die 24 to a circuit wiring pattern on the substrate 21; EMC to integrally mold the first and second dies 23 and 24 and the second bonding wire 26 to prevent contamination from the outside, and to mold a portion of the window 31 under the substrate 21. (27); It characterized in that it comprises a solder ball (29) attached to the solder ball land 28 for electrical connection to the outside.

Description

다이 적층형 윈도우 칩 스케일 패키지{A window chip scale package having stacked dies}A window chip scale package having stacked dies}

본 발명은 다이 적층형 윈도우 칩 스케일 패키지에 관한 것으로서, 특히, 기판의 다이접착면상에 센터(center) 본딩패드를 갖는 제1다이를 접착시키고, 상기 제1다이상에 에지(edge) 본딩패드를 갖는 제2다이를 접착시켜 구성함으로써, 몰딩공정시 상기 제1 및 제2다이의 본딩와이어의 단락을 방지하고 반도체 칩의 점유면적을 감소시킨 다이 적층형 윈도우 칩 스케일 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a die stacked window chip scale package, in particular, bonding a first die having a center bonding pad on a die attaching surface of a substrate, and having an edge bonding pad on the first die. The present invention relates to a die stacked window chip scale package in which a bonding die is formed to prevent shorting of the bonding wires of the first and second dies during the molding process and to reduce the occupied area of the semiconductor chip.

최근 전자제품이 소형화됨에 따라 제품내에 실장되는 반도체 소자 또한 고집적화 및 소형화의 요구가 증가되고 있는 추세이다. 이러한 추세에 발맞추어 한정된 크기의 기판상에 보다 많은 수의 반도체 칩을 실장하기 위해 반도체 패키지의 크기 및 두께를 감소시키기 위한 연구가 활발하게 이루어지고 있으며, 그 연구결과의 한예로 칩 스케일 패키지가 있다.With the recent miniaturization of electronic products, the demand for high integration and miniaturization of semiconductor devices mounted in products is also increasing. In response to this trend, studies are being actively conducted to reduce the size and thickness of semiconductor packages in order to mount a larger number of semiconductor chips on a limited sized substrate. An example of the research results is a chip scale package.

칩 스케일 패키지는 반도체 소자의 크기를 패키지 내부의 반도체 칩 크기와 거의 유사하게 제작하여 반도체 소자의 점유면적을 줄인 것이다.The chip scale package reduces the footprint of the semiconductor device by making the size of the semiconductor device almost similar to the size of the semiconductor chip inside the package.

최근에는 이러한 칩 스케일 패키지의 개발로 복수개의 반도체 칩을 단일 기판상에 적층시켜 반도체 칩의 점유면적을 감소시킨 다이 적층형 칩 스케일 패키지가 제작되고 있다.Recently, with the development of such a chip scale package, a die stacked chip scale package is manufactured in which a plurality of semiconductor chips are stacked on a single substrate to reduce the footprint of the semiconductor chip.

종래의 다이 적층형 윈도우 칩 스케일 패키지가 도 1에 도시되어 있다.A conventional die stacked window chip scale package is shown in FIG.

도 1은 종래의 다이 적층형 칩 스케일 패키지의 측단면도이다.1 is a side cross-sectional view of a conventional die stacked chip scale package.

도면과 같이, 기판(11) 상부의 다이접착면에는 다이접착필름(12)에 의해 센터본딩패드를 갖는 제1다이(13)가 본딩패드를 상부로 향하여 접착되고, 상기 제1다이(13)상에는 센터본딩패드를 갖는 제2다이(14)가 본딩패드를 상부로 향하도록 다이접착필름(12)에 의해 접착되어 있다.As shown in the drawing, a first die 13 having a center bonding pad is adhered to the die attaching surface on the substrate 11 by the die attaching film 12 with the bonding pad facing upward, and the first die 13 is attached to the die attaching surface 12. On the top, a second die 14 having a center bonding pad is bonded by the die adhesive film 12 so that the bonding pad is directed upward.

또, 제1본딩와이어(15)에 의해 상기 제1다이(13)의 본딩패드와 기판(11)상의 회로배선 패턴이 전기적으로 연결되고, 제2본딩와이어(16)에 의해 상기 제2다이(14)의 본딩패드와 기판(11)상의 회로배선 패턴이 전기적으로 연결되어 있다.In addition, a bonding pad of the first die 13 and a circuit wiring pattern on the substrate 11 are electrically connected by the first bonding wire 15, and the second die is connected by the second bonding wire 16. The bonding pad of 14 and the circuit wiring pattern on the board | substrate 11 are electrically connected.

상기 기판(11)상부의 회로배선 패턴은 비아홀(20)을 통하여 기판(11)하부의 솔더볼 랜드(18)와 연결되어 있어, 솔더볼 랜드(18)상에 부착되어 있는 솔더볼(19)에 의해 외부와 전기적으로 접속될 수 있도록 되어 있다.The circuit wiring pattern on the substrate 11 is connected to the solder ball lands 18 below the substrate 11 through the via holes 20 and externally connected by the solder balls 19 attached on the solder ball lands 18. It can be connected electrically with.

또한, 상기 제1 및 제2다이(13, 14)와 본딩와이어(15, 16)는 외부로부터의 오염을 막기 위해 EMC(Epoxy Molding Compound)(17)로 몰딩되어 있다.In addition, the first and second dies 13 and 14 and the bonding wires 15 and 16 are molded with an epoxy molding compound (EMC) 17 to prevent contamination from the outside.

그러나, 상기와 같은 종래의 다이 적층형 윈도우 칩 스케일 패키지에서는 다이의 본딩패드와 기판의 회로배선 패턴을 연결하기 위한 본딩 와이어(16, 17)의 길이가 길어지기 때문에 EMC(17)에 의한 몰딩공정중 본딩 와이어(16, 17)간의 단락이 발생하는 등의 신뢰성 문제가 있었다.However, in the conventional die stacked window chip scale package as described above, the length of the bonding wires 16 and 17 for connecting the bonding pads of the die and the circuit wiring pattern of the substrate becomes long. There was a reliability problem such as a short circuit between the bonding wires 16 and 17.

상기의 문제점을 해결하기 위한 본 발명의 목적은 기판의 다이접착면상에 센터본딩패드를 갖는 제1다이를 접착시키고, 상기 제1다이상에 에지본딩패드를 갖는 제2다이를 접착시켜 구성함으로써, 몰딩공정시 상기 제1 및 제2다이의 본딩와이어의 단락을 방지하고 반도체 칩의 점유면적을 감소시킨 다이 적층형 윈도우 칩 스케일 패키지를 제공하는데 있다.An object of the present invention for solving the above problems is by bonding a first die having a center bonding pad on the die bonding surface of the substrate, and by bonding a second die having an edge bonding pad on the first die, The present invention provides a die stacked window chip scale package which prevents shorting of the bonding wires of the first and second dies and reduces the footprint of the semiconductor chip during the molding process.

도 1은 종래의 다이 적층형 칩 스케일 패키지의 측단면도,1 is a cross-sectional side view of a conventional die stacked chip scale package;

도 2는 본 발명의 제1실시예에 의한 다이 적층형 윈도우 칩 스케일 패키지의 측단면도,2 is a side cross-sectional view of a die stacked window chip scale package according to a first embodiment of the present invention;

도 3은 본 발명의 제2실시예에 의한 다이 적층형 윈도우 칩 스케일 패키지의 측단면도.3 is a side cross-sectional view of a die stacked window chip scale package according to a second embodiment of the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

11, 21 : 기판12, 22 : 다이접착필름11, 21: substrate 12, 22: die adhesive film

13, 23 : 제1다이14, 24 : 제2다이13, 23: 1st die 14, 24: 2nd die

15, 25 : 제1본딩와이어16, 26 : 제2본딩와이어15, 25: first bonding wire 16, 26: second bonding wire

17, 27 : EMC18, 28 : 솔더볼 랜드17, 27: EMC18, 28: solder ball land

19, 29 : 솔더볼20, 30 : 비아홀19, 29: solder ball 20, 30: via hole

31 : 윈도우31: Windows

상기 목적을 이루기 위해 본 발명은 상부 및 하부에 형성된 회로배선패턴, 중앙에 관통된 윈도우, 상부 및 하부의 회로배선패턴을 연결시키기 위한 비아홀 및 하부에 형성된 솔더볼 랜드를 구비한 인쇄회로기판; 상기 기판상의 다이접착면에 다이접착필름에 의해 본딩패드가 하부로 향하도록 접착된 센터본딩패드를 갖는 제1다이; 상기 제1다이상에 본딩패드가 상부로 향하도록 다이접착필름에 의해 접착된 에지본딩패드를 갖는 제2다이; 상기 제1다이의 본딩패드와 기판하부의 회로배선 패턴을 전기적으로 연결시키는 제1본딩와이어; 상기 제2다이의 본딩패드와 기판상부의 회로배선 패턴을 전기적으로 연결시키는 제2본딩와이어; 외부로부터의 오염을 막기 위해 상기 제1 및 제2다이와 제2본딩와이어를 일체적으로 몰딩하고, 상기 기판하부의 윈도우 부분을 몰딩하는 EMC; 외부와의 전기적 접속을 위해 상기 솔더볼 랜드상에 부착되어 있는 솔더볼을 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the present invention provides a printed circuit board having a circuit wiring pattern formed on the upper and lower portions, a window penetrated in the center, a via hole for connecting the upper and lower circuit wiring patterns, and a solder ball land formed on the lower portion; A first die having a center bonding pad bonded to the die bonding surface on the substrate by a die bonding film such that the bonding pad faces downward; A second die having an edge bonding pad bonded to the first die by a die bonding film so that the bonding pad faces upward; A first bonding wire electrically connecting the bonding pad of the first die and the circuit wiring pattern under the substrate; A second bonding wire electrically connecting the bonding pad of the second die and the circuit wiring pattern on the substrate; An EMC for integrally molding the first and second dies and the second bonding wires to prevent contamination from the outside, and molding the window portion of the lower substrate; It characterized in that it comprises a solder ball attached to the solder ball land for electrical connection to the outside.

또한, 본 발명은 상부 및 하부에 형성된 회로배선패턴, 복수의 윈도우, 상부 및 하부의 회로배선패턴을 연결시키기 위한 비아홀 및 하부에 형성된 솔더볼 랜드를 구비한 인쇄회로기판; 상기 기판상의 복수의 다이접착면에 다이접착필름에 의해 본딩패드가 하부로 향하도록 접착된 센터본딩패드를 갖는 복수개의 제1다이; 상기 복수개의 제1다이 상부 각각에 본딩패드가 상부로 향하도록 다이접착필름에 의해 접착된 에지본딩패드를 갖는 복수개의 제2다이; 상기 제1다이 각각의 본딩패드와 기판하부의 회로배선 패턴을 전기적으로 연결시키는 제1본딩와이어; 상기 제2다이 각각의 본딩패드와 기판상부의 회로배선 패턴을 전기적으로 연결시키는 제2본딩와이어; 외부로부터의 오염을 막기 위해 상기 복수개의 제1 및 제2다이와 제2본딩와이어를 일체적으로 몰딩하고, 상기 기판하부의 복수의 윈도우 부분을 몰딩하는 EMC; 외부와의 전기적 접속을 위해 상기 솔더볼 랜드상에 부착되어 있는 솔더볼을 포함하여 이루어진 것을 특징으로 한다.In addition, the present invention is a printed circuit board having a circuit wiring pattern formed on the upper and lower portions, a plurality of windows, via holes for connecting the upper and lower circuit wiring patterns and a solder ball land formed on the lower portion; A plurality of first dies having a center bonding pad bonded to the plurality of die bonding surfaces on the substrate such that the bonding pads face downward by a die bonding film; A plurality of second dies having edge bonding pads bonded to each of the plurality of first dies by a die-adhesive film such that bonding pads face upwards; A first bonding wire electrically connecting the bonding pads of the first die to the circuit wiring patterns under the substrate; Second bonding wires electrically connecting the bonding pads of the second die to the circuit wiring patterns on the substrate; EMC integrally molding the plurality of first and second dies and the second bonding wires to prevent contamination from the outside, and molding the plurality of window portions under the substrate; It characterized in that it comprises a solder ball attached to the solder ball land for electrical connection to the outside.

이하, 첨부된 도면을 참조하여 본 발명을 좀 더 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in more detail the present invention.

도 2는 본 발명의 제1실시예에 의한 다이 적층형 윈도우 칩 스케일 패키지의 측단면도이다.2 is a side cross-sectional view of a die stacked window chip scale package according to a first embodiment of the present invention.

도면과 같이, 기판(21) 상부의 다이접착면에는 다이접착필름(22)에 의해 센터본딩패드를 갖는 제1다이(23)가 본딩패드를 하부로 향하도록 하여 접착되고, 상기 제1다이(23)상에 에지본딩패드를 갖는 제2다이(24)가 본딩패드를 상부로 향하도록 하여 다이접착필름(22)에 의해 접착되어 있다.As shown in the drawing, a first die 23 having a center bonding pad is bonded to the die attaching surface on the substrate 21 by the die attaching film 22 with the bonding pad facing downward, and the first die ( A second die 24 having an edge bonding pad on 23 is bonded by the die adhesive film 22 with the bonding pad facing upward.

또, 제1본딩와이어(25)에 의해 상기 제1다이(23)의 본딩패드와 기판(21)하부의 회로배선 패턴이 전기적으로 연결되고, 제2본딩와이어(26)에 의해 상기 제2다이(24)의 본딩패드와 기판(21)상부의 회로배선 패턴이 전기적으로 연결되어 있다.The bonding pad of the first die 23 and the circuit wiring pattern under the substrate 21 are electrically connected by the first bonding wire 25, and the second die is connected by the second bonding wire 26. The bonding pad of 24 and the circuit wiring pattern on the substrate 21 are electrically connected.

상기 기판(21)상부의 회로배선 패턴은 비아홀(30)을 통하여 기판(21)하부의 솔더볼 랜드(28)와 연결되어 있어, 솔더볼 랜드(28)상에 부착되어 있는 솔더볼(29)에 의해 외부와 전기적으로 접속될 수 있도록 되어 있다.The circuit wiring pattern on the substrate 21 is connected to the solder ball lands 28 below the substrate 21 through the via holes 30 and externally connected by the solder balls 29 attached on the solder ball lands 28. It can be connected electrically with.

또한, 외부로부터의 오염을 막기 위해, 상기 제1 및 제2다이(23, 24)와 본딩와이어(26)가 일체적으로 EMC(Epoxy Molding Compound)(27)에 의해 몰딩되어 있고,제1다이(23)의 본딩패드와 기판(21)하부의 회로배선 패턴을 전기적으로 연결하는 본딩 와이어(25)를 포함하는 윈도우(31)부분 또한 EMC(27)에 의해 몰딩되어 있다.In addition, in order to prevent contamination from the outside, the first and second dies 23 and 24 and the bonding wire 26 are integrally molded by an epoxy molding compound (EMC) 27, and the first die A portion of the window 31 including the bonding wire 25 for electrically connecting the bonding pad of 23 to the circuit wiring pattern under the substrate 21 is also molded by the EMC 27.

상기와 같은 구조에 의해 적층된 다이들의 본딩 와이어가 서로 단락되는 것을 방지할 수 있다.By the above structure, the bonding wires of the stacked dies can be prevented from being shorted to each other.

도 3은 본 발명의 제2실시예에 의한 다이 적층형 윈도우 칩 스케일 패키지의 측단면도이다.3 is a side cross-sectional view of a die stacked window chip scale package according to a second embodiment of the present invention.

도면과 같이, 기판(21) 상부의 복수의 다이접착면에는 다이접착필름(22)에 의해 센터본딩패드를 갖는 복수개의 제1다이(23)가 본딩패드를 하부로 향하도록 하여 접착되고, 상기 복수개의 제1다이(23)상에 에지본딩패드를 갖는 복수개의 제2다이(24)가 본딩패드를 상부로 향하도록 하여 다이접착필름(22)에 의해 접착되어 있다.As shown in the drawing, a plurality of first dies 23 having a center bonding pad are bonded to the plurality of die bonding surfaces on the substrate 21 with the bonding pads facing downward by the die bonding film 22. A plurality of second dies 24 having edge bonding pads on the plurality of first dies 23 are bonded by the die adhesive film 22 with the bonding pads facing upward.

또, 제1본딩와이어(25)에 의해 상기 제1다이(23)의 본딩패드와 기판(21)하부의 회로배선 패턴이 전기적으로 연결되고, 제2본딩와이어(26)에 의해 상기 제2다이(24)의 본딩패드와 기판(21)상부의 회로배선 패턴이 전기적으로 연결되어 있다.The bonding pad of the first die 23 and the circuit wiring pattern under the substrate 21 are electrically connected by the first bonding wire 25, and the second die is connected by the second bonding wire 26. The bonding pad of 24 and the circuit wiring pattern on the substrate 21 are electrically connected.

상기 기판(21)상부의 회로배선 패턴은 비아홀(30)을 통하여 기판(21)하부의 솔더볼 랜드(28)와 연결되어 있어, 솔더볼 랜드(28)상에 부착되어 있는 솔더볼(29)에 의해 외부와 전기적으로 접속될 수 있도록 되어 있다.The circuit wiring pattern on the substrate 21 is connected to the solder ball lands 28 below the substrate 21 through the via holes 30 and externally connected by the solder balls 29 attached on the solder ball lands 28. It can be connected electrically with.

또한, 외부로부터의 오염을 막기 위해, 상기 복수개의 제1 및 제2다이(23, 24)와 본딩와이어(26)가 일체적으로 EMC(Epoxy Molding Compound)(27)에 의해 몰딩되어 있고, 제1다이(23)의 본딩패드와 기판(21)하부의 회로배선 패턴을 전기적으로 연결하는 본딩 와이어(25)를 포함하는 윈도우(31)부분 또한 EMC(27)에 의해 몰딩되어 있다.Further, in order to prevent contamination from the outside, the plurality of first and second dies 23 and 24 and the bonding wire 26 are integrally molded by an epoxy molding compound (EMC) 27. The portion of the window 31 including the bonding wire 25 for electrically connecting the bonding pads of the one die 23 and the circuit wiring pattern under the substrate 21 is also molded by the EMC 27.

상기와 같이 구성된 실장면적을 줄이기 위한 멀티 칩 모듈(MCM : Multi Chip Module) 구조에 의해 복수개의 반도체 칩을 하나로 패키지화 함으로써, 재료의 손실 및 인덕턴스를 감소시켜 반도체 소자의 전기적 특성을 향상시킬 수 있다.By packaging a plurality of semiconductor chips into a multi chip module (MCM) structure for reducing the mounting area configured as described above, it is possible to reduce the loss of material and inductance, thereby improving the electrical characteristics of the semiconductor device.

상기한 바와 같이 본 발명에 의하면 기판의 다이접착면상에 센터본딩패드를 갖는 제1다이를 접착시키고, 상기 제1다이상에 에지본딩패드를 갖는 제2다이를 접착시켜 구성함으로써, 몰딩공정시 상기 제1 및 제2다이의 본딩와이어의 단락을 방지하여 신뢰성을 향상시키고 반도체 칩의 점유면적을 감소시킬 수 있는 효과가 있다.As described above, according to the present invention, a first die having a center bonding pad is adhered to a die attaching surface of a substrate, and a second die having an edge bonding pad is adhered to the first die to form the above die during the molding process. The short circuit of the bonding wires of the first and second dies may be prevented to improve reliability and reduce the footprint of the semiconductor chip.

Claims (2)

복수개의 반도체 칩을 적층하여 형성된 윈도우 칩 스케일 패키지에 있어서, 상부 및 하부에 형성된 회로배선패턴, 중앙에 관통된 윈도우(31), 상부 및 하부의 회로배선패턴을 연결시키기 위한 비아홀(30) 및 하부에 형성된 솔더볼 랜드(28)를 구비한 인쇄회로기판(21); 상기 기판(21)상의 다이접착면에 다이접착필름(22)에 의해 본딩패드가 하부로 향하도록 접착된 센터본딩패드를 갖는 제1다이(23); 상기 제1다이(23)상에 본딩패드가 상부로 향하도록 다이접착필름(22)에 의해 접착된 에지본딩패드를 갖는 제2다이(24); 상기 제1다이(23)의 본딩패드와 기판(21)하부의 회로배선 패턴을 전기적으로 연결시키는 제1본딩와이어(25); 상기 제2다이(24)의 본딩패드와 기판(21)상부의 회로배선 패턴을 전기적으로 연결시키는 제2본딩와이어(26); 외부로부터의 오염을 막기 위해 상기 제1 및 제2다이(23, 24)와 제2본딩와이어(26)를 일체적으로 몰딩하고, 상기 기판(21)하부의 윈도우(31) 부분을 몰딩하는 EMC(27); 외부와의 전기적 접속을 위해 상기 솔더볼 랜드(28)상에 부착되어 있는 솔더볼(29)을 포함한 것을 특징으로 하는 다이 적층형 윈도우 칩 스케일 패키지.In a window chip scale package formed by stacking a plurality of semiconductor chips, a circuit wiring pattern formed at an upper portion and a lower portion, a window 31 penetrated at the center, a via hole 30 and a lower portion connecting the upper and lower circuit wiring patterns A printed circuit board 21 having solder ball lands 28 formed thereon; A first die 23 having a center bonding pad bonded to the die bonding surface on the substrate 21 so that the bonding pad faces downward by a die bonding film 22; A second die 24 having an edge bonding pad bonded to the first die 23 by a die bonding film 22 so that the bonding pad faces upward; A first bonding wire 25 electrically connecting the bonding pad of the first die 23 to the circuit wiring pattern under the substrate 21; A second bonding wire 26 electrically connecting a bonding pad of the second die 24 to a circuit wiring pattern on the substrate 21; EMC to integrally mold the first and second dies 23 and 24 and the second bonding wire 26 to prevent contamination from the outside, and to mold a portion of the window 31 under the substrate 21. (27); And a solder ball (29) attached to the solder ball land (28) for electrical connection to the outside. 복수개의 반도체 칩을 적층하여 형성된 윈도우 칩 스케일 패키지에 있어서, 상부 및 하부에 형성된 회로배선패턴, 복수의 윈도우(31), 상부 및 하부의 회로배선패턴을 연결시키기 위한 비아홀(30) 및 하부에 형성된 솔더볼 랜드(28)를 구비한인쇄회로기판(21); 상기 기판(21)상의 복수의 다이접착면에 다이접착필름(22)에 의해 본딩패드가 하부로 향하도록 접착된 센터본딩패드를 갖는 복수개의 제1다이(23); 상기 복수개의 제1다이(23) 상부 각각에 본딩패드가 상부로 향하도록 다이접착필름(22)에 의해 접착된 에지본딩패드를 갖는 복수개의 제2다이(24); 상기 제1다이(23) 각각의 본딩패드와 기판(21)하부의 회로배선 패턴을 전기적으로 연결시키는 제1본딩와이어(25); 상기 제2다이(24) 각각의 본딩패드와 기판(21)상부의 회로배선 패턴을 전기적으로 연결시키는 제2본딩와이어(26); 외부로부터의 오염을 막기 위해 상기 복수개의 제1 및 제2다이(23, 24)와 제2본딩와이어(26)를 일체적으로 몰딩하고, 상기 기판(21)하부의 복수의 윈도우(31) 부분을 몰딩하는 EMC(27); 외부와의 전기적 접속을 위해 상기 솔더볼 랜드(28)상에 부착되어 있는 솔더볼(29)을 포함한 것을 특징으로 하는 다이 적층형 윈도우 칩 스케일 패키지.In a window chip scale package formed by stacking a plurality of semiconductor chips, a circuit wiring pattern formed on upper and lower portions, a plurality of windows 31, and via holes 30 and lower portions formed to connect circuit wiring patterns on upper and lower portions thereof are formed. A printed circuit board 21 having a solder ball land 28; A plurality of first dies (23) having a center bonding pad bonded to the plurality of die bonding surfaces on the substrate (21) so that the bonding pads face downward by the die bonding film (22); A plurality of second dies 24 having edge bonding pads bonded to each of the plurality of first dies 23 by a die bonding film 22 so that the bonding pads face upwards; A first bonding wire 25 electrically connecting a bonding pad of each of the first dies 23 and a circuit wiring pattern under the substrate 21 to each other; A second bonding wire 26 electrically connecting a bonding pad of each of the second dies 24 to a circuit wiring pattern on the substrate 21; In order to prevent contamination from the outside, the plurality of first and second dies 23 and 24 and the second bonding wire 26 are integrally molded, and the plurality of windows 31 under the substrate 21 are formed. EMC 27 for molding the; And a solder ball (29) attached to the solder ball land (28) for electrical connection to the outside.
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KR100451510B1 (en) * 2002-03-13 2004-10-06 주식회사 하이닉스반도체 method for manufacturing stacked chip package
US7119427B2 (en) 2003-11-13 2006-10-10 Samsung Electronics Ltd., Co. Stacked BGA packages
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100451510B1 (en) * 2002-03-13 2004-10-06 주식회사 하이닉스반도체 method for manufacturing stacked chip package
US7119427B2 (en) 2003-11-13 2006-10-10 Samsung Electronics Ltd., Co. Stacked BGA packages
KR200460882Y1 (en) * 2008-02-14 2012-06-14 오리엔트 세미컨덕터 일렉트로닉스 리미티드 Multi-chip package structure
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