KR200276091Y1 - 가요성 회로기판을 이용한 볼 그리드 어레이 반도체 패키지 제조용 몰딩 금형 - Google Patents
가요성 회로기판을 이용한 볼 그리드 어레이 반도체 패키지 제조용 몰딩 금형 Download PDFInfo
- Publication number
- KR200276091Y1 KR200276091Y1 KR2019970043959U KR19970043959U KR200276091Y1 KR 200276091 Y1 KR200276091 Y1 KR 200276091Y1 KR 2019970043959 U KR2019970043959 U KR 2019970043959U KR 19970043959 U KR19970043959 U KR 19970043959U KR 200276091 Y1 KR200276091 Y1 KR 200276091Y1
- Authority
- KR
- South Korea
- Prior art keywords
- circuit board
- flexible circuit
- mold
- grid array
- semiconductor package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000000465 moulding Methods 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000011347 resin Substances 0.000 claims abstract description 24
- 229920005989 resin Polymers 0.000 claims abstract description 24
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 11
- 229910000679 solder Inorganic materials 0.000 claims description 10
- 238000005538 encapsulation Methods 0.000 claims description 8
- 230000008054 signal transmission Effects 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 8
- NMWSKOLWZZWHPL-UHFFFAOYSA-N 3-chlorobiphenyl Chemical compound ClC1=CC=CC(C=2C=CC=CC=2)=C1 NMWSKOLWZZWHPL-UHFFFAOYSA-N 0.000 description 6
- 101001082832 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) Pyruvate carboxylase 2 Proteins 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 238000010030 laminating Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
Abstract
Description
Claims (1)
- 신호전달용 본드패드가 형성되어 있는 반도체칩과, 상기한 반도체칩이 열전도성 접착수단에 의하여 실장되며, 상면에는 회로패턴이 형성되고, 저면에는 개방부가 형성되어 상기한 회로패턴이 노출되는 솔더볼 랜드가 형성된 가요성 필름으로 이루어지는 가요성(可撓性) 회로기판과, 상기한 반도체칩에 형성된 본드패드와 가요성 회로기판의 상면에 형성된 회로패턴 상의 도전성 트레이스(Trace)를 접속시키는 와이어와, 상기한 반도체칩 및 본드 외어어를 외부환경으로 부터 보호하기 위하여 몰딩되는 수지 봉지부와, 상기한 가요성 회로기판 저면의 솔더볼랜드에 융착되어 입출력 단자로서 사용되는 다수의 솔더볼로 이루어지는 가요성 회로기판을 이용한 볼 그리드 어레이 반도체 패키지를 몰딩하기 위하여 상기한 가요성 회로기판의 하부에는 하형이 위치되고, 상부에는 내부에 캐비티가 형성된 상형이 위치되어, 상기한 상형과 하형을 클램핑시켜 수지 봉지제로 몰딩하도록 된 몰딩금형에 있어서, 상기한 가요성 회로기판의 하부에 위치되는 하형의 상면에는 상기한 가요성 수지필름으로 이루어지는 가요성 회로기판이 안착될 수 있는 안착홈이 더 형성되어 있는 것을 특징으로 하는 가요성 회로기판을 이용한 볼 그리드 어레이 반도체 패키지 제조용 몰딩 금형.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019970043959U KR200276091Y1 (ko) | 1997-12-30 | 1997-12-30 | 가요성 회로기판을 이용한 볼 그리드 어레이 반도체 패키지 제조용 몰딩 금형 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019970043959U KR200276091Y1 (ko) | 1997-12-30 | 1997-12-30 | 가요성 회로기판을 이용한 볼 그리드 어레이 반도체 패키지 제조용 몰딩 금형 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR19990031250U KR19990031250U (ko) | 1999-07-26 |
KR200276091Y1 true KR200276091Y1 (ko) | 2002-07-18 |
Family
ID=53898296
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR2019970043959U Expired - Fee Related KR200276091Y1 (ko) | 1997-12-30 | 1997-12-30 | 가요성 회로기판을 이용한 볼 그리드 어레이 반도체 패키지 제조용 몰딩 금형 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR200276091Y1 (ko) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100406499B1 (ko) * | 2001-09-21 | 2003-11-19 | 주식회사 칩팩코리아 | 반도체패키지의 몰딩장비 및 이를 이용한 몰딩방법 |
KR100964152B1 (ko) * | 2009-01-14 | 2010-06-17 | 주식회사 심텍 | 솔리드스테이트드라이브 |
-
1997
- 1997-12-30 KR KR2019970043959U patent/KR200276091Y1/ko not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR19990031250U (ko) | 1999-07-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100694739B1 (ko) | 다수의 전원/접지면을 갖는 볼 그리드 어레이 패키지 | |
JP3332516B2 (ja) | 露出裏面を有する熱強化型半導体デバイスと、その製造方法 | |
KR100843737B1 (ko) | 솔더 조인트의 신뢰성이 개선된 반도체 패키지 | |
US6521997B1 (en) | Chip carrier for accommodating passive component | |
US7239029B2 (en) | Packages for semiconductor die | |
JPH03165545A (ja) | 高性能オーバーモールド型電子デバイス及びその製造方法 | |
KR100282290B1 (ko) | 칩규모패키지및그제조방법 | |
US6903464B2 (en) | Semiconductor die package | |
KR200276091Y1 (ko) | 가요성 회로기판을 이용한 볼 그리드 어레이 반도체 패키지 제조용 몰딩 금형 | |
KR100199286B1 (ko) | 홈이 형성된 인쇄 회로 기판을 갖는 칩 스케일 패키지 | |
KR100369397B1 (ko) | 가요성회로기판을이용한볼그리드어레이반도체패키지 | |
KR100480834B1 (ko) | 레이저 마킹용 영구 테이프구조 | |
KR100216845B1 (ko) | CSP ( Chip Scale Package ; 칩 스케일 패키지)의 구조 및 제조방법 | |
KR19990059033A (ko) | 가요성 회로기판을 이용한 볼 그리드 어레이 반도체 패키지 | |
KR19980058592A (ko) | Bga 반도체패키지용 pcb | |
KR0161621B1 (ko) | 칩이 실장되는 공간이 형성된 기판을 적용한 칩 스케일 패키지 | |
KR19980019655A (ko) | 칩 스케일 패키지 | |
KR19980068016A (ko) | 가요성(可撓性) 회로 기판을 이용한 볼 그리드 어레이(Ball Grid Array : BGA) 반도체 패키지 및 그 제조 방법 | |
JPH06163760A (ja) | 放熱スラグを有した電子部品搭載用基板 | |
KR100225238B1 (ko) | CSP(Chip Scale Package ; 칩 스케일 패키지)의 구조 및 제조방법 | |
KR100244089B1 (ko) | 볼 그리드 어레이 반도체 패키지의 제조방법 및 그 구조 | |
KR19990059034A (ko) | 가요성 회로기판을 이용한 볼 그리드 어레이 반도체 패키지의솔더볼 랜드구조 | |
JPH02271556A (ja) | 半導体素子パツケージおよびその製造方法 | |
KR19980019666A (ko) | 칩 스케일 패키지 | |
JPH098171A (ja) | 半導体パッケージ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
UA0108 | Application for utility model registration |
Comment text: Application for Utility Model Registration Patent event code: UA01011R08D Patent event date: 19971230 |
|
UG1501 | Laying open of application | ||
A201 | Request for examination | ||
UA0201 | Request for examination |
Patent event date: 20000313 Patent event code: UA02012R01D Comment text: Request for Examination of Application Patent event date: 19971230 Patent event code: UA02011R01I Comment text: Application for Utility Model Registration |
|
N231 | Notification of change of applicant | ||
UN2301 | Change of applicant |
Comment text: Notification of Change of Applicant Patent event code: UN23011R01D Patent event date: 20000502 |
|
E701 | Decision to grant or registration of patent right | ||
UE0701 | Decision of registration |
Patent event date: 20020218 Comment text: Decision to Grant Registration Patent event code: UE07011S01D |
|
REGI | Registration of establishment | ||
UR0701 | Registration of establishment |
Patent event date: 20020508 Patent event code: UR07011E01D Comment text: Registration of Establishment |
|
UR1002 | Payment of registration fee |
Start annual number: 1 End annual number: 3 Payment date: 20020509 |
|
UG1601 | Publication of registration | ||
UR1001 | Payment of annual fee |
Payment date: 20050509 Start annual number: 4 End annual number: 4 |
|
FPAY | Annual fee payment |
Payment date: 20060508 Year of fee payment: 5 |
|
UR1001 | Payment of annual fee |
Payment date: 20060508 Start annual number: 5 End annual number: 5 |
|
LAPS | Lapse due to unpaid annual fee | ||
UC1903 | Unpaid annual fee |
Termination date: 20080610 Termination category: Default of registration fee |