KR20020091705A - Method for manufacturing tft-lcd - Google Patents

Abstract

The present invention relates to a method for manufacturing a thin film transistor liquid crystal display device, and more particularly, to a method for manufacturing a thin film transistor liquid crystal display device capable of flattening a gate insulating film over a gate electrode.

A method of manufacturing a thin film transistor liquid crystal display device for this purpose includes providing a glass substrate including a gate electrode; Forming a gate insulating film on the glass substrate; Using a half-tone mask to planarize by removing a step generated when the gate insulating layer is formed; And forming a thin film transistor on the flattened resultant.

Description

Method of manufacturing thin film transistor liquid crystal display device {METHOD FOR MANUFACTURING TFT-LCD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor liquid crystal display device, and more particularly, to a method for manufacturing a thin film transistor liquid crystal display device capable of flattening a gate insulating film over a gate electrode.

Liquid crystal display devices used in display devices such as televisions and graphic displays have been developed in place of the CRT (Cathod-ray tube). In particular, the thin film transistor liquid crystal display (hereinafter referred to as TFT-LCD) has advantages of high-speed response characteristics and high pixel number, so that a display screen comparable to the CRT can be made larger and higher in quality. . The TFT-LCD has a structure in which a liquid crystal layer is interposed between a TFT array substrate provided with a TFT and a pixel electrode and a color filter substrate provided with a color filter and a counter electrode.

Meanwhile, at present, most LCD manufacturers adopt TFTs having an Inverted Staggered structure, which is relatively easy to manufacture and does not require a separate TFT light blocking film. Such a reverse staggered TFT can be divided into a back channel etch (BCE) structure and an etch stopper structure according to a channel forming process. The manufacturing method of the BCE-TFTLCD with few lithography process is demonstrated in detail.

1A to 1C are manufacturing process diagrams for explaining a manufacturing method of a conventional BCE-TFT LCD.

As shown in FIG. 1A, a gate line (not shown) including the gate electrode 2 is formed on a transparent insulating substrate, for example, a transparent insulating substrate such as a glass substrate 1, and the gate is formed on the entire top. The insulating film 3 is deposited. At this time, in order to prevent the gate insulating film 3 from being cut off due to the step due to the gate line when the gate insulating film 3 is formed, the gate metal film is inclined to form the gate electrode 2, and the gate insulating film 3 is formed. To thick deposit.

Then, a semiconductor in which an undoped amorphous silicon film (a-si) and a doped amorphous silicon film (n + a-si) is stacked on the gate insulating film 3 on the gate electrode 2 through a known process. The layer 4 is formed, and then a single or stacked metal film for source / drain 5, for example, a metal film composed of Mo / Al / Mo is deposited.

1B, the source / drain metal film is etched by a known method to form a data line including the source / drain electrodes 5a and 5b, and subsequently the doped semiconductor layer 4 is doped. The TFT 10 is constituted by dry etching the amorphous silicon film.

Next, referring to FIG. 1C, in order to protect the TFT 10, a protective film 6, for example, a SiN x film is formed on the entire upper portion thereof, and then the protective film 6 is selectively etched to form the TFT part ( A via hole 7 exposing a predetermined portion of the source electrode 5a of A) is formed. Then, a pixel electrode 8 made of an ITO film is deposited on the protective film 6 so as to fill the via hole 7 to form a TFT substrate.

However, when the gate insulating film is thickly deposited, a high driving voltage must be applied to obtain a sufficient on-state current of the TFT. In addition, the resistance of the gate line is high, and thus the capacitance between the gate line and the data line is increased, so that the signal initially applied along the gate line is reduced, thereby failing to transmit a desired signal. This is called RC (resistance * capacitance) delay, which causes deterioration of image quality.

In addition, the gate line width must be increased or the thickness must be increased to reduce the resistance of the gate line. Increasing the gate line width causes a decrease in the aperture ratio, and when the thickness of the gate electrode 2 is increased, the gate insulating film 3 is increased. This is likely to be broken or short or open, causing a decrease in yield.

Further, when the above-described TFT-LCD is in the IPS mode, a count electrode is formed of a gate metal film of about 3000 mW, and a pixel electrode is formed using a source / drain metal film of about 2000 to 3000 mW when the source / drain electrode is formed. do. However, due to the step difference between the count electrode and the pixel electrode, the alignment is distorted at the portion where the step is generated when the alignment layer is rubbed, which is different from the plane when the liquid crystal is driven when the liquid crystal is driven. By causing the deterioration of the image quality.

In addition, even when the above-described TFT-LCD is in the FFS mode, various problems are presented due to the step difference.

Accordingly, an object of the present invention for solving the above problems is to form a stable liquid crystal array by forming a planarized gate electrode, and to suppress the RC delay by increasing the thickness of the gate line and reducing the thickness of the gate insulating film thereon. A method of manufacturing a thin film transistor liquid crystal display device is provided.

1A to 1C are manufacturing process diagrams for explaining a method for manufacturing a thin film transistor liquid crystal display device according to the prior art.

2A to 2F are manufacturing process diagrams for explaining a method for manufacturing a thin film transistor liquid crystal display device according to the present invention.

3A and 3B are manufacturing process diagrams for explaining a method for manufacturing a thin film transistor liquid crystal display device according to another embodiment of the present invention.

4A to 4E are manufacturing process diagrams for explaining a method for manufacturing a thin film transistor liquid crystal display device according to another exemplary embodiment of the present invention.

5A to 5D are manufacturing process diagrams for explaining a method for manufacturing a thin film transistor liquid crystal display device according to another exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

21 glass substrate 22 gate electrode

23a: planarized gate insulating film 24: insulating film

25 doped amorphous silicon film 26 doped amorphous silicon film

27a, 27b: source / drain electrodes 28: protective film

29 pixel electrode 50 planarization layer

60, 80: photoresist film 200: thin film transistor

Method of manufacturing a thin film transistor liquid crystal display device of the present invention for achieving the above object comprises the steps of providing a glass substrate comprising a gate electrode; Forming a gate insulating film on the glass substrate; Using a half-tone mask to planarize by removing a step generated when the gate insulating layer is formed; And forming a thin film transistor on the flattened resultant.

In addition, according to the present invention comprises the steps of providing a glass substrate comprising a gate electrode; Forming a planarization layer on the glass substrate; Performing a chemical mechanical polishing (CMP) process on the planarization layer until the gate electrode is exposed; And forming a thin film transistor on the polished resultant.

In addition, according to the present invention comprises the steps of providing a glass substrate comprising a gate electrode; Forming a gate insulating film on the glass substrate; Coating a photoresist film on the entire surface of the gate insulating film; Ashing the photoresist film until the gate insulating film is exposed; Etching and planarizing the gate insulating layer to expose the surface of the gate electrode with the photoresist layer as an etch barrier; And forming an insulating film on the flattened resultant, and forming a thin film transistor.

In addition, according to the present invention, providing a glass substrate comprising a gate electrode; Forming a gate insulating film on the glass substrate; Forming a photoresist pattern defining a region where a step occurs on the gate insulating layer; Planarizing the gate insulating layer by etching a portion of the gate insulating layer using the photoresist pattern as an etch barrier; And forming a thin film transistor on the flattened result.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

2A to 2F are manufacturing process diagrams for describing a method of manufacturing a thin film transistor liquid crystal display device according to an exemplary embodiment of the present invention.

First, as shown in FIG. 2A, a gate metal film is deposited on the glass substrate 21. Then, the gate metal film is patterned by a known photo process to form a gate electrode 22 on the glass substrate 21. Next, a gate insulating film 23 covering the gate electrode 22, for example, a SiONx film, is applied to a thickness of 3000 to 8000 kPa.

In this case, a step is formed in the gate insulating layer 23 by the height of the gate electrode 22. The step is planarized using the half-tone mask 110 as shown in FIG. 2B. That is, the gate insulating layer 23 is planarized by performing a full exposure in the stepped region and exposing only a predetermined amount in the peripheral region without the step.

As illustrated, the half-tone mask 110 includes a region 103 (transmission region) where light is transmitted 100% and a region 105 (halftone region) where about 30 to 70% of light is transmitted.

Due to the exposure and development of the half-tone mask 110, the thickness of the gate insulating film in the stepped region is 1500 to 5000 kPa, and the thickness of the gate insulating film in the peripheral region is about 2000 to 6000 kPa, thereby achieving flattening.

Accordingly, the planarization of the gate insulating film 23 reduces the leveling of the film layers formed after the planarization of the gate insulating film 23. When the electrode is formed using the source / drain metal film, the step difference caused by the gate electrode 22 is alleviated. In the etching process for forming the defects such as disconnection is reduced.

Next, as shown in FIG. 2C, an insulating film 24 for forming an active region on the planarized gate insulating film 23a, an undoped amorphous silicon film 25, and a doped amorphous silicon film 26 are formed. Deposition in turn.

Then, as shown in Fig. 2D, after forming a photoresist pattern (not shown) in the TFT formation region region, the doped amorphous silicon film 26, the undoped amorphous silicon film using the pattern as an etch barrier. The 25 and the insulating film 24 are sequentially etched.

Subsequently, as shown in FIG. 2E, a metal film for data lines is formed on the resultant, and then a photoresist pattern (not shown) defining a source / drain formation region is formed in the TFT formation region. Subsequently, the thin film transistor 200 is formed by forming the source / drain electrodes 27a and 27b by etching the data line metal film using the photoresist pattern as an etch barrier. Next, a protective film 28 for protecting the thin film transistor 200 is deposited.

Next, as shown in FIG. 2F, the thin film transistor substrate is completed by forming the pixel electrode 29 in contact with the drain electrode 27b on the passivation layer 28 through a known ITO process.

Hereinafter, the same components as those shown in FIGS. 2A to 2F will be described with the same reference numerals.

3A and 3B are manufacturing process diagrams for explaining another embodiment of the present invention.

As shown in FIG. 3A, the gate electrode 22 is formed on the transparent glass substrate 21. Next, the planarization layer 50 is formed on the gate electrode 22. In this case, the planarization layer 50 forms a fluidized film such as an SOG film and performs a heat treatment to achieve planarization. Subsequently, the planarization layer 50 is subjected to chemical mechanical polishing to expose the gate electrode 22.

Next, as shown in FIG. 3B, the gate insulating layer 23 is deposited on the entire surface of the resultant in which the planarization layer 50 is formed on both sides of the gate electrode 22. Next, as described with reference to FIGS. 2C to 2F, the thin film transistor 200 is formed to form a TFT substrate.

4A and 4E are manufacturing process diagrams for describing a method of manufacturing a thin film transistor liquid crystal display device according to another exemplary embodiment of the present invention.

As shown in FIG. 4A, the gate electrode 22 is formed on the glass substrate 21. In this case, the gate electrode 22 is formed to have a thickness of at least 3000 GPa in consideration of resistance. Next, a gate insulating film 23 is formed over the entire glass substrate 21 on which the gate electrode 22 is formed. At this time, the gate insulating film 23 is formed to a thickness approximately twice that of the gate electrode 22, that is, a thickness of at least 6000 GPa.

Next, as shown in FIG. 4B, the photoresist film 60 is coated on the entire surface of the substrate on which the gate insulating film 23 is formed. At this time, the photoresist film 60 is flattened and coated without forming a pattern, and the thickness at this time is at least 6000 GPa.

Next, as shown in FIG. 4C, the photoresist film 60 is ashed until the gate insulating film 23 is exposed. At this time, the ashing of the photoresist film 60 is performed by using reactive ion etching equipment and ashing by using O ₂ plasma.

Next, as shown in FIG. 4D, the gate insulating film 23 is etched and planarized so that the surface of the gate electrode 22 is exposed using the etched photoresist film 60a as an etch barrier.

Subsequently, as shown in FIG. 4E, the ashed photoresist film 60a is removed, and then the thin film transistor 200 is formed on the planarized resultant, as described in FIGS. 2C to 2F, to form a TFT substrate. do.

5a to 5d is a manufacturing process diagram for explaining another embodiment of the present invention.

As shown in FIG. 5A, a gate metal film is deposited on the glass substrate 21. Then, the gate metal film is patterned by a known photo process to form a gate electrode 22 on the glass substrate 21. Next, a gate insulating film 23 is applied to the entire surface of the substrate on which the gate electrode 22 is formed. Next, a photoresist film 80 is formed over the gate insulating film 23. In this case, the photoresist film 80 is formed of a negative photoresist film having a characteristic of developing only a portion where UV light does not pass during exposure.

Then, as shown in Figure 5b, the exposure on the back of the glass substrate 20. Then, since the gate electrode 22 does not pass UV light, the gate electrode 22 is self-aligned only to the upper portion of the gate electrode 22, and only a part thereof is developed. Thus, a photoresist pattern 80a is formed on the gate insulating film 23 to define an area where a step occurs.

Subsequently, as shown in FIG. 5C, a predetermined portion of the gate insulating film 23 is etched using the photoresist pattern 80a as an etch barrier to planarize.

Next, as shown in FIG. 5D, the photoresist pattern 80a is removed, and the thin film transistor 200 as described in FIGS. 2C to 2F is formed on the planarized gate insulating film 23a to form a TFT. Complete the substrate.

In the above-described embodiment, only the planarization process of the gate insulating film is described in the process of forming the thin film transistor. Since the gate insulating film formed in the step also occurs, the thin film transistor substrate may be formed by planarizing the gate insulating film through the method described above.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

According to the above-described manufacturing method of the thin film transistor liquid crystal display device, by flattening the step difference caused by the gate electrode under the gate insulating film, the film quality formed thereon is naturally flattened. Therefore, the probability of failure such as disconnection at the time of forming the source / drain electrodes is reduced, thereby improving the yield.

In addition, the height of the gate electrode can be increased, thereby reducing the gate resistance, thereby improving the thin film transistor characteristics, and reducing the width of the gate electrode, thereby increasing the opening area. Therefore, it is useful for manufacturing TFT-LCD panels using thin film transistor characteristics and high aperture ratio. In addition, imbalance of cell orientation due to poor rubbing can be prevented.

Claims (16)

Providing a glass substrate comprising a gate electrode; Forming a gate insulating film on the glass substrate; Using a half-tone mask to planarize by removing a step generated when the gate insulating layer is formed; And And forming a thin film transistor on the flattened resultant. The method of claim 1, Wherein the half-tone mask is completely exposed in a stepped region and exposed only as much as a predetermined amount in a peripheral region thereof to vary the degree of etching. The method of claim 2, The gate insulating film is formed to be 3000 ~ 8000Å, the thickness of the gate insulating film in the stepped region is 1500 ~ 5000Å by exposure and development of the half-tone mask, the gate insulating film thickness of the peripheral region is 2000 ~ 6000Å A method of manufacturing a thin film transistor liquid crystal display device. The method of claim 3. And the thin film transistor liquid crystal display device is any one of TN, STN, DSTN, IPS and FFS modes. Providing a glass substrate comprising a gate electrode; Forming a planarization layer on the glass substrate; Performing a chemical mechanical polishing (CMP) process on the planarization layer until the gate electrode is exposed; And And forming a thin film transistor on the polished resultant. The method of claim 5, And the planarization film is a fluid film such as an SOG film. The method of claim 5, And the thin film transistor liquid crystal display device is any one of TN, STN, DSTN, IPS and FFS modes. Providing a glass substrate comprising a gate electrode; Forming a gate insulating film on the glass substrate; Coating a photoresist film on the entire surface of the gate insulating film; Ashing the photoresist film until the gate insulating film is exposed; Etching and planarizing the gate insulating layer to expose the surface of the gate electrode with the photoresist layer as an etch barrier; And And forming a thin film transistor on the flattened resultant, and forming a thin film transistor. The method of claim 8, The gate electrode has a thickness of 3000 Å ~ 10000 Å, the method of manufacturing a thin film transistor liquid crystal display device. The method of claim 8, The thickness of the gate insulating film is 6000 Å ~ 10000 Å manufacturing method of the thin film transistor liquid crystal display device. The method of claim 8, The ashing of the photoresist film is a method of manufacturing a thin film transistor liquid crystal display device using an O ₂ plasma using a reactive ion etching equipment. The method of claim 8, And the thickness of the photoresist film is 6000 kPa ~ 10000 kPa. Providing a glass substrate comprising a gate electrode; Forming a gate insulating film on the glass substrate; Forming a photoresist pattern defining a region where a step occurs on the gate insulating layer; Planarizing the gate insulating layer by etching a portion of the gate insulating layer using the photoresist pattern as an etch barrier; And And forming a thin film transistor on the flattened resultant. The method of claim 13, The photoresist pattern is a manufacturing method of a thin film transistor liquid crystal display device, characterized in that the negative photoresist film has a characteristic that only the part that does not pass UV light development during exposure. The method of claim 14, And the photoresist pattern is exposed on a back side of a glass substrate to develop only a gate insulating layer on the gate electrode. The method of claim 8 or 13, And the thin film transistor liquid crystal display device is any one of TN, STN, DSTN, IPS and FFS modes.