KR20020090441A - Method for Forming Copper Line of Semiconductor Device - Google Patents
Method for Forming Copper Line of Semiconductor Device Download PDFInfo
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- KR20020090441A KR20020090441A KR1020010028982A KR20010028982A KR20020090441A KR 20020090441 A KR20020090441 A KR 20020090441A KR 1020010028982 A KR1020010028982 A KR 1020010028982A KR 20010028982 A KR20010028982 A KR 20010028982A KR 20020090441 A KR20020090441 A KR 20020090441A
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- copper
- contact hole
- barrier metal
- metal layer
- plug
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 71
- 229910052802 copper Inorganic materials 0.000 claims abstract description 65
- 239000010949 copper Substances 0.000 claims abstract description 65
- 239000010410 layer Substances 0.000 claims abstract description 48
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 23
- 230000004888 barrier function Effects 0.000 claims abstract description 22
- 239000011229 interlayer Substances 0.000 claims abstract description 14
- 125000006850 spacer group Chemical group 0.000 claims abstract description 7
- 230000009977 dual effect Effects 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 238000004140 cleaning Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000001552 radio frequency sputter deposition Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자에 관한 것으로 특히, 구리 원자의 확산을 원활하게 하여 구리 배선의 신뢰성을 향상시키기 위한 반도체 소자의 구리 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a method for forming a copper wiring in a semiconductor device for smoothing the diffusion of copper atoms to improve the reliability of the copper wiring.
일반적으로 반도체 소자의 구리배선을 형성하는 방법으로 듀얼 다마신(Dual Damascene) 방법이 주로 사용되는데, 그 순서를 간략히 설명하면 다음과 같다.In general, a dual damascene method is mainly used as a method of forming a copper wiring of a semiconductor device, and the order thereof will be briefly described as follows.
우선, 하부 구리배선이 형성된 반도체 기판에 소정의 층간 절연막들을 형성하고, 이들을 선택적으로 제거하여 비아 및 트랜치를 형성하여 듀얼 다마신 구조의 콘택홀을 형성한다.First, predetermined interlayer insulating films are formed on a semiconductor substrate on which a lower copper wiring is formed, and then selectively removed to form vias and trenches to form contact holes having a dual damascene structure.
이어, 상기 콘택홀을 포함한 전표면상에 배리어 금속막을 증착하고 상기 콘택홀이 완전히 매립되도록 전면에 소정 두께의 구리를 증착한다.Subsequently, a barrier metal film is deposited on the entire surface including the contact hole, and copper of a predetermined thickness is deposited on the entire surface so that the contact hole is completely filled.
이어, 평탄화 및 표면 세정 공정으로 상기 콘택홀 내에 구리 배선을 형성한 후에 구리 배선 표면에 생성된 구리 자연 산화막을 환원시킨 후, 공기 중에 노출시키지 않은 채로 캡핑층(Capping Layer)을 형성하여 종래 기술에 따른 반도체 소자의 배선을 완성한다.Subsequently, after forming the copper wiring in the contact hole by the planarization and surface cleaning process, the copper native oxide film formed on the copper wiring surface is reduced, and then a capping layer is formed without exposing to air. The wiring of the semiconductor device according to this is completed.
그러나, 상기와 같은 종래의 반도체 소자의 구리배선 형성방법은 다음과 같은 문제점이 있다.However, the conventional copper wiring forming method of the semiconductor device as described above has the following problems.
첫째, 배선의 단면적이 작아 전류밀도가 높아지므로 신뢰성이 저하된다.First, since the cross-sectional area of the wiring is small and the current density is high, the reliability is lowered.
둘째, 하부 구리배선과 구리 플러그 경계에 배리어 금속층이 존재하여 하부 구리배선과 구리 플러그간 구리원자 확산을 차단하여 플러그 내부에 보이드(Void)와 같은 결함이 발생되어 배선이 단락되는 등의 불량이 발생된다.Second, a barrier metal layer exists between the lower copper wiring and the copper plug to block the diffusion of copper atoms between the lower copper wiring and the copper plug, resulting in defects such as voids in the plug and short circuits such as short circuits. do.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 배리어 금속층을 증착한 후 이방성 식각 공정을 통해 하부 구리배선과 상부 구리 플러그가직접 연결되도록 하여 구리 배선의 신뢰성을 향상시키기 위한 반도체 소자의 구리배선 형성방법을 제공하는데 그 목적이 있다.The present invention has been made in order to solve the above problems, and after depositing a barrier metal layer, the lower copper wiring and the upper copper plug are directly connected through an anisotropic etching process, thereby improving the reliability of the copper wiring. The purpose is to provide a formation method.
도 1a 내지 1f는 본 발명에 따른 반도체 소자의 구리 배선 제조공정 단면도1A to 1F are cross-sectional views of a copper wiring manufacturing process of a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호 설명Explanation of symbols for the main parts of drawings
11 : 제 1 층간 절연막 12 : 하부 구리 배선11 first interlayer insulating film 12 lower copper wiring
13 : 제 1 식각 정지막 14 : 제 2 층간 절연막13 first etch stop film 14 second interlayer insulating film
15 : 제 2 식각 정지막 16 : 제 3 층간 절연막15: second etch stop film 16: third interlayer insulating film
17 : 제 3 식각 정지막 18 : 비아17: third etching stop film 18: via
19 : 트랜치 20 : 배리어 금속층19 trench 20 barrier metal layer
20a : 스페이서 21 : 구리층20a: spacer 21: copper layer
21a : 구리 플러그 22 : 캡핑층21a: copper plug 22: capping layer
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 구리배선 형성방법은 하부 구리배선의 일영역을 노출시키는 듀얼 다마신 구조의 콘택홀을 형성하는 단계와, 상기 콘택홀을 포함한 전면에 배리어 금속층을 증착하는 단계와, 이방성 식각 공정으로 상기 콘택홀 하부의 배리어 금속층을 완전히 제거하여 하부 구리배선을 노출시키고 상기 콘택홀 측면에 배리어 금속층을 잔류시키어 스페이서를 형성하는 단계와, 상기 콘택홀에 구리 플러그를 형성하는 단계와, 상기 플러그를 포함한 전면에 캡핑층을 형성하는 단계를 포함하여 형성함을 특징으로 한다.According to an aspect of the present invention, there is provided a method for forming a copper wiring of a semiconductor device, the method including: forming a contact hole having a dual damascene structure exposing a region of a lower copper wiring; Depositing a metal layer, completely removing the barrier metal layer under the contact hole by an anisotropic etching process to expose the lower copper wiring, and leaving a barrier metal layer on the side of the contact hole to form a spacer; Forming a plug, and forming a capping layer on a front surface of the plug including the plug.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 구리배선 형성방법을 설명하면 다음과 같다.Hereinafter, a copper wiring forming method of a semiconductor device according to the present invention will be described with reference to the accompanying drawings.
도 1a 내지 도 1f는 본 발명의 실시예에 따른 반도체 소자의 구리배선 제조 공정 단면도이다.1A to 1F are cross-sectional views illustrating a process for manufacturing copper wiring of a semiconductor device according to an embodiment of the present invention.
우선, 도 1a에 도시된 바와 같이, 하부 구리 배선(12)이 형성된 제 1 층간 절연막(11)상에 제 1 식각 정지막(13)과, 제 2 층간 절연막(14)과, 제 2 식각 정지막(15)과, 제 3 층간 절연막(16)과 제 3 식각 정지막(17)을 차례로 증착한다.First, as shown in FIG. 1A, the first etch stop layer 13, the second interlayer insulating layer 14, and the second etch stop are formed on the first interlayer insulating layer 11 on which the lower copper wiring 12 is formed. The film 15, the third interlayer insulating film 16, and the third etch stop film 17 are sequentially deposited.
여기서, 상기 제 1, 2, 3 층간 절연막(11, 14, 16)은 낮은 절연 상수(k)를 갖는 물질로, 주로 실리콘 산화막(SiO2)을 이용하여 형성하고, 상기 제 1, 2, 3 식각 정지막(13, 15, 17)은 주로 실리콘 질화막(SiN)을 이용하여 형성한다.Here, the first, second, and third interlayer insulating films 11, 14, and 16 are materials having a low dielectric constant (k), and are mainly formed using a silicon oxide film (SiO 2 ). The etch stop films 13, 15, and 17 are mainly formed using silicon nitride film (SiN).
그리고, 소정의 공정으로 상기 하부 구리 배선(12)이 노출되도록 상기 제 3, 2, 1 식각 정지막(17, 15, 13) 및 제 3, 2 층간 절연막(16, 14)을 선택적으로 제거하여 비아(18) 및 트랜치(19)로 이루어진 듀얼 다마신(Dual Damascene) 구조의 콘택홀(18)(19)을 형성한다.The third, second, and first etch stop layers 17, 15, and 13 and the third and second interlayer insulating layers 16 and 14 may be selectively removed to expose the lower copper wiring 12 in a predetermined process. Contact holes 18 and 19 having a dual damascene structure formed of vias 18 and trenches 19 are formed.
이어, RF 스퍼터링(Sputtering) 세정 또는 수소환원 세정공정에 의하여 하부 구리 배선(12)의 표면을 세정한다.Subsequently, the surface of the lower copper wiring 12 is cleaned by an RF sputtering cleaning or a hydrogen reduction cleaning process.
그리고, 도 1b에 도시된 바와 같이 상기 콘택홀(18)(19)을 포함한 전면에 100∼800Å 두께의 배리어 금속층(20)을 증착한다.As shown in FIG. 1B, a barrier metal layer 20 having a thickness of 100 to 800 Å is deposited on the entire surface including the contact holes 18 and 19.
상기 배리어 금속층(20) 증착 공정은 이온화된 PVD(Ionized Physical Vapor Deposition) 방식을 이용하여 실시하며, 상기 배리어 금속층(20) 물질로는 탄탈륨(Ta) 또는 탄탈륨 질화막(TaN) 등을 이용한다.The barrier metal layer 20 deposition process is performed using an ionized Physical Vapor Deposition (PVD) method, and the material of the barrier metal layer 20 uses tantalum (Ta) or a tantalum nitride layer (TaN).
상기 공정을 이온화된 PVD 방법을 이용함에 따라서 기존의 스퍼터링(Sputtering) 방법에 비하여 스텝 커버리지(Step Coverage)가 크게 향상된다.By using the ionized PVD method, the step coverage is greatly improved as compared to the conventional sputtering method.
이어, 도 1c에 도시된 바와 같이 상기 비아(18) 바닥에 존재하는 배리어 금속층(20)이 제거될 때까지 상기 배리어 금속층(20) 식각 공정 및 세정 공정을 실시한다.Subsequently, as shown in FIG. 1C, the barrier metal layer 20 is etched and cleaned until the barrier metal layer 20 existing on the bottom of the via 18 is removed.
이때, 이방성 식각 공정을 진행하여 상기 비아(18) 및 트랜치(19) 측면에 상기 배리어 금속층(20)을 잔류시키어 스페이서(20a)를 형성한다.At this time, the anisotropic etching process is performed to leave the barrier metal layer 20 on the side surfaces of the via 18 and the trench 19 to form the spacer 20a.
따라서, 구리원자의 콘택홀(18)(19) 측면 방향으로의 확산은 제 2, 3 식각 정지막(15, 17)과 스페이서(20a)에 의해 금지된다.Therefore, diffusion of the copper atoms in the lateral direction of the contact holes 18 and 19 is inhibited by the second and third etch stop films 15 and 17 and the spacer 20a.
그리고, 도 1d에 도시된 바와 같이, 상기 콘택홀(18)(19)이 완전히 매립되도록 전면에 구리층(21)을 증착한 후, 후속 열처리 공정을 실시한다.As shown in FIG. 1D, the copper layer 21 is deposited on the entire surface such that the contact holes 18 and 19 are completely filled, and then a subsequent heat treatment process is performed.
상기 구리 증착법으로는 매립 특성 및 물성이 우수한 전해 도금법이 유리하다. 전해도금법을 이용하기 위해서는 구리 씨드(Seed)층을 이온화된 PVD 방법을 이용하여 500∼2000Å 두께로 미리 증착한다. 그리고, 구리 씨드층을 기반으로 구리를 성장시키어 형성한다.As the copper deposition method, an electrolytic plating method having excellent embedding characteristics and physical properties is advantageous. In order to use the electroplating method, a copper seed layer is previously deposited to a thickness of 500 to 2000 kW using an ionized PVD method. Then, copper is formed by growing the copper seed layer.
여기서, 상기 후속 열처리 공정의 목적은 구리층(21) 결정립의 크기를 증가시키고 안정화시키기 위한 것으로, 상기 후속 열처리 공정은 급속 열처리 공정(RTP)을 이용하여 150∼400℃에서 1∼2분 동안 실시한다.Here, the purpose of the subsequent heat treatment process is to increase and stabilize the size of the copper layer 21 grains, the subsequent heat treatment process is carried out for 1 to 2 minutes at 150 ~ 400 ℃ using a rapid heat treatment process (RTP) do.
이어, 도 1e에 도시된 바와 같이 상기 제 3 식각 정지막(17)을 에치 스탑퍼층으로 이용한 CMP 공정으로 상기 구리층(21)과 상기 제 3 식각 정지막(17)을 제거하여 상기 콘택홀(18)(19) 내부에 구리 플러그(21a)를 형성한다.Subsequently, as shown in FIG. 1E, the contact hole may be removed by removing the copper layer 21 and the third etch stop layer 17 by a CMP process using the third etch stop layer 17 as an etch stopper layer. 18) (19) to form a copper plug (21a).
그리고, 표면 세정 공정을 실시하여 상기 CMP(Chemical Mechanical Polishing) 공정에 의해 유발된 표면 결함 및 불순물 입자(Particle)를 제거한다.The surface cleaning process is performed to remove surface defects and impurity particles caused by the chemical mechanical polishing (CMP) process.
이어, 구리 플러그(21a) 표면에 생성된 구리 자연 산화막을 환원시킨다.Next, the natural copper oxide film produced on the surface of the copper plug 21a is reduced.
그리고, 구리 플러그(21a) 내의 구리원자가 상부에 형성되는 층간 절연층으로 확산하여 배선 사이의 누설(Leakage)을 유발하는데 이를 방지하기 위하여 도 1f에 도시된 바와 같이, 공기 중에 노출시키지 않은 채로 PECVD(Plasma EnhancedChemical Vapor Deposition) 방식을 이용하여 전면에 캡핑층(22)을 형성하여 본 발명에 따른 반도체 소자의 구리배선을 완성한다.In addition, the copper atoms in the copper plug 21a diffuse into the interlayer insulating layer formed thereon to cause leakage between the wirings. To prevent this, as shown in FIG. 1F, PECVD (not exposed to air) is prevented. The copper wiring of the semiconductor device according to the present invention is completed by forming a capping layer 22 on the front surface by using a plasma enhanced chemical vapor deposition method.
상기와 같은 본 발명의 반도체 소자의 구리배선 형성방법은 다음과 같은 효과가 있다.The copper wiring forming method of the semiconductor device of the present invention as described above has the following effects.
첫째, 하부구리 배선과 구리 플러그 사이의 배리어 금속층을 제거하여 하부 구리배선과 구리 플러그간의 구리원자 상호확산이 가능하므로 구리배선의 신뢰성을 향상시킬 수 있다.First, since the barrier metal layer between the lower copper wiring and the copper plug is removed, copper atoms can be inter-diffused between the lower copper wiring and the copper plug, thereby improving the reliability of the copper wiring.
둘째, 배리어 금속층을 이방성 건식각하여 스페이서를 형성함에 따라서 콘택홀 내부의 공간이 확보되므로 구리 씨드층 증착 및 구리매립 공정이 유리하다.Second, as the barrier metal layer is anisotropically dry etched to form a spacer, the space inside the contact hole is secured, so that the copper seed layer deposition and the copper filling process are advantageous.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010028982A KR20020090441A (en) | 2001-05-25 | 2001-05-25 | Method for Forming Copper Line of Semiconductor Device |
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| KR1020010028982A KR20020090441A (en) | 2001-05-25 | 2001-05-25 | Method for Forming Copper Line of Semiconductor Device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040036012A (en) * | 2002-10-23 | 2004-04-30 | 주식회사 하이닉스반도체 | Method of forming a copper wiring in a semiconductor device |
| KR101055028B1 (en) * | 2006-10-11 | 2011-08-05 | 인터내셔널 비지네스 머신즈 코포레이션 | Enhanced Interconnect Structure |
-
2001
- 2001-05-25 KR KR1020010028982A patent/KR20020090441A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040036012A (en) * | 2002-10-23 | 2004-04-30 | 주식회사 하이닉스반도체 | Method of forming a copper wiring in a semiconductor device |
| KR101055028B1 (en) * | 2006-10-11 | 2011-08-05 | 인터내셔널 비지네스 머신즈 코포레이션 | Enhanced Interconnect Structure |
| US8129842B2 (en) | 2006-10-11 | 2012-03-06 | International Business Machines Corporation | Enhanced interconnect structure |
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