KR20020058235A - Bonding pad structure in semiconductor device and method for fabricating the same - Google Patents
Bonding pad structure in semiconductor device and method for fabricating the same Download PDFInfo
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Abstract
Description
본 발명은 반도체 소자 및 그 제조 방법에 관한 것으로서, 특히 반도체 소자의 본딩 패드(bonding pad) 구조 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a bonding pad structure of a semiconductor device and a method of manufacturing the same.
반도체 조립 공정에는, 반도체 소자의 본딩 패드와 리드 프레임의 단자를 골드 와이어와 같이 도전성이 좋은 금속선으로 연결하는 와이어 본딩 공정이 포함된다. 와이어 본딩 공정을 종료한 후에는, 본딩 패드 상부에 형성된 볼과 본딩 패드와의 접착력을 평가하는 단계를 수행하는 것이 일반적이다. 그런데 이때 본딩 패드 상부의 볼이 본딩 패드로부터 떨어지는 경우가 발생할 수 있으며, 경우에 따라서는 본딩 패드 자체가 하부 막질인 절연층 또는 금속층과 떨어지는 경우도 발생될 수 있다. 이와 같은 현상들이 발생되면, 불량인 반도체 소자가 만들어지므로 이와 같은 현상이 발생하지 않도록 본딩 패드와 볼, 그리고 본딩 패드와 하부 막질 사이의 접착력을 견고하게 할 필요가 있다.The semiconductor assembly step includes a wire bonding step of connecting the bonding pad of the semiconductor element and the terminal of the lead frame with a metal wire having good conductivity such as gold wire. After finishing the wire bonding process, it is common to perform the step of evaluating the adhesion between the bonding pad and the ball formed on the bonding pad. In this case, however, the ball on the bonding pad may fall from the bonding pad, and in some cases, the bonding pad itself may be separated from the insulating layer or the metal layer having the lower film quality. If such phenomena occur, a defective semiconductor device is made, and thus it is necessary to strengthen the adhesive force between the bonding pad and the ball and the bonding pad and the lower film to prevent such a phenomenon from occurring.
도 1은 종래의 반도체 소자의 본딩 패드 구조를 나타내 보인 단면도이다.1 is a cross-sectional view illustrating a bonding pad structure of a conventional semiconductor device.
도 1에 도시된 바와 같이, 반도체 기판(미도시) 상부의 도전막(미도시)과의 절연을 위한 절연막(10)이 도전막 위에 배치된다. 그리고 도전성 막질로 이루어진 본딩 패드(11)가 상기 절연막(10) 위에 패터닝되어 배치된다. 보호막(12)은 본딩 패드(11)의 상부 일부 표면을 노출시키도록 절연막(10) 및 본딩 패드(11) 위에 배치된다.As shown in FIG. 1, an insulating film 10 for insulating a conductive film (not shown) on a semiconductor substrate (not shown) is disposed on the conductive film. A bonding pad 11 made of a conductive film material is patterned and disposed on the insulating film 10. The passivation layer 12 is disposed on the insulating layer 10 and the bonding pad 11 to expose a portion of the upper surface of the bonding pad 11.
이와 같은 본딩 패드 구조에 있어서, 앞서 설명한 바와 같이, 절연막(10)과 본딩 패드(11)의 접촉 면적이 작아서 본딩 패드(11)가 절연막(10)으로부터 이탈될 수 있다.As described above, in the bonding pad structure, the contact area between the insulating film 10 and the bonding pad 11 is small so that the bonding pad 11 may be separated from the insulating film 10.
도 2는 상기와 같은 문제점을 개선하기 위하여 제안된 종래의 다른 반도체 소자의 본딩 패드 구조를 나타내 보인 단면도이다.2 is a cross-sectional view illustrating a bonding pad structure of another conventional semiconductor device proposed to improve the above problems.
도 2에 도시된 바와 같이, 절연막(20)에는 소정 간격으로 이격된 일정 깊이의 홀(20h)들이 형성되며, 본딩 패드(21)는 이 홀(20h)들을 채우면서 절연막(20) 위에 패터닝되어 배치된다. 보호막(22)은 본딩 패드(21)의 상부 일부 표면을 노출시키도록 절연막(20) 및 본딩 패드(21) 위에 배치된다.As shown in FIG. 2, holes 20h having a predetermined depth are formed in the insulating film 20, and the bonding pads 21 are patterned on the insulating film 20 while filling the holes 20h. Is placed. The passivation layer 22 is disposed on the insulating layer 20 and the bonding pads 21 to expose a portion of the upper surface of the bonding pads 21.
이와 같은 본딩 패드 구조에 있어서는, 상기 홀(20h)의 존재로 인하여 절연막(20)과 본딩 패드(21)의 접촉 면적이 넓어졌다. 이에 따라 본딩 패드(21)와 절연막(20) 사이의 접착력이 증가되어, 도 1에 나타낸 본딩 패드 구조에 비하여, 본딩 패드(21)가 절연막(20)으로부터 이탈되는 것이 억제된다.In such a bonding pad structure, the contact area between the insulating film 20 and the bonding pad 21 is enlarged due to the presence of the hole 20h. As a result, the adhesive force between the bonding pad 21 and the insulating film 20 is increased, and the separation of the bonding pad 21 from the insulating film 20 is suppressed as compared with the bonding pad structure shown in FIG. 1.
그러나 이 경우에도 단지 본딩 패드(21)와 절연막(20) 사이의 접촉 면적만을 증가시킴으로써 접착력을 증가시키고 하였으므로, 그 사이의 접착력 증가 효과는 미약하며, 따라서 여전히 본딩 패드(21)가 절연막(20)으로부터 이탈되는 문제를 갖고 있다.However, even in this case, since the adhesive force was increased by only increasing the contact area between the bonding pad 21 and the insulating film 20, the effect of increasing the adhesive force therebetween is weak, and thus the bonding pad 21 is still in the insulating film 20. There is a problem of deviating from.
본 발명이 이루고자 하는 기술적 과제는, 하부 막질로부터의 이탈을 억제시킨 반도체 소자의 본딩 패드 구조를 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a bonding pad structure of a semiconductor device in which separation from lower film quality is suppressed.
본 발명이 이루고자 하는 다른 기술적 과제는 상기 반도체 소자의 본딩 패드 구조를 제조하는 방법을 제공하는 것이다.Another object of the present invention is to provide a method of manufacturing a bonding pad structure of the semiconductor device.
도 1은 종래의 반도체 소자의 본딩 패드 구조를 나타내 보인 단면도이다.1 is a cross-sectional view illustrating a bonding pad structure of a conventional semiconductor device.
도 2는 종래의 다른 반도체 소자의 본딩 패드 구조를 나타내 보인 단면도이다.2 is a cross-sectional view illustrating a bonding pad structure of another conventional semiconductor device.
도 3은 본 발명에 따른 반도체 소자의 본딩 패드 구조를 나타내 보인 단면도이다.3 is a cross-sectional view illustrating a bonding pad structure of a semiconductor device according to the present invention.
도 4 내지 도 6은 본 발명에 따른 반도체 소자의 본딩 패드 구조를 제조하는 방법을 설명하기 위하여 나타내 보인 단면도들이다.4 to 6 are cross-sectional views illustrating a method of manufacturing a bonding pad structure of a semiconductor device according to the present invention.
상기 기술적 과제를 달성하기 위하여, 본 발명에 따른 반도체 소자의 본딩 패드 구조는, 반도체 기판 위의 도전층과 연결되며, 외부의 리드 프레임과 각각 연결되는 반도체 소자의 본딩 패드 구조에 있어서, 상기 도전층 위에 형성되되, 상부 표면에 형성된 홈을 갖는 보조막; 상기 보조막 위에서 상기 홈의 일부를 노출시키는 컨택 홀을 갖는 절연막 패턴; 및 상기 절연막 패턴의 컨택 홀을 통해 상기 보조막의 홈을 완전히 채우면서 상기 절연막 패턴 위에 형성된 본딩 패드를 구비하는 것을 특징으로 한다.In order to achieve the above technical problem, the bonding pad structure of the semiconductor device according to the present invention is connected to the conductive layer on the semiconductor substrate, in the bonding pad structure of the semiconductor device respectively connected to an external lead frame, the conductive layer An auxiliary film formed thereon, the auxiliary film having a groove formed on an upper surface thereof; An insulating film pattern having a contact hole exposing a part of the groove on the auxiliary film; And a bonding pad formed on the insulating layer pattern while completely filling the groove of the auxiliary layer through the contact hole of the insulating layer pattern.
상기 보조막은 절연막 혹은 도전막일 수 있는데, 여기서 사용하는 절연막은 산화막, 질화막, USG, BPSG 또는 TEOS막인 것이 바람직하고, 여기서 사용하는 도전막은 폴리실리콘, 텅스텐, Ti, TiN 또는 알루미늄 합금막인 것이 바람직하다.The auxiliary film may be an insulating film or a conductive film, and the insulating film used herein may be an oxide film, a nitride film, a USG, a BPSG, or a TEOS film, and the conductive film used herein may be a polysilicon, tungsten, Ti, TiN, or aluminum alloy film. .
상기 다른 기술적 과제를 달성하기 위하여, 본 발명에 따른 반도체 소자의 본딩 패드 구조 제조 방법은, 소정의 하부막 위에 보조막을 형성하는 단계; 상기 보조막 위에 상기 보조막의 일부 표면을 노출시키는 절연막 패턴을 형성시키는 단계; 상기 보조막의 노출 표면에 언더컷을 형성시키는 단계; 및 상기 절연막 패턴 및 상기 보조막의 노출 표면 위에 본딩 패드를 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above another technical problem, a method of manufacturing a bonding pad structure of a semiconductor device according to the present invention, forming an auxiliary film on a predetermined lower layer; Forming an insulating layer pattern on the auxiliary layer to expose a portion of the surface of the auxiliary layer; Forming an undercut on an exposed surface of the auxiliary film; And forming a bonding pad on the exposed surface of the insulating layer pattern and the auxiliary layer.
상기 보조막 및 절연막 패턴은 상호 식각 선택비가 다른 물질막을 사용하여 형성하는 것이 바람직하다.The auxiliary layer and the insulating layer pattern may be formed using a material layer having a different etching selectivity.
상기 본딩 패드를 형성하는 단계는, 상기 절연막 패턴 및 상기 보조막 위에 본딩 패드로 사용할 도전막을 형성하는 단계; 상기 도전막이 상기 보조막의 언더컷을 완전히 채울 수 있는 온도 범위에서 리플로우 공정을 수행하는 단계: 및 상기 도전막을 패터닝하여 상기 본딩 패드를 형성하는 단계를 포함하는 것이 바람직하다.The forming of the bonding pad may include forming a conductive film on the insulating layer pattern and the auxiliary layer to be used as a bonding pad; And performing a reflow process in a temperature range in which the conductive film completely fills the undercut of the auxiliary film; and patterning the conductive film to form the bonding pad.
이하 첨부 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3은 본 발명에 따른 반도체 소자의 본딩 패드 구조를 나타내 보인 단면도이다.3 is a cross-sectional view illustrating a bonding pad structure of a semiconductor device according to the present invention.
도 3에 도시된 바와 같이, 반도체 기판(미도시) 상부의 도전막(미도시)과의 절연을 위한 절연막(100)이 도전막 위에 배치된다. 이 절연막(100) 위에는 보조막(110)이 형성된다. 이 보조막(110)의 상부 표면에는 적어도 하나의 홈(111)이 형성된다. 이 홈(111)은 보조막(110)의 상부 표면으로부터 일정 깊이까지 형성된다. 상기 보조막(110)은 절연막일 수도 있고 도전막일 수도 있다. 절연막인 경우에는 산화막, 질화막, USG(Undoped Silicate Glass), BPSG(BoroPhosphoSilicate Glass) 혹은 TEOS(TetraEthlyOrthoSilicate Glass)막을 사용할 수 있으며, 도전막인 경우에는 폴리실리콘, 텅스텐, Ti, TiN 혹은 알루미늄 합금막을 사용할 수 있다.As shown in FIG. 3, an insulating film 100 for insulation from a conductive film (not shown) on a semiconductor substrate (not shown) is disposed on the conductive film. An auxiliary film 110 is formed on the insulating film 100. At least one groove 111 is formed on an upper surface of the auxiliary layer 110. The groove 111 is formed to a predetermined depth from the upper surface of the auxiliary film 110. The auxiliary layer 110 may be an insulating film or a conductive film. In the case of an insulating film, an oxide film, a nitride film, USG (Undoped Silicate Glass), BPSG (BoroPhosphoSilicate Glass) or TEOS (TetraEthlyOrthoSilicate Glass) film may be used, and in the case of a conductive film, polysilicon, tungsten, Ti, TiN, or an aluminum alloy film may be used. have.
상기 보조막(110) 위에는 컨택 홀을 갖는 절연막 패턴(120)이 배치된다. 이 절연막 패턴(120)을 관통하는 컨택 홀은 상기 보조막(110)의 홈의 일부를 노출시킨다. 즉 상기 컨택 홀에 의하여 상기 보조막(110)의 홈 전체가 노출되는 것이 아니라, 홈의 가장자리는 절연막 패턴(120)에 의해 덮이고, 홈의 중심 부분만이 노출된다.An insulating layer pattern 120 having contact holes is disposed on the auxiliary layer 110. The contact hole penetrating the insulating layer pattern 120 exposes a part of the groove of the auxiliary layer 110. That is, the entire groove of the auxiliary layer 110 is not exposed by the contact hole, but the edge of the groove is covered by the insulating layer pattern 120, and only the center portion of the groove is exposed.
본딩 패드(130)는 도전성 막질로 이루어지며, 상기 절연막 패턴(120) 위에 형성된다. 이때 상기 본딩 패드(130)는 절연막 패턴(120)의 컨택 홀 내에도 채워지며, 또한 보조막(110)의 홈(111) 내부도 완전히 채워지도록 형성된다. 이와 같은 구조에서, 보조막(110)의 홈(111) 내부에 채워진 본딩 패드(130)의 가장자리 부분은 절연막 패턴(120)에 의해 지지된다. 즉 도면에서의 상부 방향을 향하여 상당한 크기의 힘이 가해지더라도, 본딩 패드(130)와 보조막(110)의 홈(111)을 채우고 있으므로 증가된 접촉 면적에 대응하여 접착력이 증가되며, 또한 앞서 설명한 바와 같이 보조막(110)의 홈(111) 내부에 채워진 본딩 패드(130)의 가장자리 부분은 절연막 패턴(120)에 의해 지지되므로, 본딩 패드(130)가 하부 막질인 절연막 패턴(120)으로부터 분리되는 현상이 억제된다.The bonding pad 130 is formed of a conductive film and is formed on the insulating film pattern 120. In this case, the bonding pads 130 are also filled in the contact holes of the insulating layer pattern 120, and the inside of the groove 111 of the auxiliary layer 110 is also completely filled. In such a structure, the edge portion of the bonding pad 130 filled in the groove 111 of the auxiliary film 110 is supported by the insulating film pattern 120. That is, even if a considerable amount of force is applied toward the upper direction in the drawing, the bonding pad 130 and the groove 111 of the auxiliary film 110 are filled, thereby increasing the adhesive force corresponding to the increased contact area. As described above, since the edge portion of the bonding pad 130 filled in the groove 111 of the auxiliary layer 110 is supported by the insulating layer pattern 120, the bonding pad 130 is separated from the insulating layer pattern 120 having a lower film quality. Phenomenon is suppressed.
한편, 보호막(140)은 본딩 패드(130)의 상부 일부 표면을 노출시키도록 절연막 패턴(120) 및 본딩 패드(130) 위에 배치된다.Meanwhile, the passivation layer 140 is disposed on the insulating layer pattern 120 and the bonding pad 130 to expose a portion of the upper surface of the bonding pad 130.
도 4 내지 도 6은 본 발명에 따른 반도체 소자의 본딩 패드 구조 제조 방법을 설명하기 위하여 나타내 보인 단면도들이다.4 to 6 are cross-sectional views illustrating a method of manufacturing a bonding pad structure of a semiconductor device according to the present invention.
먼저 도 4에 도시된 바와 같이, 도전막(미도시) 위에 절연막(100)을 형성한다. 상기 도전막(미도시)은 반도체 기판(미도시) 위에 형성된다. 다음에 절연막(100) 위에 보조막(110')을 형성한다. 이 보조막(110')은 절연막일 수도 있고 도전막일 수도 있다. 절연막인 경우에는 산화막, 질화막, USG, BPSG 혹은 TEOS막을 사용할 수 있으며, 도전막인 경우에는 폴리실리콘, 텅스텐, Ti, TiN 혹은 알루미늄 합금막을 사용할 수 있다. 상기 보조막(110')은 절연막(100)의 일부 표면을 노출시키도록 형성될 수 있다. 이어서 절연막(100)의 노출 표면 및 보조막(110') 위에 절연막 패턴(120)을 형성한다. 이 절연막 패턴(120)은 보조막(110')의 일부 표면을 노출시키는 개구부(121)를 갖는다. 상기 개구부(121)는 적어도 하나 이상, 즉 복수개로 형성시킬 수 있다. 상기 절연막 패턴(120)은 여러 절연성 물질을 사용하여 형성할 수 있는데, 특히 상기 보조막(110')과 습식식각 선택비 및 건식 식각 선택비가 다른 물질을 사용하여야 한다. 상기 절연막 패턴(120)을 형성하는 방법은 통상의 패터닝 방법을 사용할 수 있다.First, as shown in FIG. 4, an insulating film 100 is formed on a conductive film (not shown). The conductive film (not shown) is formed on a semiconductor substrate (not shown). Next, an auxiliary film 110 ′ is formed on the insulating film 100. The auxiliary film 110 ′ may be an insulating film or a conductive film. In the case of an insulating film, an oxide film, a nitride film, a USG, a BPSG, or a TEOS film may be used. In the case of a conductive film, a polysilicon, tungsten, Ti, TiN, or an aluminum alloy film may be used. The auxiliary layer 110 ′ may be formed to expose a portion of the surface of the insulating layer 100. Subsequently, an insulating film pattern 120 is formed on the exposed surface of the insulating film 100 and the auxiliary film 110 ′. The insulating layer pattern 120 has an opening 121 exposing a part of the surface of the auxiliary layer 110 ′. At least one or more openings 121 may be formed. The insulating layer pattern 120 may be formed using various insulating materials. In particular, a material having a different wet etching selectivity and dry etching selectivity from the auxiliary layer 110 ′ should be used. As a method of forming the insulating layer pattern 120, a conventional patterning method may be used.
다음에 도 5에 도시된 바와 같이, 등방성 식각, 예컨대 습식 식각법을 사용하여 보조막(110) 상부 표면에 언더컷(undercut)(111)을 형성시킨다. 상기 언더컷(111)은, 절연막 패턴(120)과 보조막(110) 사이의 식각 선택비가 다르므로, 등방성 식각을 수행함에 따라 자연적으로 형성된다.Next, as shown in FIG. 5, an undercut 111 is formed on the upper surface of the auxiliary layer 110 using an isotropic etching, for example, a wet etching method. Since the undercut 111 has a different etching selectivity between the insulating layer pattern 120 and the auxiliary layer 110, the undercut 111 is naturally formed by performing isotropic etching.
다음에 도 6에 도시된 바와 같이, 도전성 물질, 예컨대 금속을 사용하여 본딩 패드(130)를 절연막 패턴(120) 및 보조막(110)의 노출면 위에 형성한다. 이때 본딩 패드(130)가 절연막 패턴(120) 사이의 컨택 홀 내부는 물론이고 보조막(110) 상부 표면에 형성된 언더컷(111) 내부도 완전히 채워지도록 한다. 이를 위하여, 먼저 본딩 패드로 사용할 금속막을 전면에 형성한다. 그리고 소정 온도, 예컨대 400-600℃의 온도에서 리플로우(reflow) 공정을 수행한다. 그러면 상기 본딩 패드로 사용할 금속막이 절연막 패턴(120) 사이의 컨택 홀 내부와 함께 보조막(110) 상부 표면에 형성된 언더컷(111) 내부를 완전히 채우게 된다. 이어서 상기 금속막을 패터닝하여, 도시된 바와 같은 본딩 패드(130)를 형성한다.Next, as illustrated in FIG. 6, a bonding pad 130 is formed on the exposed surface of the insulating layer pattern 120 and the auxiliary layer 110 by using a conductive material such as a metal. In this case, the bonding pad 130 may completely fill not only the inside of the contact hole between the insulating layer patterns 120 but also the inside of the undercut 111 formed on the upper surface of the auxiliary layer 110. To this end, first, a metal film to be used as a bonding pad is formed on the front surface. And a reflow process at a predetermined temperature, for example 400-600 ° C. Then, the metal layer to be used as the bonding pad completely fills the inside of the undercut 111 formed on the upper surface of the auxiliary layer 110 together with the contact hole between the insulating layer patterns 120. Subsequently, the metal film is patterned to form a bonding pad 130 as shown.
다음에 절연막 패턴(120) 및 본딩 패드(130) 위에 보호막을 형성하고, 본딩 패드(130)의 일부 표면이 노출되도록 보호막을 패터닝하면, 도 3에 도시된 바와 같은 본딩 패드 구조가 완성된다.Next, when the passivation layer is formed on the insulating layer pattern 120 and the bonding pad 130, and the passivation layer is patterned so that a part of the surface of the bonding pad 130 is exposed, the bonding pad structure as illustrated in FIG. 3 is completed.
이상의 설명에서와 같이, 본 발명에 따른 반도체 소자의 본딩 패드 구조 및그 제조 방법에 의하면, 본딩 패드가 볼 방향으로 상당한 크기의 힘이 가해지더라도, 본딩 패드가 보조막의 홈 내부를 채우고 있으므로 본딩 패드와 보조막 사이의 증가된 접촉 면적에 대응하여 접착력이 증가되며, 또한 보조막의 홈 내부에 채워진 본딩 패드의 가장자리 부분은 절연막 패턴에 의해 지지되므로, 본딩 패드가 하부 막질인 절연막 패턴으로부터 분리되는 현상이 억제된다.As described above, according to the bonding pad structure and the manufacturing method of the semiconductor device according to the present invention, even if the bonding pad is applied a considerable amount of force in the ball direction, since the bonding pad fills the inside of the groove of the auxiliary film, the bonding pad and the auxiliary Adhesion is increased in response to the increased contact area between the films, and the edge portion of the bonding pad filled inside the groove of the auxiliary film is supported by the insulating film pattern, so that the phenomenon that the bonding pad is separated from the insulating film pattern having the lower film quality is suppressed. .
Claims (6)
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7271439B2 (en) | 2003-12-19 | 2007-09-18 | Hynix Semiconductor Inc. | Semiconductor device having pad structure for preventing and buffering stress of silicon nitride film |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7271439B2 (en) | 2003-12-19 | 2007-09-18 | Hynix Semiconductor Inc. | Semiconductor device having pad structure for preventing and buffering stress of silicon nitride film |
| US8067838B2 (en) | 2003-12-19 | 2011-11-29 | Hynix Semiconductor Inc. | Semiconductor device having pad structure for preventing and buffering stress of silicon nitride film |
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