KR20020056800A - Method for fabricating a landing plug of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a landing plug of a semiconductor device. The method includes forming a gate electrode on an upper side of a substrate, forming a sidewall formed of an insulating material on a sidewall thereof, and removing silicon on the substrate exposed between sidewalls of the gate electrode. Selective epitaxial overgrowth covering the top of the gate electrode and buried between the sidewalls, polishing the selective epitaxial growth film with CMP to the surface of the gate electrode, and then self-aligning to the sidewall using a landing plug mask. The epitaxial growth film is etched to form a landing plug connected to the junction of the substrate. Therefore, when the landing plug is manufactured by the conventional PPP or SAC process, the space between the gate electrodes has a high aspect ratio, so that the gap fill characteristics are poor or are generated due to the etching when the plug contact holes are formed between the gate electrodes. Substrate loss can be prevented in advance.

Description

Method for fabricating a landing plug of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, a landing plug is stably manufactured between sidewalls of a gate electrode by using a selective epitaxial growth of silicon (SEG) process in a highly integrated semiconductor device. It's about how you can do it.

In recent years, as semiconductor devices become more integrated, memory cell sizes are gradually decreasing, and contact margins between word lines and bit lines are gradually decreasing. Thus, as a method for increasing the contact margin, there is a well-known self-aligned contact (hereinafter referred to as SAC) manufacturing technology. The contact hole is formed by using the step of the surrounding structure. The contact hole of various sizes can be obtained without using a mask by the height of the surrounding structure, the thickness of the insulating material on which the contact hole is to be formed, and the etching method. It is used in a method suitable for realizing a semiconductor device to be micronized.

Conventional self-aligned contact (landing plug) landing plug fills the gap between the gate electrodes with an interlayer insulating film and forms a contact hole by etching the portion where the landing plug is to be formed on the sidewall of the gate electrode. Polysilicon is embedded in the contact hole or the epitaxial film is grown by SEG process.

However, in the SAC type landing plug formation, the substrate is excessively etched during the contact hole etching process of the SAC to realize contact holes having a high aspect ratio in the device technology of 0.16 μm or less. The problem is that the depth is changed. In addition, since the line width of the contact hole of the SAC structure is very small, gap-fill gap of the interlayer insulating film is difficult, and if voids are formed in the interlayer insulating film, a short problem with adjacent cell transistors is caused.

Thus, the landing plug manufacturing method of the SAC has a limitation in accurately obtaining a contact hole having a high aspect ratio, a new technology is required. As such a new landing plug manufacturing technology, there is a manufacturing method of PPP (Pre-Poly Plug).

In the landing plug method of PPP, after forming a spacer on the sidewall of the gate electrode, the entire substrate is doped with polysilicon and then gap-filled between the gate electrodes, and then the part to be the landing plug is masked and the remaining portion of the poly Remove the silicon. Such a PPP method can form a good contact of a landing plug for a bit line or a storage node electrode, and is suitable for the contact technology of a highly integrated semiconductor device than the SAC method.

However, such a landing plug manufacturing method using PPP is not only difficult to gapfill polysilicon due to the narrow space between the gate electrodes, but also residues of polysilicon on the sidewalls of the gate electrodes, rather than the landing plug regions, may remain during the etching process. There was a problem causing short with the adjacent cell.

An object of the present invention is to perform the SEG process on the silicon between the sidewalls of the gate electrode in order to solve the problems of the prior art as described above, after overgrowing with a selective epitaxial film so as to surround the upper side of the gate electrode. By grinding the surface, masking only the landing plug portion and removing the epitaxial growth film of the remaining portions to form the landing plug, the space between the gate electrodes has a high aspect ratio, so that the gap fill property is poor in the plug manufacturing process or between the gate electrodes The present invention provides a method for manufacturing a landing plug of a semiconductor device, which can prevent a substrate loss caused by etching when forming a contact hole.

1 and 2 are a plan view and a vertical cross-sectional view of the result of forming the sidewall of the gate electrode in the semiconductor manufacturing process according to the present invention,

3, 4A and 4B are plan and vertical cross-sectional views of the result of performing the SEG process in the semiconductor manufacturing process according to the present invention,

5, 6A and 6B are a plan view and a vertical cross-sectional view of the result of performing the CMP process in the semiconductor manufacturing process according to the present invention,

7 is a plan view showing an example of the landing plug mask used in the manufacturing process of the present invention,

8, 9A and 9B are plan views and vertical cross-sectional views showing the structure of a landing plug formed by an etching process using a landing plug mask in a semiconductor manufacturing process according to the present invention.

Explanation of symbols on the main parts of the drawings

100: silicon substrate 102: field oxide film

110 gate electrode 112 doped polysilicon film or metal film

114: capping film 116: sidewall

120: selective epitaxial transient growth film

120 ': polished epitaxial growth film

120a: landing plug

124: portion where the interlayer insulating film is to be deposited

In order to achieve the above object, the present invention forms a landing plug by selective epitaxial growth of silicon between sidewalls of a gate electrode formed on a silicon substrate, and forms a gate electrode on the substrate and an insulating material on the sidewall thereof. Forming a sidewall, and selectively growing epitaxially silicon on the substrate exposed between the sidewalls of the gate electrode to cover the top of the gate electrode and to fill the sidewalls, and to selectively surface the surface of the gate electrode. Polishing the tactical growth film, and etching the selective epitaxial growth film to self-align the sidewall using a landing plug mask to form a landing plug between the sidewalls of the predetermined region.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 and 2 are a plan view and a vertical cross-sectional view of the resultant formed to the sidewall of the gate electrode in the semiconductor manufacturing process according to the present invention. FIG. 2 is a vertical cross-sectional view of the semiconductor structure taken along line BB ′ of FIG. 1.

First, referring to FIG. 2, a field oxide film 102 is formed on a silicon substrate 100, and a conventional cell transistor is formed on the substrate 100 as a semiconductor memory device. Accordingly, the gate electrode 110 including the doped polysilicon layer 112 and the capping layer 114 is formed on the substrate 100. The sidewall 116 is formed of an insulating material on the side of the gate electrode 110. In this case, the sidewall 116 is formed of a material having an etching selectivity with respect to the selective epitaxial growth layer to be formed later.

Next, although not shown in the drawing, a source impurity ion is implanted under the substrate between the sidewalls 116 to form a source / drain region (not shown).

3, 4A, and 4B are plan and vertical cross-sectional views of a result of the SEG process performed in the semiconductor manufacturing process according to the present invention. FIG. 4A is a vertical cross-sectional view of the semiconductor structure taken along line AA ′ of FIG. 3 and line B-B ′ of FIG. 3.

4A and 4B, the SEG process is performed on the substrate exposed between the sidewalls 116 of the gate electrode 110 to overgrow the silicon of the substrate to the selective epitaxial growth layer 120. Accordingly, the selective epitaxial growth layer 120 covers the upper portion of the gate electrode 110 and fills all of the sidewalls 116. At this time, the growth of the selective epitaxial layer during the SEG process is grown in the vertical direction only in the silicon substrate, but induces silicon to grow excessively in the horizontal direction over time.

5, 6A and 6B are plan views and vertical cross-sectional views of a result of the CMP process performed in the semiconductor manufacturing process according to the present invention. FIG. 6A is a vertical cross-sectional view of the semiconductor structure taken along line AA ′ of FIG. 5 and line B-B ′ of FIG. 5.

6A and 6B, the surface of the selective epitaxial growth layer 120 grown higher than the capping layer 114 of the gate electrode 110 is ground by CMP to separate the cells.

7 is a plan view showing an example of the landing plug mask used in the manufacturing process of the present invention. As such, a mask (photoresist pattern or hard mask) 122 defining a landing plug region is formed in the selective epitaxial growth layer 120 where the cells are separated and the surface is flat.

8, 9A, and 9B are plan views and vertical cross-sectional views illustrating a structure of a landing plug formed by an etching process using a landing plug mask in a semiconductor manufacturing process according to the present invention. FIG. 9A is a vertical cross-sectional view of the semiconductor structure taken along line AA ′ of FIG. 8, and FIG. 9B is a line B-B ′ of FIG. 8.

9A and 9B, using a landing plug mask formed on the planarized selective epitaxial growth layer 120 ′ and performing an etching process to self-align the sidewalls 116 of the gate electrode 110. The selective epitaxial growth layer 120 'is etched to leave the selective epitaxial growth layer only at the junction portion for the bit line or the storage node electrode, and all other portions 124 are removed to remove the landing plug 120a according to the present invention. Form.

Subsequently, a space between the remaining gate electrodes 124 is filled with an insulating layer in a resultant product in which a landing plug 120a made of a silicon epitaxial growth layer is formed only between sidewalls of a bit line or storage node junction. Line production).

As described above, according to the manufacturing method of the present invention, it is possible to solve the gap fill problem of the polysilicon or the interlayer insulating film generated when the landing plug is formed of the prior art PPP or SAC. That is, in the case of the conventional PPP method, when the gap region of the plug region is filled with polysilicon or the interlayer insulating film is gap filled with the SAC method, the gap fill is not good because the space between the gate electrodes has a very high aspect ratio. However, the present invention can solve the gap fill problem of the conventional plug since the silicon is selectively epitaxially grown using SEG technology to fill all the spaces between the gate electrodes.

In addition, when the landing plug is manufactured by the conventional SAC method, the bonding region of silicon is damaged by the SAC contact hole etching process and the shorting problem with the adjacent cell occurs due to the void of the interlayer insulating layer. Since the etching process for opening the circuit is omitted, the substrate is safe from etching damage and the interlayer insulating film is formed after the landing plug is formed, thereby improving the interlayer insulating property.

Claims (3)

In forming a landing plug by selective epitaxial growth of silicon between sidewalls of a gate electrode formed on a silicon substrate, Forming a gate electrode on the substrate and forming sidewalls of an insulating material on sidewalls of the gate electrode; Selectively epitaxially growing silicon of the substrate exposed between the sidewalls of the gate electrode to cover the top of the gate electrode and fill the gaps between the sidewalls; Polishing the selective epitaxial growth film to the surface of the gate electrode; And And manufacturing a landing plug between sidewalls of a predetermined portion by etching the selective epitaxial growth layer so as to self-align the sidewall using the landing plug mask. Way. The method of claim 1, wherein the sidewall is formed of a material having an etch selectivity with respect to the selective epitaxial growth layer. The method of claim 1, wherein the growth of the selective epitaxial growth film induces growth of the epitaxial film in a vertical direction and a horizontal direction.