KR20020045894A - Method for forming a isolation film - Google Patents
Method for forming a isolation film Download PDFInfo
- Publication number
- KR20020045894A KR20020045894A KR1020000075311A KR20000075311A KR20020045894A KR 20020045894 A KR20020045894 A KR 20020045894A KR 1020000075311 A KR1020000075311 A KR 1020000075311A KR 20000075311 A KR20000075311 A KR 20000075311A KR 20020045894 A KR20020045894 A KR 20020045894A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- forming
- oxide film
- device isolation
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Element Separation (AREA)
Abstract
본 발명의 소자분리막 형성 방법은 소자분리 영역의 반도체 기판상에 소자분리 산화막을 형성하고 활성 영역의 반도체 기판상에 에피택셜(Epitaxial)층을 형성하므로, 소자분리 산화막 형성후 패턴(Pattern) 밀도차에 따른 단차를 제거하 위한 사진 식각 공정과 평탄화하기 위한 시엠피(Chemical Mechanical Polishing: CMP) 등의 공정 단계을 줄여 소자 제조 비용 및 소요 시간을 저하시키는 특징이 있다.The device isolation film forming method of the present invention forms a device isolation oxide film on the semiconductor substrate in the device isolation region and an epitaxial layer on the semiconductor substrate in the active region. It reduces the manufacturing cost and time required for the device by reducing the process steps such as the photolithography process to remove the step by step and the chemical mechanical polishing (CMP) to planarize.
Description
본 발명은 소자분리막 형성 방법에 관한 것으로, 특히 소자분리 영역의 반도체 기판상에 소자분리 산화막을 형성하고 활성 영역의 반도체 기판상에 에피택셜(Epitaxial)층을 형성하여 소자 제조 비용 및 소요 시간을 저하시키는 소자분리막 형성 방법에 관한 것이다.The present invention relates to a method for forming an isolation layer, and in particular, an element isolation oxide film is formed on a semiconductor substrate in an isolation region and an epitaxial layer is formed on the semiconductor substrate in an active region to reduce device manufacturing cost and time required. It relates to a device isolation film forming method.
반도체 소자는 매년 집적도의 증가 추세를 보이고 있으며, 이러한 집적도의 증가는 소자 각각의 구성 요소 면적 및 크기의 감소를 수반하게 되어 여러 가지 공정상의 제약을 맞게 되는데 그 중에서 소자 분리가 문제된다.Semiconductor devices show an increasing trend in integration every year, and the increase in integration is accompanied by a reduction in the component area and size of each device, which results in various process constraints, among which device separation is a problem.
소자 분리 기술에는 크게 로코스(LOCOS)방법과 기판을 깍아 낸 다음에 CVD산화막으로 채운뒤에 평탄화하는 에스티아이(Shallow Trench Isolation: STI) 방법이 있다.Device isolation techniques include the LOCOS method and the Shallow Trench Isolation (STI) method, in which a substrate is scraped off and filled with a CVD oxide film and then planarized.
종래의 소자분리막 형성 방법은 도 1a에서와 같이, STI 방법에 있어서, 소자분리 영역이 정의된 반도체 기판(11)상에 패드(Pad) 산화막(12), 질화막(13) 및 제 1 감광막(14)을 순차적으로 형성한 다음, 상기 제 1 감광막(14)을 상기 소자분리 영역 상측에만 제거되도록 선택적으로 노광 및 현상한다.In the conventional method of forming a device isolation film, as shown in FIG. 1A, in the STI method, a pad oxide film 12, a nitride film 13, and a first photosensitive film 14 are formed on a semiconductor substrate 11 on which device isolation regions are defined. ) Is sequentially formed, and then the first photosensitive film 14 is selectively exposed and developed to be removed only above the device isolation region.
도 1b에서와 같이, 상기 선택적으로 노광 및 현상된 제 1 감광막(14)을 마스크로 상기 질화막(13), 패드 산화막(12) 및 반도체 기판(11)을 선택 식각하여 트렌치(15)를 형성한다.As shown in FIG. 1B, the trench 15 is formed by selectively etching the nitride film 13, the pad oxide film 12, and the semiconductor substrate 11 using the selectively exposed and developed first photosensitive film 14 as a mask. .
도 1c에서와 같이, 상기 제 1 감광막(14)을 제거한 다음, 상기 트렌치를 포함한 전면에 소자분리 산화막(16)을 형성한다.As shown in FIG. 1C, after removing the first photoresist layer 14, an isolation oxide layer 16 is formed on the entire surface including the trench.
여기서, 상기 소자분리 산화막(16) 형성 공정시, 패턴 밀도가 높은 부위(A)의 소자분리 산화막(16)이 패턴 밀도가 낮은 부위(B)의 소자분리 산화막(16)보다 높게 형성된다.Here, in the process of forming the device isolation oxide film 16, the device isolation oxide film 16 of the portion A having a high pattern density is formed higher than the device isolation oxide film 16 of the portion B having a low pattern density.
도 1d에서와 같이, 상기 소자분리 산화막(16)상에 제 2 감광막(17)을 도포하고, 상기 제 2 감광막(17)을 상기 단차가 낮은 부위인 패턴(Pattern) 밀도가 낮은부위(B)에만 남도록 선택적으로 노광 및 현상한다.As shown in FIG. 1D, a second photoresist layer 17 is coated on the device isolation oxide layer 16, and the second photoresist layer 17 has a low pattern density (B) where the step difference is low. It is selectively exposed and developed so as to remain only.
그리고, 상기 선택적으로 노광 및 현상된 제 2 감광막(17)을 마스크로 상기 소자분리 산화막(16)을 선택 식각하여 전면을 평탄화한다.The device isolation oxide layer 16 is selectively etched using the selectively exposed and developed second photoresist layer 17 to planarize the entire surface.
도 1e에서와 같이, 상기 제 2 감광막(17)을 제거한 후, 상기 질화막(13)을 식각 종말점으로 상기 소자분리 산화막(16)을 시엠피(Chemical Mechanical Polishing: CMP) 방법으로 평탄화 시킨다.As shown in FIG. 1E, after the second photoresist layer 17 is removed, the device isolation oxide layer 16 is planarized by a chemical mechanical polishing (CMP) method using the nitride layer 13 as an etching end point.
도 1f에서와 같이, 상기 반도체 기판(11)상에 형성된 질화막(13) 및 패드 산화막(12)을 제거한다.As shown in FIG. 1F, the nitride film 13 and the pad oxide film 12 formed on the semiconductor substrate 11 are removed.
종래의 소자분리막 형성 방법은 STI 방법에 있어서, 소자분리 산화막 형성후 패턴 밀도차에 따른 단차를 제거하 위한 사진 식각 공정과 평탄화하기 위한 CMP 등의 공정 단계가 복잡하여 소자 제조 비용 및 소요 시간이 증가되는 문제점이 있었다.In the conventional device isolation film forming method, in the STI method, a photolithography process for removing a step due to a pattern density difference after forming the device isolation oxide film and a process step such as CMP for planarization are complicated, thereby increasing device manufacturing cost and time required. There was a problem.
본 발명은 상기의 문제점을 해결하기 위해 안츨한 것으로 소자분리 영역의 반도체 기판상에 소자분리 산화막을 형성하고 활성 영역의 반도체 기판상에 에피택셜층을 형성하여 소자분리막 형성 공정 단계을 감소시키는 소자분리막 형성 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and the device isolation film is formed to reduce the process steps of forming the device isolation film by forming an isolation layer on the semiconductor substrate in the device isolation region and forming an epitaxial layer on the semiconductor substrate in the active region. The purpose is to provide a method.
도 1a내지 도 1f는 종래 기술에 따른 소자분리막 형성 방법을 나타낸 공정 단면도1A to 1F are cross-sectional views illustrating a method of forming a device isolation film according to the related art.
도 2a내지 도 2f는 본 발명의 실시 예에 따른 소자분리막 형성 방법을 나타낸 공정 단면도2A to 2F are cross-sectional views illustrating a method of forming a device isolation film according to an embodiment of the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
31 : 반도체 기판 32 : HDP 산화막31 semiconductor substrate 32 HDP oxide film
33 : 질화막 34 : 감광막33 nitride film 34 photosensitive film
35 : 라이너 산화막 36 : 에피택셜층35 liner oxide film 36 epitaxial layer
37 : 열산화막37: thermal oxide film
본 발명의 소자분리막 형성 방법은 활성 영역과 소자분리 영역이 정의된 반도체 기판상에 HDP 산화막과 질화막을 순차적으로 형성하는 단계, 상기 소자분리영역의 질화막상에 감광막 패턴을 형성하는 단계, 상기 감광막 패턴을 마스크로 상기 활성 영역의 질화막과 HDP 산화막을 식각한 후, 클리닝 공정을 진행하는 단계, 상기 감광막을 제거하고, 전면에 라이너 산화막을 형성하는 단계, 상기 반도체 기판과 HDP 산화막상의 라이너 산화막을 제거하는 단계, 상기 활성 영역의 반도체 기판상에 에피택셜층을 형성하는 단계, 상기 에피택셜층상에 열산화막을 성장시키는 단계 및 상기 열산화막과 질화막을 제거하는 단계를 포함하여 이루어짐을 특징으로 한다.The method of forming a device isolation film of the present invention comprises sequentially forming an HDP oxide film and a nitride film on a semiconductor substrate in which an active region and a device isolation region are defined, forming a photoresist pattern on the nitride film of the device isolation region, and the photoresist pattern. Etching the nitride layer and the HDP oxide layer in the active region using a mask, followed by a cleaning process, removing the photoresist layer, forming a liner oxide layer on the entire surface, and removing the liner oxide layer on the semiconductor substrate and the HDP oxide layer. Forming an epitaxial layer on the semiconductor substrate of the active region; growing a thermal oxide film on the epitaxial layer; and removing the thermal oxide film and the nitride film.
상기와 같은 본 발명에 따른 소자분리막 형성 방법의 바람직한 실시 예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Referring to the accompanying drawings, preferred embodiments of the device isolation film forming method according to the present invention as described above in detail as follows.
도 2a내지 도 2f는 본 발명의 실시 예에 따른 소자분리막 형성 방법을 나타낸 공정 단면도이다.2A to 2F are cross-sectional views illustrating a method of forming a device isolation film according to an exemplary embodiment of the present invention.
본 발명의 실시 예에 따른 소자분리막 형성 방법은 도 2a에서와 같이, 활성 영역과 소자분리 영역이 정의된 반도체 기판(31)상에 에이치디피(High Density Plasma: HDP) 산화막(32), 질화막(33) 및 감광막(34)을 순차적으로 형성한 다음, 상기 감광막(34)을 상기 소자분리 영역 상측에만 남도록 선택적으로 노광 및 현상한다.In the method of forming a device isolation film according to an embodiment of the present invention, as shown in FIG. 2A, a high density plasma (HDP) oxide film 32 and a nitride film (HDP) are formed on a semiconductor substrate 31 on which active regions and device isolation regions are defined. 33) and the photosensitive film 34 are sequentially formed, and then the photosensitive film 34 is selectively exposed and developed so as to remain only above the device isolation region.
여기서, 상기 HDP 산화막(32)을 2000 ∼ 5000Å의 두께로 형성하고, 상기 질화막(33)을 100 ∼ 1000Å의 두께로 형성한다.Here, the HDP oxide film 32 is formed to a thickness of 2000 to 5000 kPa, and the nitride film 33 is formed to a thickness of 100 to 1000 kPa.
상기 HDP 산화막(32) 대신에 SiO2막,SiON막, TiN막 또는 WN막으로 형성할 수있다.Instead of the HDP oxide film 32, an SiO 2 film , a SiON film, a TiN film, or a WN film may be formed.
상기 질화막(33)은 후 공정에서 산화막을 습식식각하는 공정시 상기 HDP 산화막(32)을 보호하는 역할을 한다.The nitride layer 33 serves to protect the HDP oxide layer 32 during the wet etching process of the oxide layer in a later process.
상기 감광막(34)을 사용한 사진 식각 공정은 활성 영역의 셀(Cell)의 최소 크기가 70mn까지 가능하며, 상기 셀의 크기에 따라 I-line, KrF 및 ArF 등의 리소그래피(Lithography) 공정을 사용한다.In the photolithography process using the photoresist layer 34, a minimum size of a cell of an active region may be up to 70mn, and a lithography process such as I-line, KrF, and ArF may be used according to the size of the cell. .
도 2b에서와 같이, 상기 선택적으로 노광 및 현상된 감광막(34)을 마스크로 사용하여 상기 활성 영역의 질화막(33)과 HDP 산화막(32)을 선택 식각한 후, 클리닝(Cleaning) 공정을 진행한다.As shown in FIG. 2B, after selectively etching the nitride layer 33 and the HDP oxide layer 32 of the active region using the selectively exposed and developed photoresist layer 34 as a mask, a cleaning process is performed. .
여기서, 상기 클리닝 공정은 상기 HDP 산화막(32) 식각 공정에서 형성된 산화막성 폴리머(Polymer)를 포함한 폴리머층을 제거하기 위한 습식 클리닝 공정으로 불소(F) 계열의 실리콘(Si) 또는 실리콘 산화막을 식각할 수 있는 HF와 비오이(Buffered Oxide Etcher: BOE) 등과 같은 화합물을 사용하여 실시한다.Here, the cleaning process is a wet cleaning process for removing a polymer layer including an oxide polymer formed in the HDP oxide layer 32 etching process, and the fluorine (F) -based silicon (Si) or silicon oxide layer may be etched. And compounds such as HF and BOE (Buffered Oxide Etcher).
도 2c에서와 같이, 상기 감광막(34)을 제거한 다음, 상기 질화막(33)을 포함한 전면에 10 ∼ 200Å두께의 라이너(Liner) 산화막(35)을 형성한다.As shown in FIG. 2C, after the photosensitive film 34 is removed, a liner oxide film 35 having a thickness of 10 to 200 μs is formed on the entire surface including the nitride film 33.
여기서, 상기 라이너 산화막(35) 대신에 SiO2막,SiON막, TiN막 또는 WN막으로 형성할 수 있다.The SiO 2 film , the SiON film, the TiN film, or the WN film may be formed instead of the liner oxide film 35.
상기 라이너 산화막(35)은 상기 HDP 산화막(32)의 전기적 절연 특성을 보안하는 역할을 한다.The liner oxide layer 35 serves to secure the electrical insulating properties of the HDP oxide layer 32.
도 2d에서와 같이, 상기 라이너 산화막(35)을 에치백하여 상기 반도체 기판(31)과 HDP 산화막(32)상의 라이너 산화막(35)을 제거한다.As shown in FIG. 2D, the liner oxide layer 35 is etched back to remove the liner oxide layer 35 on the semiconductor substrate 31 and the HDP oxide layer 32.
그리고, 상기 노출된 반도체 기판(31) 즉 활성 영역의 반도체 기판(31)상에 에스이지(Selective Epitaxial Growth: SEG) 공정으로 에피택셜(Epitaxial)층(36)을 형성한다.An epitaxial layer 36 is formed on the exposed semiconductor substrate 31, ie, the semiconductor substrate 31 in the active region by a selective epitaxial growth (SEG) process.
여기서, 상기 SEG 공정은 초고진공실에서 실리콘을 기상에서 증착시킬 수 있는 방법 또는 액상에서 실리콘을 성장시키는 방법을 포함한다.Here, the SEG process includes a method of depositing silicon in the vapor phase in an ultra-high vacuum chamber or a method of growing silicon in a liquid phase.
도 2e에서와 같이, 상기 에피택셜층(36)의 상부가 산화되도록 전면에 열산화 공정을 진행하여 상기 에피택셜층(36)상에 열산화막(37)을 성장시킨다.As illustrated in FIG. 2E, a thermal oxidation process is performed on the entire surface of the epitaxial layer 36 to oxidize it to grow a thermal oxide film 37 on the epitaxial layer 36.
여기서, 상기 열산화막(37)의 성장 공정으로 상기 에피택셜층(36) 형성 이후 표면의 단차 방지 및 상기 에피택셜층(36)의 형성 모양에 따른 보이드(Void) 발생을 방지한다.In this case, after the epitaxial layer 36 is formed in the growth process of the thermal oxide layer 37, it is possible to prevent the step difference of the surface and the generation of voids according to the shape of the epitaxial layer 36.
도 2f에서와 같이, 상기 열산화막(37)을 습식식각하여 제거한 다음, 상기 질화막(33)을 제거한다.As shown in FIG. 2F, the thermal oxide film 37 is removed by wet etching, and then the nitride film 33 is removed.
본 발명의 소자분리막 형성 방법은 소자분리 영역의 반도체 기판상에 소자분리 산화막을 형성하고 활성 영역의 반도체 기판상에 에피택셜층을 형성하므로, 소자분리 산화막 형성후 패턴 밀도차에 따른 단차를 제거하 위한 사진 식각 공정과 평탄화하기 위한 CMP 등의 공정 단계을 줄여 소자 제조 비용 및 소요 시간을 저하시키는 효과가 있다.In the device isolation film forming method of the present invention, since the device isolation oxide film is formed on the semiconductor substrate in the device isolation region and the epitaxial layer is formed on the semiconductor substrate in the active region, the step difference caused by the pattern density difference is eliminated after the device isolation oxide film is formed. By reducing the photolithography process and the process step such as CMP to planarize, there is an effect of reducing the device manufacturing cost and time required.
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000075311A KR100685581B1 (en) | 2000-12-11 | 2000-12-11 | Device Separator Formation Method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000075311A KR100685581B1 (en) | 2000-12-11 | 2000-12-11 | Device Separator Formation Method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20020045894A true KR20020045894A (en) | 2002-06-20 |
| KR100685581B1 KR100685581B1 (en) | 2007-02-22 |
Family
ID=27680996
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000075311A Expired - Fee Related KR100685581B1 (en) | 2000-12-11 | 2000-12-11 | Device Separator Formation Method |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100685581B1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100503935B1 (en) * | 2001-09-20 | 2005-07-26 | 미쓰비시덴키 가부시키가이샤 | Method of manufacturing semiconductor device |
| KR100569510B1 (en) * | 2004-06-16 | 2006-04-07 | 주식회사 하이닉스반도체 | Device Separator Formation Method of Semiconductor Device |
| WO2008140250A1 (en) * | 2007-05-14 | 2008-11-20 | Nest Corp. | Reverse gap-fill method for semiconductor device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101006508B1 (en) | 2003-07-23 | 2011-01-07 | 매그나칩 반도체 유한회사 | Device Separating Method of Semiconductor Device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06101518B2 (en) * | 1985-10-14 | 1994-12-12 | 富士通株式会社 | Method of manufacturing integrated circuit |
| KR940009579B1 (en) * | 1992-02-24 | 1994-10-15 | 삼성전자주식회사 | Manufacturing Method of Semiconductor Device |
| KR100219523B1 (en) * | 1997-01-10 | 1999-09-01 | 윤종용 | Semiconductor device with high device isolation and manufacturing method |
| KR20000003360A (en) * | 1998-06-27 | 2000-01-15 | 김영환 | Forming method of device isolation film using selective epitaxial growth technique |
-
2000
- 2000-12-11 KR KR1020000075311A patent/KR100685581B1/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100503935B1 (en) * | 2001-09-20 | 2005-07-26 | 미쓰비시덴키 가부시키가이샤 | Method of manufacturing semiconductor device |
| KR100569510B1 (en) * | 2004-06-16 | 2006-04-07 | 주식회사 하이닉스반도체 | Device Separator Formation Method of Semiconductor Device |
| WO2008140250A1 (en) * | 2007-05-14 | 2008-11-20 | Nest Corp. | Reverse gap-fill method for semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100685581B1 (en) | 2007-02-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6429123B1 (en) | Method of manufacturing buried metal lines having ultra fine features | |
| KR100870616B1 (en) | Methods of Forming Trench Isolation Regions | |
| US6071792A (en) | Methods of forming shallow trench isolation regions using plasma deposition techniques | |
| US5930646A (en) | Method of shallow trench isolation | |
| US6015757A (en) | Method of oxide etching with high selectivity to silicon nitride by using polysilicon layer | |
| KR100685581B1 (en) | Device Separator Formation Method | |
| KR100677998B1 (en) | Shallow Trench Isolation Method for Semiconductor Devices | |
| US6103581A (en) | Method for producing shallow trench isolation structure | |
| KR100559553B1 (en) | Shallow Trench Isolation Method for Semiconductor Devices | |
| KR20010008560A (en) | Method For Forming The Isolation Layer Of Semiconductor Device | |
| KR20030059482A (en) | Method of forming isolating layer for semiconductor device | |
| KR100760908B1 (en) | Manufacturing Method of Semiconductor Device | |
| KR100561513B1 (en) | Shallow trench isolation method for semiconductor devices | |
| KR100849064B1 (en) | Method for forming an element isolation film of a semiconductor element | |
| KR100632683B1 (en) | Shallow Trench Isolation Method | |
| KR19990074726A (en) | Separation layer of semiconductor device and forming method thereof | |
| KR100303365B1 (en) | Method of manufacturing SOI substrate | |
| KR20050059703A (en) | Method for forming isolation layer of semiconductor device | |
| JPH05218191A (en) | Manufacture of semiconductor device having different-width inter-element isolating regions | |
| KR20100032039A (en) | Method for manufacturing shallow trench isolation of semiconductor device | |
| KR20040001913A (en) | Method for forming trench type isolation layer in semiconductor device | |
| KR20010095656A (en) | Method for manufacturing isolation of semiconductor device | |
| KR20050003046A (en) | Method of manufacturing isolation using liner nitride | |
| KR20050012652A (en) | Method for forming element isolation layer of semiconductor device | |
| KR20010112739A (en) | An active area widening method in trench isolation process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 20001211 |
|
| PG1501 | Laying open of application | ||
| A201 | Request for examination | ||
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 20050922 Comment text: Request for Examination of Application Patent event code: PA02011R01I Patent event date: 20001211 Comment text: Patent Application |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20061026 Patent event code: PE09021S01D |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 20070108 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 20070214 Patent event code: PR07011E01D |
|
| PR1002 | Payment of registration fee |
Payment date: 20070213 End annual number: 3 Start annual number: 1 |
|
| PG1601 | Publication of registration | ||
| PR1001 | Payment of annual fee |
Payment date: 20100126 Start annual number: 4 End annual number: 4 |
|
| FPAY | Annual fee payment |
Payment date: 20110126 Year of fee payment: 5 |
|
| PR1001 | Payment of annual fee |
Payment date: 20110126 Start annual number: 5 End annual number: 5 |
|
| LAPS | Lapse due to unpaid annual fee | ||
| PC1903 | Unpaid annual fee |