KR20020044204A - Method for measuring barrier potential for unit pixel in image sensor - Google Patents
Method for measuring barrier potential for unit pixel in image sensor Download PDFInfo
- Publication number
- KR20020044204A KR20020044204A KR1020000073183A KR20000073183A KR20020044204A KR 20020044204 A KR20020044204 A KR 20020044204A KR 1020000073183 A KR1020000073183 A KR 1020000073183A KR 20000073183 A KR20000073183 A KR 20000073183A KR 20020044204 A KR20020044204 A KR 20020044204A
- Authority
- KR
- South Korea
- Prior art keywords
- barrier potential
- test pattern
- gate electrode
- unit pixel
- image sensor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 230000004888 barrier function Effects 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims abstract description 5
- 238000005259 measurement Methods 0.000 claims abstract description 4
- 238000000691 measurement method Methods 0.000 claims abstract description 3
- 239000012535 impurity Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 10
- 238000009792 diffusion process Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/80—Constructional details of image sensors
- H10F39/803—Pixels having integrated switching, control, storage or amplification elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
본 발명은 이미지센서의 단위픽셀의 베리어 포텐셜을 정확히 측정하는 방법을 제공하고자하는 것으로, 이를 위한 본 발명의 이미지센서 단위 픽셀의 베리어 포텐셜 측정방법은, 단위 픽셀과 동일한 구조의 제1테스트패턴과, 베리어 포텐셜이 존재하지 않는 제2테스트패턴을 형성하고, 상기 제1 및 제2 테스트패턴을 동일한 조건에서 I-V 측정을 실시하여 상기 단위 픽셀의 베리어 포텐셜을 측정하는 것을 특징으로 한다.The present invention is to provide a method for accurately measuring the barrier potential of the unit pixel of the image sensor, the barrier potential measurement method of the image sensor unit pixel of the present invention, the first test pattern of the same structure as the unit pixel, A second test pattern in which no barrier potential exists is formed, and the first and second test patterns are subjected to IV measurement under the same conditions to measure the barrier potential of the unit pixel.
Description
본 발명은 CMOS 이미지센서에 관한 것으로, 특히 단위 픽셀에서 베리어 포텐셜(barrier potential)을 측정하기 위한 방법에 관한 것이다.TECHNICAL FIELD The present invention relates to CMOS image sensors, and more particularly to a method for measuring barrier potential at a unit pixel.
잘 알려진 바와 같이 이미지센서 소자는 포토다이오드 영역에서 집적된 광전하를 센싱노드로 전달시켜 센싱노드의 전위의 변화를 감지하므로써 광신호를 전자신호로 바꾸어 준다.As is well known, an image sensor device converts an optical signal into an electronic signal by transferring a photocharge integrated in a photodiode region to a sensing node and detecting a change in potential of the sensing node.
이때 포토다이오드를 구성하는 실리콘 표면 부근의 불순물이 트랜스퍼 트랜지스터의 채널 부위로 확산되어 포토다이오드 내에서 생성된 광전하를 센싱노드로 이동하려는 전하 흐름에 베리어로써 작용을 하고, 이를 베리어 포텐셜이라 한다.At this time, impurities near the surface of the silicon constituting the photodiode diffuse into the channel region of the transfer transistor and act as a barrier to the charge flow to move the photocharge generated in the photodiode to the sensing node, which is called a barrier potential.
이러한 베리어 포텐셜은 저조도에서 출력신호가 나오지 않는 데드죤(dead zone)을 형성시켜 저조도 특성을 악화시킨다.This barrier potential deteriorates low light characteristics by forming a dead zone in which an output signal does not come out at low light.
그러므로 베리어 포텐셜을 감소시켜야 하고, 이를 위해서는 베리어 포텐셜을 정확히 측정하는 것이 매우 중요한데, 현재의 이미지센서는 단위 픽셀의 베리어 포텐셜을 정확히 측정할 수 있는 패턴이 없었기 때문에 단위 픽셀의 정확한 특성을 확인할 수 없었다.Therefore, it is very important to measure the barrier potential accurately. For this purpose, the current image sensor could not confirm the exact characteristics of the unit pixel because there was no pattern to accurately measure the barrier potential of the unit pixel.
본 발명은 이미지센서의 단위픽셀의 베리어 포텐셜을 정확히 측정하는 방법을 제공하는데 그 목적이 있다.It is an object of the present invention to provide a method for accurately measuring the barrier potential of a unit pixel of an image sensor.
도 1 내지 도 4는 이미지센서소자의 픽셀내 베리어 포텐셜을 측정할 수 있는 테스트패턴들의 보여주는 도면,1 to 4 illustrate test patterns capable of measuring intra-pixel barrier potential of an image sensor device.
도5는 제1 및 제2 테스트패턴의 I-V 곡선.5 is an I-V curve of the first and second test patterns.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
101 : 기판 102 : 필드산화막101: substrate 102: field oxide film
103 : 트랜스퍼트랜지스터의 게이트전극 104 : N형분술물층103: gate electrode of the transfer transistor 104: N-type powder layer
105 : P형불순물층 106 : 플로팅확산층105: P-type impurity layer 106: floating diffusion layer
상기 목적을 달성하기 위한 본 발명의 이미지센서 단위 픽셀의 베리어 포텐셜 측정방법은, 단위 픽셀과 동일한 구조의 제1테스트패턴과, 베리어 포텐셜이 존재하지 않는 제2테스트패턴을 형성하고, 상기 제1 및 제2 테스트패턴을 동일한 조건에서 I-V 측정을 실시하여 상기 단위 픽셀의 베리어 포텐셜을 측정하는 것을 특징으로 한다.In order to achieve the above object, the barrier potential measurement method of an image sensor unit pixel according to an embodiment of the present invention may include forming a first test pattern having the same structure as that of a unit pixel and a second test pattern having no barrier potential, The barrier potential of the unit pixel is measured by performing IV measurement on the second test pattern under the same conditions.
상기 본 발명에서, 상기 제1테스트패턴은 기판 상에 트랜스퍼 트랜지스터의 게이트전극이 패턴되어 있고, 상기 게이트전극의 일측방의 상기 기판에는 상기 게이트전극의 일측에지에 동일하게 정렬된 제1도전형불순물층 및 제2도전형불순물층에 의해 베리드포토다이오드가 형성되고, 상기 게이트전극의 타측방 기판 내에는 플로팅확산층이 형성되며, 상기 제2테스트패턴은 상기 제1테스트패턴과 동일한 구조를 가지되, 제2도전형의 불순물층이 상기 게이트전극의 일측에지로부터 수 ㎛ 이격되어 형성된 것을 특징으로 한다.In the present invention, in the first test pattern, a gate electrode of a transfer transistor is patterned on a substrate, and a first conductive impurity that is aligned on one side edge of the gate electrode on the substrate on one side of the gate electrode. The buried photodiode is formed by the layer and the second conductive impurity layer, and a floating diffusion layer is formed in the other side substrate of the gate electrode, and the second test pattern has the same structure as the first test pattern. The impurity layer of the second conductivity type is formed by being spaced several micrometers from one edge of the gate electrode.
이와 같이 본 발명은 실제 단위 픽셀과 동일한 제1테스트패턴과 베리어 포텐셜이 형성되지 않는 제2테스트패턴을 이미지센서 소자의 소정부위(실제소자가 형성되지 않은 웨이퍼의 여백)에 만들어, 각각에서 I-V 특성을 측정함으로써 베리어 포텐셜을 측정해 내는 것이다.As described above, the present invention makes the first test pattern identical to the actual unit pixel and the second test pattern in which the barrier potential is not formed on a predetermined portion of the image sensor device (the margin of the wafer on which the actual device is not formed), respectively. By measuring the barrier potential is measured.
이에 의해 실제 단위 픽셀내에서 측정 불가능한 베리어 포텐셜을 측정할 수 있다.This makes it possible to measure barrier potentials that are not measurable within the actual unit pixels.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도 1 내지 도 4는 이미지센서소자의 픽셀내 베리어 포텐셜을 측정할 수 있는 테스트패턴들의 보여준다. 도 1 및 도 3은 실제 단위 픽셀과 동일한 제1테스트패턴의 평면도 및 단면도이고, 도 2 및 도 4는 베리어 포텐셜이 없는 제2테스트패턴의 평면도 및 단면도이다.1 to 4 show test patterns for measuring intra-pixel barrier potential of an image sensor device. 1 and 3 are plan and cross-sectional views of the same first test pattern as the actual unit pixel, and FIGS. 2 and 4 are plan and cross-sectional views of the second test pattern without barrier potential.
먼저, 제1테스트패턴은 실제 단위 픽셀과 동일한 구조를 갖는 것으로, 도 1 및 도 3을 참조하면, P형기판(101) 상에 트랜스퍼 트랜지스터의 게이트전극(103)이 패턴되어 있고, 게이트전극(103)의 일측방 기판(101)에는 N형불순물층(104) 및 P형불순물층(105)에 의해 베리드 포토다이오드(BPD)가 형성되고, 게이트전극(103)의 타측방 기판(101) 내에는 센싱노드인 플로팅확산층(FD)(106)이 형성되어 있다. 도면부호 102는 필드산화막을 나타낸다.First, the first test pattern has the same structure as the actual unit pixel. Referring to FIGS. 1 and 3, the gate electrode 103 of the transfer transistor is patterned on the P-type substrate 101, and the gate electrode ( The buried photodiode BPD is formed on the one side substrate 101 of the 103 by the N-type impurity layer 104 and the P-type impurity layer 105, and the other side substrate 101 of the gate electrode 103 is formed. A floating diffusion layer (FD) 106 is formed in the sensing node. Reference numeral 102 denotes a field oxide film.
여기서, N형불순물층(104) 및 P형불순물층(105)은 게이트전극(103)의 일측벽이 오픈된 상태에서 이온주입에 의해 형성되는 바, 두 불순물층은 모두 게이트전극(103)의 일측 에지에 정렬되어 형성되게 된다.Here, the N-type impurity layer 104 and the P-type impurity layer 105 are formed by ion implantation with one side wall of the gate electrode 103 open, and both impurity layers are formed on the gate electrode 103. It is formed to be aligned to one edge.
이때, P형불순물층(105)은 고농도로 형성되는 바, P형 불순물이 게이트전극(103) 하부의 채널 부위로 확산되어 베리어 포텐셜을 형성하게 된다.At this time, the P-type impurity layer 105 is formed at a high concentration, so that the P-type impurity diffuses into the channel portion under the gate electrode 103 to form a barrier potential.
다음, 제2테스트패턴은 베리어 포텐셜이 없는 구조로서, 도 2 및 도4를 참조하면, 제1테스트패턴과 동일한 구조를 가지되, P형불순물층(105a)이 제1테스트패턴의 P형불순물층(105)과는 다르게 게이트전극(103)의 일측에지로부터 일정간격(수㎛) 이격되어 있다. 때문에 어느정도 P형불순물층(105)의 불순물이 확산되더라도 베리어 포텐셜은 없게 된다.Next, the second test pattern has no barrier potential. Referring to FIGS. 2 and 4, the second test pattern has the same structure as the first test pattern, and the P-type impurity layer 105a is formed of the P-type impurity of the first test pattern. Unlike the layer 105, the gate electrode 103 is spaced apart from one edge of the gate electrode 103 by a predetermined interval. Therefore, even if impurities of the P-type impurity layer 105 diffuse to some extent, there is no barrier potential.
도 3과 도 4를 보면 알 수 있듯이, 제1테스트패턴은 고농도 저에너지로 이온주입에 의해 형성되는 P형불순물층(105)이 트랜스퍼 트랜지스터의 게이트전극(103) 아래쪽 가까이까지 확산되어 전하(전자) 흐름의 베리어로써 작용을 하지만, 제2테스트패턴은 P형불순물층(105a)이 게이트전극(103)에서 수 um 정도 떨어져 있기 때문에 광전하의 흐름에는 거의 영향을 미치지 않게 된다.As can be seen from FIGS. 3 and 4, in the first test pattern, the P-type impurity layer 105 formed by ion implantation at high concentration and low energy is diffused to the lower side of the gate electrode 103 of the transfer transistor to be charged (electrons). Although acting as a barrier of flow, the second test pattern has little effect on the flow of photocharges because the P-type impurity layer 105a is a few um away from the gate electrode 103.
이러한 점을 이용하여 두 테스트패턴에서 동시에 동일한 조건으로 I-V 특성 테스트를 실시해보면 도 5에 나타난 것과 같이 피닝전압(Pinning Voltage) 차이(φbarrier)가 발생되게되고, 이 피닝전압의 차이가 베리어 포텐셜이 된다.Using this point, if the IV characteristic test is conducted simultaneously under the same conditions in both test patterns, a pinning voltage difference (φ barrier ) is generated as shown in FIG. do.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명은 단위픽셀 내 베리어 포텐셜을 측정할 수 있어, 이미지 센서 소자의 기본 단위인 픽셀의 특성 향상을 위한 데이터를 마련할 수 있고, 이에 의해 이미지센서의 특성을 향상시킬 수 있다.According to the present invention, the barrier potential in a unit pixel can be measured, so that data for improving the characteristics of the pixel, which is a basic unit of the image sensor element, can be provided, thereby improving the characteristics of the image sensor.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000073183A KR20020044204A (en) | 2000-12-05 | 2000-12-05 | Method for measuring barrier potential for unit pixel in image sensor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000073183A KR20020044204A (en) | 2000-12-05 | 2000-12-05 | Method for measuring barrier potential for unit pixel in image sensor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20020044204A true KR20020044204A (en) | 2002-06-15 |
Family
ID=27679514
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000073183A Withdrawn KR20020044204A (en) | 2000-12-05 | 2000-12-05 | Method for measuring barrier potential for unit pixel in image sensor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20020044204A (en) |
-
2000
- 2000-12-05 KR KR1020000073183A patent/KR20020044204A/en not_active Withdrawn
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8093633B2 (en) | Method and device for wavelength-sensitive photo-sensing | |
| JP4171820B2 (en) | Cumulative chemical / physical phenomenon detector | |
| US6294133B1 (en) | Multiple detecting apparatus for physical phenomenon and/or chemical phenomenon | |
| US5736756A (en) | Solid-state image sensing device with lght shielding film | |
| US20110236263A1 (en) | Combined Detector | |
| CN101556962B (en) | Image sensor with sensing transistor having two gates and method of operating the same | |
| US6563320B1 (en) | Mask alignment structure for IC layers | |
| US20060145202A1 (en) | Image sensor and method for forming isolation structure for photodiode | |
| JP2020109851A (en) | Gate-controlled charge modulated device for cmos image sensor | |
| KR102760736B1 (en) | Measurement Method of Image Sensor | |
| KR20090071067A (en) | Image sensor and its manufacturing method | |
| US9976981B2 (en) | Device for detecting chemical/physical phenomenon having a diffusion layer formed between an input charge control region and a sensing region on a substrate | |
| KR20020044204A (en) | Method for measuring barrier potential for unit pixel in image sensor | |
| KR100803502B1 (en) | Test pattern and manufacturing method of image sensor for measuring sheet resistance | |
| KR100705215B1 (en) | Image sensor with test pattern and test method | |
| US7030434B1 (en) | Arrangement with image sensors | |
| US20010015428A1 (en) | Solid-state image sensor and manufacturing method therefor | |
| KR100429568B1 (en) | Image sensor for measuring the sheet resistance and fabricating method of the same | |
| KR100873293B1 (en) | Image sensor to prevent crosstalk | |
| KR20040092827A (en) | Cmos image sensor with test pattern and the method for test | |
| KR20040093279A (en) | Cmos image sensor with test pattern and test method | |
| US6984817B2 (en) | CMOS-type photodetector for improved charge transfer from the photodetector to a MOS transistor | |
| KR20060020411A (en) | Image sensor capable of measuring capacitance and leakage current and its capacitance measurement method | |
| KR100399938B1 (en) | Image sensor for measuring the dark signal | |
| KR100735624B1 (en) | Test pattern of the image sensor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 20001205 |
|
| PG1501 | Laying open of application | ||
| N231 | Notification of change of applicant | ||
| PN2301 | Change of applicant |
Patent event date: 20041006 Comment text: Notification of Change of Applicant Patent event code: PN23011R01D |
|
| PC1203 | Withdrawal of no request for examination | ||
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |