KR20020041486A - method of driving plasma display panel - Google Patents

Abstract

The present invention proposes a method for analyzing the characteristics of a ramp wave, while ensuring that conditions can have the same output wall voltage even when an input wall voltage of various conditions is applied to a lamp pulse, the plasma can be applied to an optimal driving condition. A driving method of a display panel is provided.

The driving method includes a plurality of display cells (discharge cells) having at least two electrodes, and after the reset and / or erase pulses are applied to the display cells to form the same wall voltage, the sustain discharge voltage A method of driving a plasma display panel which emits light by applying a discharge to the display panel, the output wall voltage characteristic curve corresponding to the change of the input wall voltage caused by the wall charge of all the display cells is measured so as to overlap each characteristic curve. It is characterized by using a corresponding voltage as a condition of a reset pulse or an erase pulse.

Description

Method of driving plasma display panel

The present invention relates to a method of driving a plasma display panel, and more particularly, to stable operation of a plasma display panel by generating a constant output wall voltage regardless of an input wall voltage in a reset pulse or an erase pulse in a surface discharge plasma display panel. The present invention relates to a method of driving a plasma display panel.

1 and 2 are schematic plan views and cross-sectional views of a discharge cell, which is one display cell for explaining the configuration of a surface discharge AC plasma display panel that emits light continuously by a memory effect caused by wall charges on a dielectric layer. 1 and 2, in the plasma display panel, a front electrode group formed of the X electrode 3 and the Y electrode 4 is formed on the front substrate 1, and a dielectric layer 6 is formed thereon. do. In addition, an address electrode 5 is formed on the opposite rear substrate 2 of the front substrate 1, a dielectric layer 7 is formed thereon, and discharge gas is formed between the front substrate 1 and the front substrate 1. The partition 8 is formed to give a constant discharge space to be charged, and R, G, and B fluorescent layers 9 are formed between the partitions 8.

The driving method applied to the plasma display panel configured as described above includes an address / oil dielectric separation method (disclosed in Japanese Patent Laid-Open Publication No. Hei 4-195188 (1992)) and an address / oil dielectric multiple method (Japanese Patent Number). 2,528,195), but mainly an address / dielectric field separation method is applied. As shown in FIG. 3, one field (frame) is displayed for gray scale display, for example. The subfields are divided into first to eighth subfields, and each subfield is composed of a reset period, an address period, and a sustain period, and each subfield is set with a specific sustain period. The gray level of the screen is displayed.

In the reset period of each subfield, all Y electrodes first become 0V level, and at the same time, a front write pulse of high voltage (approximately 330V) is applied to the X electrode so that all display lines of all subfields are irrelevant. Discharge is performed in all the cells. The address electrode potential at this time is about 100V. The wall charges are accumulated on the dielectric layers 6 and 7 covering the X electrode 3 and the Y electrode 4 by such front discharge. In other words, negative charges are accumulated on the X electrode 3 and positive charges are accumulated on the Y electrode 4. Next, the potentials of the X electrode and the address electrode become 0 V, and the discharge starts when the voltage of the wall charge itself exceeds the discharge start voltage in all the cells. This discharge is self-neutralized and the discharge ends. So-called self-erasing discharge. By this self-erasing discharge, the state of all the cells in the panel is made into a uniform state without wall charges, whereby the next address (write) discharge can be stabilized. In addition, as shown in FIG. 3, a priming erase pulse may be selectively applied. This priming erase pulse further discharges the cells whose wall charges are not completely erased to initialize all the cells completely. Such an initialization process is an essential process for distinguishing each subfield when a gray level is expressed by dividing one field into a plurality of subfields.

Next, in the address period, address discharge is sequentially performed in order to turn on / off the cells in accordance with the display data. First, a predetermined voltage (approximately 50 V) is applied to the X electrode, a scan pulse (approximately -150 V) is sequentially applied to the Y electrode, and a cell causing sustain discharge in the address electrode (A electrode), i.e., is turned on. An address pulse (approximately 50 V) is selectively applied to the address electrode corresponding to the cell, so that a discharge occurs between the address electrode and the Y electrode of the cell to be lit, thereby accumulating wall charges capable of sustain discharge. Further, a predetermined voltage (about -50 V) is applied to the Y electrode to which the scan pulse is not applied so that no discharge occurs.

Thereafter, in the sustain discharge period, a sustain pulse (about 180 V) is applied to the Y electrode and the X electrode alternately to perform sustain discharge, thereby performing image display in one subfield. That is, in a cell in which wall charge is accumulated in an address period, discharge occurs because the voltage caused by the wall charge overlaps the sustain discharge pulse. However, in a cell in which wall charge is not accumulated in the address period, even if the sustain discharge pulse is applied, the discharge is not performed. By not generating, image display of one subfield can be performed. In addition, a voltage of about 100 V is applied to the address electrode in order to avoid discharge between the address electrode and the X electrode or the Y electrode. In this " address / sustain discharge separation method ", the luminance is determined by the length and duration of the sustain discharge period, that is, the number of sustain pulses.

In the circuit for the above driving method, although not shown, the address pulse at the time of address discharge is applied to the address electrode 5 by the address driver, and the address driver is controlled by the control circuit. The Y electrodes 4 are each connected to a Y scan driver, the scan driver is connected to a common driver on the Y side, pulses during address discharge are generated by the scan driver, and sustain pulses and the like are common on the Y side. Generated by the driver, these pulses are applied to the Y electrode 4 via the Y scan driver. The common driver on the Y side is controlled by the common driver control unit provided in the panel drive control unit, and the Y scan driver is controlled by the scan driver control unit installed in the panel drive control unit. The X electrodes 3 are commonly connected through all the display lines of the plasma display panel. The common driver on the X side generates a full screen write pulse, a sustain pulse, and the like, and is controlled by the common driver control unit. The common driver control unit, the scan driver control unit and the control circuit are controlled by the vertical synchronizing signal and the horizontal synchronizing signal input to the panel driving control unit from the outside of the apparatus, the display data signal input to the display data control unit and the clock. In addition, the display data signal input in accordance with the clock is stored in the frame memory.

Recently, a weak discharge occurs during discharge in a PDP to realize a high contrast, and in particular, ramp waves are used to initialize and equalize all the cells in the driving pulses so as to linearly control the output wall voltage. I use it. That is, as shown in the pulse waveform diagram of FIG. 4, in the method of driving a plasma display panel manufactured by Panasonic, lamp waves are employed as reset pulses and erase pulses.

However, the complete study and results of the above-described characteristics of the lamp wave have not been properly disclosed, and the optimum conditions are also being studied.

Therefore, the present invention provides a method for analyzing the characteristics of the above-described ramp wave, while ensuring that the optimum driving conditions can be achieved by securing a condition that can have the same output wall voltage even if the input wall voltage of various conditions is applied to the lamp pulse. It is an object of the present invention to provide a method of driving a plasma display panel that can be applied.

1 is a schematic partial plan view for explaining the configuration of a three-electrode plasma display panel;

2 is a schematic partial cross-sectional view for explaining the configuration of a three-electrode plasma display panel;

3 is a pulse waveform diagram for explaining a driving method of a three-electrode plasma display panel;

4 is a pulse waveform diagram for explaining a driving method employing a conventional reset pulse and an erase pulse using a ramp wave;

5 is a graph for explaining a driving method based on a characteristic curve of an output wall voltage generated by a lamp wave according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

1: front board 2: back board

3: X electrode 3 ', 4': bus electrode

3 ", 4": black matrix 4,14: Y electrode

5: address electrode 6, 7: dielectric layer

8: partition 9: fluorescent layer

In order to achieve the above object, a driving method of a plasma display panel according to an exemplary embodiment of the present invention includes a plurality of display cells (discharge cells) having at least two electrodes, and a reset pulse and / or Or a method of driving a plasma display panel that emits light by applying an erase pulse to form a same wall voltage and then applying a sustain discharge voltage to discharge the light. The output wall voltage characteristic curve is measured and is designed using a voltage corresponding to a range where each characteristic curve overlaps as a condition of a reset pulse or an erase pulse.

Design waveforms such that the condition is achieved in a lower voltage and a wider range of voltages corresponding to the range where the characteristic curves overlap, and also design a waveform of a voltage of a range that can initialize the wall charges at the address electrode It is preferable.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 5 is a graph for describing a driving method of obtaining a characteristic curve of an output wall voltage generated by a ramp wave according to an embodiment of the present invention, and driving under conditions designed therefrom.

One embodiment of the present invention is applied to the drive pulse of the AC PDP, as shown in Figures 1 to 2, the plasma display panel, a plurality of front surface is formed parallel to the back surface of the front substrate (1) Multiple formed on the rear substrate 2 opposite the front electrode group X, Y so as to form a display cell at an intersection with the electrode group X, Y and the front electrode group X, Y, respectively. Fluorescence formed on the address electrode 5 of the dielectric layer, the dielectric layers 6 and 7 formed on the front electrode groups X and Y and the address electrode 5, and the dielectric layer 7 on the address electrode 5, respectively. It comprises a layer (9).

In the driving method, as shown in Fig. 3, one field (frame) is divided into a plurality of subfields (subframes), and each subfield is divided into a reset period, an address period, and a sustain discharge period. A reset voltage is applied to at least a portion of the front electrode group (X, Y) and the address electrode 5 so as to uniformly initialize the wall charges of the display cells, and discharge is performed to each cell having a predetermined state in the address period. By selectively applying an address voltage in accordance with the display data to accumulate charges corresponding to the display data for each cell, and applying a sustain discharge voltage to each cell in the sustain discharge period to generate a discharge in a cell where a predetermined charge is accumulated. The light emission is performed, and each subfield has a different sustain discharge period, whereby the subfields are combined to display gradations.

However, in the reset period, the reset pulse and the erase pulse of the ramp wave as shown in FIG. 4 are applied. The present invention proposes a design condition and an optimization condition for the reset pulse and / or the erase pulse of such a ramp wave and its voltage.

That is, FIG. 5 shows the change of the output wall voltage Vwout generated by applying a ramp wave having a slope of 1.5V / ㎲ in a state (△) where the input wall voltage is 0V and a state (-) where the input wall voltage is -150V. It was heard.

The experimental result shows that when the input wall voltage is 0V, the peak voltage of the ramp wave continuously discharges from about 213V to 350V, and the output wall voltage is controlled to slope 1.

In addition, when the input wall voltage is -150V, the weak discharge occurs at about 60V and the output wall voltage is controlled by the slope 1, and the self-discharge discharge occurs near 260V, indicating that the wall voltage is reduced to 0V.

It can be seen that the portion where the above two curves overlap, that is, the same portion as in the 220V to 256V portion, has the same output wall voltage (Vwout), which is equal to the output wall voltage regardless of the state of the input wave voltage of the ramp wave. Make sure you know it.

Therefore, such a condition can be applied to the drive waveform of the PDP which needs to make the output wall voltage the same while generating the weak discharge like the lamp wave and minimizing the intensity of the emitted light. Specifically, it is essential to determine the voltage condition of the reset pulse and the voltage condition of the erase pulse.

In the above-described method of the present invention, the conditions for the experimental results may be used by applying not only ramp waves but also pulses of various shapes and experimenting with the above-described conditions. This can greatly affect the driving characteristics of the actual PDP, for example, main characteristics such as dynamic margin, brightness and contrast. In addition, a drive waveform may be employed in which the output wall voltage is controlled by a characteristic having a slowing factor of 1 with respect to the external voltage by using a ramp wave, and a waveform capable of arbitrarily using the output variation voltage is inserted.

In addition, the above-described experimental conditions in the present invention, for the purpose of designing to implement the above conditions at the lowest possible voltage and low discharge discharge amount in the study of all structures, discharge gas, waveform, etc. using the AC PDP. May be used.

According to the configuration and operation of the method of driving the plasma display panel according to the embodiment of the present invention described above, the discharge characteristic in sustain discharge can be improved from the output wall voltage characteristic curve according to the change of the input wall voltage, and the contrast can be improved. Not only can this be improved, but margins are improved and PDP panel design is proposed.

Claims (6)

It comprises a plurality of display cells (discharge cells) having at least two electrodes, and applies the reset pulses and / or erase pulses to the display cells to form the same wall voltage, and then emits the light by applying a sustain discharge voltage. In the method of driving a plasma display panel, Characterized by the output wall voltage characteristic curve according to the change of the input wall voltage due to the wall charge of all the display cells by using a voltage corresponding to the overlapping range of each characteristic curve as a reset pulse or erase pulse condition A method of driving a plasma display panel. The driving method of claim 1, wherein the waveform is designed such that a condition is achieved at a lower voltage and a wider range of voltages corresponding to overlapping ranges of the characteristic curves. The method of driving a plasma display panel according to claim 1 or 2, wherein a waveform of a voltage in a range in which wall charges at the address electrode can be initialized is designed. 3. The plasma display panel according to claim 1 or 2, wherein the plasma display panel includes a plurality of front electrode groups (X, Y) formed in parallel with the rear surface of the front substrate (1), and the front electrode groups (X, Y). A plurality of address electrodes 5 formed on the rear substrate 2 so as to face the front electrode groups X and Y so as to form display cells at intersections thereof, and the front electrode groups X and Y and addresses thereof; Dielectric layers 6 and 7 formed on the electrodes 5 and fluorescent layers 9 formed on the dielectric layers 7 on the address electrodes 5, respectively. The driving method includes one field (frame). ) Is divided into a plurality of subfields (subframes), each subfield is divided into a reset period, an address period and a sustain discharge period, and the front electrode group ( A discharge is applied by applying a reset voltage to at least a portion of the X and Y and the address electrodes 5, In the address period, an address voltage is selectively applied to each cell in a predetermined state in accordance with the display data to accumulate charge corresponding to the display data for each cell, and a sustain discharge voltage is applied to each cell in the sustain discharge period. A discharge method is performed in a cell in which charge is accumulated, thereby causing light emission, and each subfield has a different sustain discharge period so that gray levels are displayed by combining each subfield. 3. A range according to claim 1 or 2, wherein the range overlapping from the output wall voltage characteristic curve obtained by a ramp wave having an input wall voltage of 0 V and -150 V and a slope of 1.5 V / ㎲ is between about 220 V and 256 V. A method of driving a plasma display panel. The plasma display according to claim 1 or 2, wherein a waveform in which the output wall voltage can be arbitrarily used by controlling the output wall voltage by using a ramp wave as a characteristic having a slowing factor of 1 with respect to the external voltage is inserted. How to drive the panel.