KR20020034373A - Method for forming metal wire of semiconductor device - Google Patents
Method for forming metal wire of semiconductor device Download PDFInfo
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- KR20020034373A KR20020034373A KR1020000064592A KR20000064592A KR20020034373A KR 20020034373 A KR20020034373 A KR 20020034373A KR 1020000064592 A KR1020000064592 A KR 1020000064592A KR 20000064592 A KR20000064592 A KR 20000064592A KR 20020034373 A KR20020034373 A KR 20020034373A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 종래에는 구리 배선과 상부 질화산화막의 낮은 접착특성으로 인해 높은 전류밀도를 갖게 되어 구리원자가 계면을 통해 쉽게 이동하여 초소형 설계 배선의 전자이동 수명이 짧아지기 때문에 신뢰성이 저하되는 문제점이 있었다. 따라서, 본 발명은 하부배선이 형성된 반도체기판의 상부에 층간절연막을 증착한 다음 비아콘택홀과 배선 부분을 식각하는 공정과; 상기 결과물의 상부전면에 확산방지층을 증착한 다음 구리를 진공증착하고, 계속적으로 전기도금하여 비아콘택과 배선을 형성하는 공정과; 상기 배선의 상부에 접착촉진층으로 구리와 반응성이 좋은 Ti 또는 Cr을 얇게 증착하는 공정과; 상기 결과물의 상부전면에 후속 산화막 내부로의 구리확산을 방지하기 위하여 질화산화막을 증착하는 공정으로 이루어지는 반도체소자의 금속배선 형성방법을 통해 구리와 반응성이 좋은 금속인 Ti 또는 Cr을 얇게 증착하여 접착촉진층을 형성함에 따라 구리 배선과 접착촉진층의 계면 접착력이 향상되므로, 계면을 통한 구리원자의 이동을 억제하여 초소형 설계 배선의 전자이동 수명을 향상시킴으로써, 신뢰성을 향상시킬 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device. In the related art, a low current property of a copper wiring and an upper nitride oxide film has a high current density, and thus copper atoms move easily through an interface, so that the electron transfer life of the micro-designed wiring is increased. There is a problem that the reliability is lowered because it becomes short. Therefore, the present invention comprises the steps of depositing an interlayer insulating film on the upper portion of the semiconductor substrate on which the lower wiring is formed, and then etching the via contact hole and the wiring portion; Depositing a diffusion barrier layer on the upper surface of the resultant, vacuum depositing copper, and subsequently electroplating to form via contacts and wirings; Thinly depositing Ti or Cr, which is highly reactive with copper, as an adhesion promoter layer on the wiring; Thin metal deposition of Ti or Cr, which is highly reactive with copper, promotes adhesion through a method of forming a metal wiring of a semiconductor device, which comprises a process of depositing a nitride oxide film on the upper surface of the resultant to prevent copper diffusion into a subsequent oxide film. As the layer is formed, the interfacial adhesion between the copper wiring and the adhesion promoting layer is improved, thereby suppressing the movement of copper atoms through the interface to improve the electron transfer life of the micro-designed wiring, thereby improving reliability.
Description
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 특히 비아콘택 및 배선 물질로 구리를 적용한 구리 듀얼 다마신(copper dual damascene) 공정에서 초소형 설계 배선(sub-micron design)의 신뢰성을 향상시키기에 적당하도록 한 반도체소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and in particular, to improve reliability of sub-micron designs in a copper dual damascene process using copper as a via contact and wiring material. The present invention relates to a method for forming a metal wiring of a semiconductor device so as to be suitable.
종래 반도체소자의 금속배선은 도1의 단면도에 도시한 바와같이 하부배선이 형성된 반도체기판(1)의 상부에 층간절연막(2)을 증착한 다음 비아콘택홀과 배선 부분을 식각한다.In the metal wiring of the conventional semiconductor device, as shown in the cross-sectional view of FIG. 1, an interlayer insulating film 2 is deposited on the semiconductor substrate 1 on which the lower wiring is formed, and then the via contact hole and the wiring portion are etched.
그리고, 상기 결과물의 상부전면에 확산방지층(3)을 증착한 다음 구리(4)를 진공증착하고, 계속적으로 전기도금하여 비아콘택과 배선을 형성한다.Then, the diffusion barrier layer 3 is deposited on the upper surface of the resultant product, and the copper 4 is vacuum-deposited, and subsequently electroplated to form via contacts and wirings.
이후에, 상기 결과물의 상부전면에 후속 산화막 내부로의 구리확산을 방지하기 위하여 질화산화막(5)을 증착한다.Thereafter, an oxide nitride film 5 is deposited on the upper surface of the resultant to prevent copper diffusion into the subsequent oxide film.
이때, 초소형 설계 배선의 경우에는 배선 선폭의 크기가 결정립(grain)의 크기보다 작기 때문에 배선 내 결정립 경계(grain boundary)가 적은 대나무(bamboo)구조가 된다.In this case, since the size of the wiring line width is smaller than the grain size in the case of the micro-designed wiring, a bamboo structure having fewer grain boundaries in the wiring is obtained.
따라서, 전자이동(electromigration) 현상을 일으키는 원자이동 경로가 배선 표면이 되어 배선과 상부층과의 접착력이 매우 중요해진다.Therefore, the atomic migration path causing the electromigration phenomenon becomes the wiring surface, and the adhesion between the wiring and the upper layer becomes very important.
그러나, 구리(4) 배선의 경우에는 상부의 질화산화막(5)과 낮은 접착특성으로 인해 높은 전류밀도를 갖게 되어 구리원자가 계면을 통해 쉽게 이동하여 초소형 설계 배선의 전자이동 수명이 기존의 알루미늄 배선보다 오히려 짧아질 수 있다.However, in the case of copper (4) wiring, due to the high adhesion density of the oxide nitride film (5) on the upper side and high current density, copper atoms easily move through the interface, so that the electron transfer life of the micro-designed wiring is higher than that of the conventional aluminum wiring. Rather, it can be shortened.
왜냐하면, 알루미늄 배선의 경우에는 표면에 생성되는 자연산화막과 강한 접착특성을 갖게 되므로, 계면을 통한 원자이동을 억제하여 초소형 설계 배선의 전자이동 수명이 길기 때문이다.This is because, in the case of aluminum wiring, since it has a strong adhesive property with the natural oxide film formed on the surface, the electron transfer life of the micro-designed wiring is long by suppressing atomic movement through the interface.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 비아콘택 및 배선 물질로 구리를 적용한 구리 듀얼 다마신 공정에서 계면을 통한 구리원자의 이동을 억제하여 초소형 설계 배선의 전자이동 수명을 향상시킬 수 있는 반도체소자의 금속배선 형성방법을 제공하는데 있다.The present invention was devised to solve the conventional problems as described above, and an object of the present invention is to minimize the movement of copper atoms through the interface in the copper dual damascene process in which copper is applied as via contact and wiring material. The present invention provides a method for forming a metal wiring of a semiconductor device that can improve the electron transfer life of the wiring.
도1은 종래 반도체소자의 금속배선 구조를 보인 단면도.1 is a cross-sectional view showing a metal wiring structure of a conventional semiconductor device.
도2는 본 발명에 의한 반도체소자의 금속배선 구조를 보인 단면도.2 is a cross-sectional view showing a metal wiring structure of a semiconductor device according to the present invention.
도3은 종래기술과 본 발명의 비교 그래프도.Figure 3 is a comparison graph of the prior art and the present invention.
***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***
11:반도체기판12:층간절연막11: semiconductor substrate 12: interlayer insulating film
13:확산방지막14:구리13: Diffusion barrier 14: Copper
15:접착촉진층16:산화질화막15: adhesion promoting layer 16: oxynitride film
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자의 금속배선 형성방법은 하부배선이 형성된 반도체기판의 상부에 층간절연막을 증착한 다음 비아콘택홀과 배선 부분을 식각하는 공정과; 상기 결과물의 상부전면에 확산방지층을 증착한 다음 구리를 진공증착하고, 계속적으로 전기도금하여 비아콘택과 배선을 형성하는 공정과; 상기 배선의 상부에 접착촉진층으로 구리와 반응성이 좋은 Ti 또는 Cr을 얇게 증착하는 공정과; 상기 결과물의 상부전면에 후속 산화막 내부로의 구리확산을 방지하기 위하여 질화산화막을 증착하는 공정을 구비하여 이루어지는 것을 특징으로 한다.A method of forming a metal wiring of a semiconductor device as described above includes: depositing an interlayer insulating film on an upper portion of a semiconductor substrate on which lower wiring is formed, and then etching via contact holes and wiring portions; Depositing a diffusion barrier layer on the upper surface of the resultant, vacuum depositing copper, and subsequently electroplating to form via contacts and wirings; Thinly depositing Ti or Cr, which is highly reactive with copper, as an adhesion promoter layer on the wiring; And depositing a nitride oxide film on the upper surface of the resultant to prevent copper diffusion into the subsequent oxide film.
상기한 바와같은 본 발명에 의한 반도체소자의 금속배선 형성방법을 첨부한도면을 참조하여 상세히 설명하면 다음과 같다.The metal wiring forming method of the semiconductor device according to the present invention as described above will be described in detail with reference to the accompanying drawings.
도2는 본 발명에 의한 금속배선의 구조를 보인 단면도로서, 이에 도시한 바와같이 하부배선이 형성된 반도체기판(11)의 상부에 층간절연막(12)을 증착한 다음 비아콘택홀과 배선 부분을 식각한다.FIG. 2 is a cross-sectional view illustrating a structure of a metal wiring according to the present invention. As shown in FIG. 2, an interlayer insulating film 12 is deposited on an upper portion of a semiconductor substrate 11 on which a lower wiring is formed, and then a via contact hole and a wiring portion are etched. do.
그리고, 상기 결과물의 상부전면에 확산방지층(13)을 증착한 다음 구리(14)를 진공증착하고, 계속적으로 전기도금하여 비아콘택과 배선을 형성한다.Then, after the diffusion barrier layer 13 is deposited on the upper surface of the resultant, copper 14 is vacuum-deposited and continuously electroplated to form via contacts and wiring.
그리고, 상기 구리(14) 배선의 상부에 무전해 도금(electroless plating) 방법이나 또는 선택적 박막증착(selective reactive chemical vapor deposition) 방법을 통해 구리(14)와 반응성이 좋은 금속인 Ti 또는 Cr을 얇게 증착하여 접착촉진층(adhesion promoter layer : APL, 15)을 형성한다. 따라서, 상기 구리(14) 배선과 접착촉진층(15)의 계면 접착력이 향상되므로, 도3에 도시한 종래기술(a)과 본 발명(b)의 비교 그래프도에서 알 수 있듯이 계면을 통한 구리원자의 이동을 억제하여 초소형 설계 배선의 전자이동 수명을 향상시킬 수 있게 된다.In addition, a thin layer of Ti or Cr, which is highly reactive with copper 14, is deposited on the copper 14 via an electroless plating method or a selective reactive chemical vapor deposition method. To form an adhesion promoter layer (APL, 15). Therefore, since the interface adhesion between the copper 14 wiring and the adhesion promotion layer 15 is improved, as can be seen from the comparative graph of the prior art (a) and the invention (b) shown in FIG. By restraining the movement of atoms, it is possible to improve the electron transfer life of micro-designed wiring.
이후에, 상기 결과물의 상부전면에 후속 산화막 내부로의 구리확산을 방지하기 위하여 질화산화막(16)을 증착한다.Thereafter, an oxide nitride film 16 is deposited on the upper surface of the resultant to prevent copper diffusion into the subsequent oxide film.
상술한 바와같이 본 발명에 의한 반도체소자의 금속배선 형성방법은 구리와 반응성이 좋은 금속인 Ti 또는 Cr을 얇게 증착하여 접착촉진층을 형성함에 따라 구리 배선과 접착촉진층의 계면 접착력이 향상되므로, 계면을 통한 구리원자의 이동을 억제하여 초소형 설계 배선의 전자이동 수명을 향상시킴으로써, 신뢰성을 향상시킬 수 있는 효과가 있다.As described above, the method for forming a metal wiring of the semiconductor device according to the present invention improves the interfacial adhesion between the copper wiring and the adhesion promoting layer by forming a thin film of Ti or Cr, which is highly reactive with copper, to form an adhesion promoting layer. By suppressing the movement of copper atoms through the interface to improve the electron transfer life of the micro-designed wiring, there is an effect that can improve the reliability.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100519169B1 (en) * | 2003-05-09 | 2005-10-06 | 매그나칩 반도체 유한회사 | Method of forming metal line of semiconductor devices |
| KR100986813B1 (en) * | 2008-05-30 | 2010-10-08 | 몽 필 김 | Red Pepper Sterilization and Iron Remover |
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| JPH10261635A (en) * | 1997-03-18 | 1998-09-29 | Mitsubishi Electric Corp | Semiconductor device |
| KR19990040755A (en) * | 1997-11-19 | 1999-06-05 | 김영환 | Metal wiring layer contact formation method of semiconductor device |
| KR19990059087A (en) * | 1997-12-30 | 1999-07-26 | 김영환 | Metal wiring formation method of semiconductor device |
| KR20010076493A (en) * | 2000-01-26 | 2001-08-16 | 윤종용 | An interconnection structure formed by damascene process of semiconductor device |
| KR20010100810A (en) * | 2000-03-08 | 2001-11-14 | 가나이 쓰토무 | Semiconducting system and production method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100519169B1 (en) * | 2003-05-09 | 2005-10-06 | 매그나칩 반도체 유한회사 | Method of forming metal line of semiconductor devices |
| KR100986813B1 (en) * | 2008-05-30 | 2010-10-08 | 몽 필 김 | Red Pepper Sterilization and Iron Remover |
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