KR20020014225A - Integrated device having insulator layer in trench overlapped with fine inductor and method for foming the same - Google Patents
Integrated device having insulator layer in trench overlapped with fine inductor and method for foming the same Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 10
- 239000012212 insulator Substances 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 65
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 35
- 239000010703 silicon Substances 0.000 claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 claims abstract description 16
- 238000002955 isolation Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000010410 layer Substances 0.000 description 3
- 239000002131 composite material Substances 0.000 description 2
- 206010017577 Gait disturbance Diseases 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000729 poly(L-lysine) polymer Polymers 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/645—Inductive arrangements
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Abstract
본 발명은 인덕터와 중첩되는 실리콘 기판 부분의 저항을 증가시켜 인덕터의 에너지 손실 및 인덕턴스의 감소를 방지할 수 있는, 미세 인덕터와 중첩되는 트렌치 내에 절연막을 구비하는 집적 소자 및 그 제조 방법에 관한 것이다. 인덕터의 에너지 손실을 적게 하려면 자기장이 지나가는 기판 아래 부분의 저항을 증가시키면 된다. 본 발명은 인덕터와 중첩되는 반도체 기판을 식각하여 반도체 기판 내부에 산화막 등의 절연막을 채워 저항값을 크게 증가시키는데 그 특징이 있다. 이러한 특징을 갖는 본 발명은 인덕터와 중첩된 반도체 기판 부분에 다수개 형성되며 그 각각의 내부에 절연막이 매립된 트렌치를 구비하는 집적 소자 및 그 제조 방법을 제공한다.The present invention relates to an integrated device having an insulating film in a trench overlapping with a fine inductor and to a method of manufacturing the same, which can increase the resistance of the portion of the silicon substrate overlapping the inductor to prevent the reduction of energy loss and inductance of the inductor. To reduce the energy loss of the inductor, increase the resistance underneath the substrate through which the magnetic field passes. The present invention is characterized in that the semiconductor substrate overlapping the inductor is etched to fill an insulating film such as an oxide film in the semiconductor substrate, thereby greatly increasing the resistance value. SUMMARY OF THE INVENTION The present invention having such a feature provides an integrated device having a plurality of trenches formed in a portion of a semiconductor substrate overlapping an inductor and having an insulating film embedded therein, and a method of manufacturing the same.
Description
본 발명은 고집적 소자 제조 분야에 관한 것으로, 특히 실리콘 기판 상부에 미세 인덕터를 구비하는 고집적 소자에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of highly integrated device manufacturing, and more particularly, to a highly integrated device having a fine inductor on a silicon substrate.
종래 초고주파 소자의 설계 및 제조에는 화합물 반도체인 GaAs(갈륨비소) 기판이 이용되고 있다. GaAs 반도체 기판은 반절연(semi-insulator) 특성을 가지고 있으므로 도 1a 및 도 1b에 각각 도시한 바와 같은 나선 구조의 인덕터(spiral inductor)를 GaAs 상부에 집적할 경우 기판 저항에 의한 에너지 손실이 크지 않다.Conventionally, GaAs (gallium arsenide) substrates, which are compound semiconductors, have been used for the design and manufacture of microwave devices. Since GaAs semiconductor substrates have semi-insulator characteristics, when the spiral inductor as shown in FIGS. 1A and 1B is integrated on top of GaAs, energy loss due to substrate resistance is not large. .
한편, 실리콘 기판을 이용한 고집적 소자 제조 기술이 급속도로 발전하여 감에 따라, 초고주파 소자, 아날로그 소자 및 디지털 소자를 포함하는 복합 소자를 하나의 실리콘 기판 상에 구현하려는 노력이 많이 이루어지고 있다. 이러한 복합 소자를 실리콘 기판 상에 구현하고자 하는데 가장 큰 어려움 중의 하나가 미세 인덕터를 제조하는 일이다. 실리콘 기판은 기판 자체의 저항이 갈륨비소 기판 보다 훨씬 작아서 기판 저항에 의한 인덕터의 에너지 손실이 크기 때문에 이 문제의 해결에 대한 많은 연구가 진행되어 오고 있다.On the other hand, as the technology for manufacturing highly integrated devices using silicon substrates has been rapidly developed, many efforts have been made to implement composite devices including ultra-high frequency devices, analog devices, and digital devices on a single silicon substrate. One of the biggest difficulties in implementing such a composite device on a silicon substrate is to manufacture a fine inductor. Since the silicon substrate has a much smaller resistance than the gallium arsenide substrate, the energy loss of the inductor due to the substrate resistance is large, and much research has been conducted to solve this problem.
도 2는 p + 실리콘 기판(10) 상의 산화막(11) 위에 나선 구조의 인덕터(12)가 형성된 것을 보이는 단면도이다. 도 2와 같이 실리콘 기판(10) 상부에 나선 구조의 인덕터(12)를 형성하였을 때, 인덕턴스(L)는 다음의 수학식1에 보이는 바와 같이 시간에 따라 변화하는 자기장(B)과 전류(I)의 관계식에 의하여 결정된다.2 is a cross-sectional view showing a spiral inductor 12 formed on the oxide film 11 on the p + silicon substrate 10. When the inductor 12 having a spiral structure is formed on the silicon substrate 10 as shown in FIG. 2, the inductance L is a magnetic field B and a current I varying with time as shown in Equation 1 below. Is determined by the relationship
도 2와 같은 구조에서 인덕터에 흐르는 전류가 시간에 따라 변화하면 자기장이 형성된다. 이와 같이 형성된 자기장은 기판의 깊은 부분까지 이어지고 기판의 저항이 작을 경우에는 시간에 따른 자기장의 변화에 의해 기판에도 전류가 발생한다. 기판 전류의 변화에 의해 자기장이 또다시 형성되는데 그 방향은 원래 생성된 자기장과는 반대 방향을 가져 전체적으로 자기장의 세기는 감소한다. 따라서, 소자에 인가되는 전류변화에 의해 인덕턴스가 감소되고 작은 기판 저항에 의한 에너지 손실이 추가되므로 인덕터의 효율이 크게 저하된다. 더구나 MOSFET 소자의 크기가 작아짐에 따라 발생하는 단채널 효과(short channel effect)의 방지를 위해 기판 및 웰(well)의 도핑 농도가 높아지고 이에 따라 기판 저항이 점점 더 작아지고 있어 인덕터의 구현에 더욱 큰 걸림돌이 되고 있다.In the structure shown in FIG. 2, when the current flowing through the inductor changes with time, a magnetic field is formed. The magnetic field formed as described above extends to the deep portion of the substrate, and when the resistance of the substrate is small, current also occurs in the substrate due to the change of the magnetic field over time. The magnetic field is formed again by the change of the substrate current, the direction of which is opposite to the originally generated magnetic field, and the intensity of the magnetic field as a whole decreases. Therefore, the inductance is reduced by the current change applied to the device, and the energy loss due to the small substrate resistance is added, thereby greatly reducing the efficiency of the inductor. In addition, the doping concentration of the substrate and the well is increased to prevent short channel effects caused by the smaller MOSFET device, and thus the substrate resistance is getting smaller and smaller. It is a stumbling block.
진성 실리콘 반도체의 도핑농도는 1010/㎤이고, 집적소자 제조에 보통 이용되는 실리콘 기판의 도전형은 p형이며 도핑 농도는 1015/㎤ 내외이다. 실리콘 기판에 웰을 형성할 때는 통상적으로 1017/㎤농도의 불순물을 도핑한다. 따라서 웰 형성이 완료된 실리콘 기판 상부에 인덕터를 제조하였을 때에는 기판 저항이 작을 수 밖에 없다. 그러므로 실리콘 기판 상에 인덕터를 제조함에 있어 기판 저항에 의한 문제점이 우선적으로 해결되어야 한다.The intrinsic silicon semiconductor has a doping concentration of 10 10 / cm 3, the conductivity of a silicon substrate commonly used in integrated device fabrication is p-type, and the doping concentration is about 10 15 / cm 3. When the wells are formed on the silicon substrate, the dopants are typically doped at a concentration of 10 17 / cm 3. Therefore, when the inductor is manufactured on the silicon substrate on which the well formation is completed, the substrate resistance is small. Therefore, in manufacturing the inductor on the silicon substrate, the problem caused by the substrate resistance must be solved first.
상기와 같은 문제점을 해결하기 위한 본 발명은, 인덕터와 중첩되는 실리콘 기판 부분의 저항을 증가시켜 인덕터의 에너지 손실 및 인덕턴스의 감소를 방지할 수 있는, 미세 인덕터와 중첩되는 트렌치 내에 절연막을 구비하는 집적 소자 및 그 제조 방법을 제공하는데 목적이 있다.SUMMARY OF THE INVENTION The present invention for solving the above problems is to increase the resistance of the portion of the silicon substrate overlapping the inductor to prevent the reduction of energy loss and inductance of the inductor, integrated with an insulating film in the trench overlapping the fine inductor It is an object to provide a device and a method of manufacturing the same.
도 1a 및 도 1b는 나선 구조의 인덕터 형상을 보이는 평면도,1A and 1B are plan views showing a spiral inductor shape;
도 2는 종래 기술에 따라 p + 실리콘 기판 상의 산화막 위에 나선 구조의 인덕터가 형성된 것을 보이는 단면도,2 is a cross-sectional view showing that a spiral inductor is formed on an oxide film on a p + silicon substrate according to the prior art;
도 3a 및 도 3b는 본 발명의 실시예에 따른 집적 소자 제조 공정 단면도,3A and 3B are cross-sectional views of an integrated device fabrication process according to an embodiment of the present invention;
도 4는 한개의 트렌치에 절연막을 매립할 경우 발생하는 디싱 현상을 보이는 공정 단면도.4 is a cross-sectional view illustrating a dishing phenomenon occurring when an insulating film is buried in one trench;
*도면의 주요부분에 대한 도면 부호의 설명** Description of reference numerals for the main parts of the drawings *
30: 실리콘 기판 31: 산화막30: silicon substrate 31: oxide film
In: 인덕터In: Inductor
상기와 같은 목적을 달성하기 위한 본 발명은, 반도체 기판 상부에 인덕터를 구비하는 집적 소자에 있어서 반도체 기판; 인덕터 중첩 영역의 상기 반도체 기판 내에 형성된 적어도 한개의 트렌치; 상기 트렌치 내에 매립된 절연막; 상기 인덕터 중첩 영역의 상기 반도체 기판을 덮는 적어도 한층의 절연막; 상기 절연막 상에 형성된 인덕터를 포함하는 집적 소자를 제공한다.The present invention for achieving the above object is an integrated device having an inductor on the semiconductor substrate; At least one trench formed in the semiconductor substrate in an inductor overlap region; An insulating film embedded in the trench; At least one insulating film covering the semiconductor substrate in the inductor overlap region; An integrated device including an inductor formed on the insulating film is provided.
또한 상기 목적을 달성하기 위한 본 발명은, 실리콘 기판을 마련하는 제1 단계; 상기 실리콘 기판을 선택적으로 식각하여 상기 실리콘 기판 상부에 형성될 인덕터와 중첩되는 적어도 한개의 트렌치를 형성하는 제2 단계; 상기 트렌치 내에 절연막을 매립하는 제3 단계; 상기 실리콘 기판을 덮는 적어도 한층의 절연막을 형성하는 제4 단계; 및 상기 절연막 상에 상기 트렌치와 중첩되는 인덕터를 형성하는 제5 단계를 포함하는 집적 소자 제조 방법을 제공한다.In addition, the present invention for achieving the above object, the first step of providing a silicon substrate; Selectively etching the silicon substrate to form at least one trench overlapping an inductor to be formed on the silicon substrate; A third step of embedding an insulating film in the trench; A fourth step of forming at least one insulating film covering the silicon substrate; And forming a inductor overlapping the trench on the insulating layer.
인덕터의 에너지 손실을 적게 하려면 자기장이 지나가는 기판 아래 부분의 저항을 증가시키면 된다. 본 발명은 인덕터와 중첩되는 반도체 기판을 식각하여 반도체 기판 내부에 산화막 등의 절연막을 채워 저항값을 크게 증가시키는데 그 특징이 있다. 이러한 특징을 갖는 본 발명은 인덕터와 중첩된 반도체 기판 부분에 다수개 형성되며 그 각각의 내부에 절연막이 매립된 트렌치를 구비하는 집적 소자 및 그 제조 방법을 제공한다.To reduce the energy loss of the inductor, increase the resistance underneath the substrate through which the magnetic field passes. The present invention is characterized in that the semiconductor substrate overlapping the inductor is etched to fill an insulating film such as an oxide film in the semiconductor substrate, thereby greatly increasing the resistance value. SUMMARY OF THE INVENTION The present invention having such a feature provides an integrated device having a plurality of trenches formed in a portion of a semiconductor substrate overlapping an inductor and having an insulating film embedded therein, and a method of manufacturing the same.
이하, 첨부된 도면 도 3a 및 도 3b 그리고 도 4를 참조하여 본 발명의 실시예에 따른 집적 소자 및 그 제조 방법을 상세하게 설명한다.Hereinafter, an integrated device and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to FIGS. 3A, 3B, and 4.
먼저 도 3a에 도시한 바와 같이, P형 실리콘 기판(30)에 소자분리를 위한 STI(shallow trench isolation) 공정을 진행하는 과정에서 인덕터와 중첩될 실리콘 기판(30) 내에 다수의 트렌치를 병렬로 형성하고, 상기 전체 구조 상에 산화막(31)을 증착하고 평탄화 공정을 실시하여 트렌치 내부에만 산화막(31)이 잔류하도록 한다.First, as illustrated in FIG. 3A, in the process of performing a shallow trench isolation (STI) process for device isolation on the P-type silicon substrate 30, a plurality of trenches are formed in parallel in the silicon substrate 30 to overlap the inductor. The oxide film 31 is deposited on the entire structure and the planarization process is performed so that the oxide film 31 remains only in the trench.
다수의 트렌치를 대신하여 하나의 트렌치를 형성할 수도 있다. 그러나 인덕터와 중첩되는 실리콘 기판(30) 부분에 하나의 트렌치를 형성할 경우 트렌치의 면적이 넓어진다. 그에 따라, 트렌치 내부에 산화막을 매립한 다음 실시하는 연마 등의 평탄화 공정 후에 도 4에 보이는 바와 같이 트렌치 내에 매립된 산화막의 일부가 손실되는 디싱(dishing) 현상이 발생하여 소자의 특성을 저하시킬 우려가 있다. 이러한 문제점은 도 3a에 보이는 바와 같이 인덕터와 중첩되는 실리콘 기판(30)에 다수의 트렌치를 형성함으로써 해결할 수 있다.Instead of multiple trenches, one trench may be formed. However, when one trench is formed in the portion of the silicon substrate 30 overlapping the inductor, the area of the trench is widened. As a result, a dishing phenomenon occurs in which a portion of the oxide film embedded in the trench is lost, as shown in FIG. 4, after a planarization process such as polishing, which is performed after the oxide film is embedded in the trench, thereby deteriorating characteristics of the device. There is. This problem can be solved by forming a plurality of trenches in the silicon substrate 30 overlapping the inductor as shown in FIG. 3A.
전술한 바와 같이 인덕터와 중첩되는 실리콘 기판(30) 내에 다수의 트렌치를 형성하고, 상기 트렌치 내에 절연막을 매립한 이후에는, 인덕터와 함께 다양한 소자를 실리콘 기판(30) 상에 집적시킨다.As described above, after forming a plurality of trenches in the silicon substrate 30 overlapping the inductor, and filling the insulating layer in the trench, various elements are integrated on the silicon substrate 30 together with the inductor.
도 3b는 전술한 공정에 따라 STI 공정에서 인덕터 중첩영역의 실리콘 기판(30) 부분에 다수의 트렌치를 형성하고 산화막(31)을 매립한 다음, 실리콘 기판 내에 형성된 n 웰(31) 및 p웰(32) 상에 각각 PMOS 트랜지스터 및 NMOS 트랜지스터의 게이트 절연막(34), 게이트 전극(35), 절연막 스페이서(36) 및 소오스·드레인(37)을 형성하고, 층간절연막(38), 제1 금속배선(M1), 제1 금속배선간 절연막(39), 제2 금속배선(M2), 제2 금속배선간 절연막(40)을 형성한 다음, 인덕터 중첩영역의 실리콘 기판(30)을 덮고 있는 제2 금속배선간 절연막(40) 상에 인덕터(In)를 형성한 상태를 보이고 있다. 도 3b에 도시한 집적 소자는 최상 금속층으로 인덕터를 형성하고 자기장(B)이 지나가는 경로의 대부분이 절연막이므로 에너지 손실을 최소할 수 있다.3B shows a plurality of trenches formed in the silicon substrate 30 portion of the inductor overlap region in the STI process, the oxide film 31 is buried, and the n well 31 and p well ( The gate insulating film 34, the gate electrode 35, the insulating film spacer 36, and the source drain 37 of the PMOS transistor and the NMOS transistor are formed on the 32, and the interlayer insulating film 38 and the first metal wiring ( M1), the first intermetallic insulating film 39, the second metal wiring M2, and the second intermetallic insulating film 40 are formed, and then the second metal covering the silicon substrate 30 in the inductor overlap region. The inductor In is formed on the inter-wire insulating film 40. The integrated device shown in FIG. 3B forms an inductor as the uppermost metal layer and most of the path through which the magnetic field B passes is an insulating film, thereby minimizing energy loss.
전술한 바와 같이 이루어지는 본 발명은 VCO, PLL, 전력증폭기(power amplifier), 저잡음증폭기(low noise amplifier) 등과 같은 초고주파 소자에 응용될 수 있다.The present invention as described above can be applied to ultra-high frequency devices such as VCOs, PLLs, power amplifiers, low noise amplifiers, and the like.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 실리콘 웨이퍼 상에 큰 기판 저항을 필요로하는 집적 인덕터를 형성할 수 있어 종래 아날로그 소자, 디지털 소자 및 고주파 소자를 하나의 칩(chip) 집적할 수 있으므로 전체 시스템의 크기가 줄어 소형, 경량화를 실현할 수 있다. 또한, GaAs 기판 보다 단가가 싼 실리콘 기판 상에 기존 CMOS 제조 공정의 변화없이 인덕터를 구현할 수 있어 제조 비용을 절감시킬 수 있다.The present invention made as described above can form an integrated inductor that requires a large substrate resistance on a silicon wafer, and thus can integrate a conventional analog device, digital device, and high frequency device into one chip, thereby reducing the size of the entire system. It is possible to realize compactness and weight reduction. In addition, inductors can be implemented on silicon substrates that are cheaper than GaAs substrates without changing the conventional CMOS manufacturing process, thereby reducing manufacturing costs.
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| KR100829067B1 (en) * | 2003-12-10 | 2008-05-19 | 더 리전트 오브 더 유니버시티 오브 캘리포니아 | Low crosstalk substrate for mixed-signal integrated circuits |
| KR100880794B1 (en) * | 2002-07-05 | 2009-02-02 | 매그나칩 반도체 유한회사 | Inductor of semiconductor device and forming method thereof |
| KR100889556B1 (en) * | 2007-08-31 | 2009-03-23 | 주식회사 동부하이텍 | Inductor of semiconductor device and manufacturing method thereof |
| KR101044389B1 (en) * | 2004-07-23 | 2011-06-29 | 매그나칩 반도체 유한회사 | Inductor Formation Method of Semiconductor Device |
| KR20170029126A (en) | 2015-09-07 | 2017-03-15 | 전자부품연구원 | Passive device and manufacturing method thereof |
| CN114823638A (en) * | 2022-04-27 | 2022-07-29 | 电子科技大学 | Integrated inductance structure with low parasitic capacitance |
| US11600690B2 (en) | 2018-02-11 | 2023-03-07 | Danmarks Tekniske Universitet | Power converter embodied in a semiconductor substrate member |
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