KR20010093456A - Method of forming interconnections in semiconductor devices - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a wiring connection part of a semiconductor device. In particular, a barrier layer of a contact plug electrically connected to an upper electrode or a bit line of a capacitor is plated by an ionized metal plasma method. After depositing and forming the first tungsten layer having the type grains, the second tungsten layer is deposited by chemical vapor deposition to form a contact plug, thereby preventing volkeno phenomenon and forming a uniform second tungsten layer to form foreign matter such as bumps. The present invention relates to a method for forming a barrier layer for contact plugs in a semiconductor device, which prevents formation and forms a second tungsten layer at a high pressure, thereby shortening a deposition time and improving process efficiency. A method of forming a wiring connection part of a semiconductor device according to the present invention includes forming an insulating layer having an opening that exposes a predetermined portion of a lower wiring formed on a surface of a substrate, and ionizing a barrier metal layer made of tungsten having a predetermined thickness on an inner surface of the opening. Forming a plug by physical vapor deposition using a metal plasma; depositing a tungsten layer by chemical vapor deposition on the barrier metal layer to fill the opening; and forming a plug on the insulating layer so as to contact the plug. Forming a wiring.

Description

Method of forming interconnections in semiconductor devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a wiring connection part of a semiconductor device. In particular, a barrier layer of a contact plug electrically connected to an upper electrode or a bit line of a capacitor is plated by an ionized metal plasma method. After depositing and forming the first tungsten layer having the type grains, the second tungsten layer is deposited by chemical vapor deposition to form a contact plug, thereby preventing volkeno phenomenon and forming a uniform second tungsten layer to form foreign matter such as bumps. The present invention relates to a method of forming a barrier layer for contact plugs in a semiconductor device which prevents formation and forms a second tungsten layer at a high pressure, thereby shortening a deposition time and improving process efficiency.

In the manufacturing process of a semiconductor device, a plug is formed of a conductor such as metal to connect an active region or a lower wiring and an upper wiring of a substrate for electrical connection between devices. The plug is formed by forming a contact hole or via hole exposing a predetermined portion of an active region or a lower wiring in a predetermined portion of the insulating layer, and then filling it with a conductive material such as tungsten. That is, a first barrier metal layer is formed on an insulating layer including a contact hole or a via hole inner surface, and a metal layer having a thickness sufficiently filling the inside of the hole is formed on the first barrier metal layer, and then the metal layer fills only the holes. An etch back process using the first barrier metal layer as an etch stop layer is performed to form a plug made of the remaining metal layer.

However, in the process of forming a contact / via of 0.5 μm or less, tungsten residues generated during the formation of tungsten plugs remain on the insulating layer and cause a short circuit between these wirings when a connection wiring is formed of a metal such as aluminum. .

Specifically, in the tungsten plug forming process, a first barrier metal layer is formed in the contact hole or the via hole to improve the mutual adhesion of the wiring connection portion, the tungsten layer is deposited thereon, and the tungsten layer is etched back. To remove the tungsten except for the hole.

Thereafter, the lower barrier metal layer, the main wiring layer, and the upper barrier metal layer are sequentially deposited and then patterned to form a connection wiring.

1A to 1B are cross-sectional views illustrating a wiring forming method including a plug of a semiconductor device according to the prior art.

Referring to FIG. 1A, an insulating layer 11 is formed of an oxide film such as spin-on glass (SOG) on a silicon substrate 10, which is a semiconductor substrate. In this case, elements such as a transistor including an impurity diffusion region may be formed on the silicon substrate 10.

Then, a metal layer such as aluminum is deposited on the insulating layer 11 by sputtering, and then patterned by photolithography to form the lower wiring 12. In this case, the lower wiring 12 may be an upper electrode of a bit line or a capacitor.

Then, an intermetal dielectric layer 13 covering the lower wiring 12 is formed on the insulating layer 11.

Then, a predetermined portion of the interlayer insulating layer 13 is removed by photolithography to form a via hole exposing a part surface of the lower wiring 12.

Next, Ti and TiN are sequentially deposited on the interlayer insulating layer 13 including the via hole to form the first barrier layer 14 and the second barrier layer 15 to a predetermined thickness. In this case, the second barrier layer 15 may be formed by chemical vapor deposition or an ionized metal plasma method.

The tungsten layer 16 is deposited by chemical vapor deposition to completely fill the via holes. In this case, the tungsten layer 16 may improve the step coverage of the tungsten layer 16 by increasing the partial pressure of WF ₆ at a high pressure.

However, when the aspect ratio of the via hole is 10 or more, the WF6 gas penetrates into the first barrier layer 14, which is the underlying layer, through the boundary of the second barrier layer 15 made of TiN, and reacts with Ti to cause volcano. This results in lowering the reliability of the device.

In addition, since the grain of TiN, which is the second barrier layer 15, has a columnar structure, nonuniform nucleation occurs at the deposition site of tungsten deposited by chemical vapor deposition, and foreign matters such as bumps or spots are bundled. .

Referring to FIG. 1B, the top surface of the interlayer insulating layer 13 is exposed by performing etch back on the tungsten layer, the second barrier layer, and the first barrier layer. At this time, the etch back is carried out so that the surface of the interlayer insulating layer 13 is exposed by reactive ion etching (hereinafter referred to as RIE) using a gas such as SiF ₆ or Cl ₂ as an etchant.

Accordingly, the tungsten plug 160 including the remaining tungsten layer 160 interposed between the first barrier layer 140 and the second barrier layer 150 interposed between the interlayer insulating layer 13 as a result of the etch back. To form.

Next, the plug 160 and the main wiring to be formed later on the exposed top surface of the first barrier layer 140, the second barrier layer 150, and the plug 160 and the exposed interlayer insulating layer 13. In order to increase the adhesion with the material, it is formed by depositing Ti into the lower arc layer 17 by sputtering.

After sputtering, an aluminum layer 18 to be used as the main wiring material is formed on the lower arc layer 17, and then the upper arc layers 19 and 20 are sputtered on Ti / It is formed by depositing TiN.

Next, the upper arc layers 20, 19 / aluminum layer 18 / lower arc layer 17 are formed by photolithography using anisotropic etching such as a wiring resist photoresist pattern (not shown) and dry etching. The upper wiring layer consisting of the remaining upper arc layers 20 and 19 / aluminum layer 18 / lower arc layer 17 by patterning is completed.

Therefore, when the wiring forming method including the plug of the semiconductor device according to the related art described above is employed, in the fifth generation or more of the 64M DRAM, the aspect ratio becomes 10 or more in the contact structure between the metal wiring and the bit line, so that the via hole is filled. In order to increase the step coverage by increasing the partial pressure of WF ₆ at high pressure under the CVD tungsten layer deposition condition, WF6 penetrates through the grain boundary of the TiN film, which is a barrier metal, and reacts with Ti, which is the underlying layer, to cause a volcano phenomenon. Tungsten deposition at high pressure becomes difficult.

Therefore, it is difficult to solve the poor step coverage of the tungsten layer, which is a via hole filling material, and the yield decreases.

In addition, since the crystal structure of TiN, which is a barrier layer, is a column structure, non-uniform nucleation occurs at a specific site when the CVD tungsten layer is formed, and thus foreign substances such as bumps or spots are generated.

Accordingly, an object of the present invention is to provide a first tungsten layer having a plate-type grain in an ionized metal plasma method, which is a physical vapor deposition method, of a barrier layer of a contact plug electrically connected to an upper electrode or a bit line of a capacitor. After the deposition, the second tungsten layer is deposited by chemical vapor deposition to form a contact plug, thereby preventing volkeno phenomenon and forming a uniform second tungsten layer to prevent foreign matter generation such as bumps. The present invention provides a method for forming a barrier layer for contact plugs in a semiconductor device, which is formed at high pressure, thereby shortening deposition time and improving process efficiency.

According to an aspect of the present invention, there is provided a method for forming a wiring connection part of a semiconductor device, the method including: forming an insulating layer having an opening that exposes a predetermined portion of a lower wiring formed on a surface of a substrate; Forming a barrier metal layer formed by physical vapor deposition using an ionized metal plasma, depositing a tungsten layer by chemical vapor deposition on the barrier metal layer to fill the opening, and forming a plug; And forming an upper wiring on the insulating layer.

1A to 1B are process cross-sectional views showing a wiring forming method including a plug of a semiconductor device according to the prior art;

2A to 2B are cross-sectional views illustrating a method of forming a wiring connection part of a semiconductor device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of forming a contact plug made of tungsten between an upper electrode and a lower line of an upper electrode or a bit line of a capacitor of a dynamic random access memory (DRAM) used as a semiconductor memory device. The barrier layer is formed of tungsten (or Ti / W) ionized metal plasma instead of conventional ionized metal plasma (Ti / TiN).

According to the present invention, the barrier layer is formed of an ionized metal plasma, thereby preventing volcano phenomena caused by the reaction of tungsten and oxide film generated during CVD tungsten deposition, securing excellent step coverage of the tungsten layer, and generating a blanket, etc. Can be prevented.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2B are cross-sectional views illustrating a method of forming a wire connection part of a semiconductor device according to the present invention.

Referring to FIG. 2A, an insulating layer 31 is formed of an oxide film on a silicon substrate 30, which is a semiconductor substrate. In this case, devices such as a transistor including an impurity diffusion region may be formed on the silicon substrate 30.

A metal layer such as aluminum is deposited on the insulating layer 31 by sputtering, and then patterned by photolithography to form the lower wiring 32. In this case, the lower wiring 32 may be an upper electrode of a bit line or a capacitor.

Then, an intermetal dielectric layer 33 covering the lower wiring 32 is formed on the insulating layer 31.

Then, a predetermined portion of the interlayer insulating layer 33 is removed by photolithography using anisotropic etching, such as dry food, to form a via hole exposing a part surface of the lower wiring 32.

Next, a barrier layer 34 is formed on the interlayer insulating layer 33 including the via hole so as to cover the exposed surface of the lower wiring 32. In this case, the barrier layer 34 is formed by depositing a tungsten layer or a Ti / W layer to a predetermined thickness by an advanced physical vapor deposition method using an ionized metal plasma. At this time, the deposition thickness of the barrier layer 34 is 500 kPa or less. Therefore, since the barrier property against WF ₆ of the barrier layer 34 formed by the ionization metal plasma method is superior to that of conventional TiN, volcano phenomenon is prevented.

In addition, the tungsten layer 34 formed by the ionized metal plasma method acts as an excellent adhesive layer when forming the tungsten layer for plug formation by chemical vapor deposition, thereby ensuring an excellent step coverage in the via hole.

In addition, since the grains of the tungsten layer 34 formed on the interlayer insulating layer 33 made of an oxide film have a plate-like structure rather than a columnar structure (in the case of Ti / W, the grains of W are Ti-like structures). The tungsten layer for plugs formed on the 34 is formed to have a uniform morphology.

The tungsten layer 35 is deposited by chemical vapor deposition so as to completely fill the via hole on the barrier layer 34. In this case, the plug forming tungsten layer 35 may improve the step coverage of the tungsten layer 16 by increasing the partial pressure of WF ₆ at a high pressure.

That is, even if the partial pressure increases, penetration of the WF ₆ into the underlayer is prevented by the barrier layer 34 covering the surface of the via hole.

Referring to FIG. 2B, the top surface of the interlayer insulating layer 33 is exposed by performing etch back on the plug tungsten layer and the barrier layer. At this time, the etch back is carried out so that the surface of the interlayer insulating layer 33 is exposed by a reactive ion etching (hereinafter referred to as RIE) method using a gas such as SiF ₆ , Cl ₂ as an etchant.

Accordingly, as a result of the etch back, a tungsten plug 350 including a residual tungsten layer 350 interposed between the barrier layer 340 between the interlayer insulating layer 33 is formed.

And, the lower arc to increase the adhesion between the plug 350 and the main wiring material to be formed later on the exposed top surface of the barrier layer 340 and plug 350 and the exposed interlayer insulating layer 33. The layer 36 is formed by depositing Ti by sputtering.

The sputtered aluminum layer 37 to be used as the main wiring material is formed on the lower arc layer 36 by sputtering, and the upper arc layers 38 and 39 on the aluminum layer 37 are also sputtered by Ti /. It is formed by depositing TiN.

Then, the upper arc layers 38 and 39 / aluminum layer 37 / lower arc layer 36 are formed by photolithography using anisotropic etching such as a wiring resist photoresist pattern (not shown) and dry etching. The upper wiring layer consisting of the remaining upper arc layers 39 and 38 / aluminum layer 37 / lower arc layer 36 is patterned in order.

Therefore, in the method for forming the wiring connection part of the semiconductor device according to the present invention, after forming the barrier layer of the contact plug by depositing a first tungsten layer having a plate-type grain by ionized metal plasma, which is a physical vapor deposition method, By depositing the second tungsten layer by chemical vapor deposition to form a contact plug, it is possible to prevent volkeno phenomenon, to form a uniform second tungsten layer, to prevent foreign substances such as bumps, and to form the second tungsten layer at high pressure. There is an advantage of improving the process efficiency by reducing the time.

Claims (5)

Forming an insulating layer having an opening that exposes a predetermined portion of the lower interconnection formed on the substrate surface; Forming a barrier metal layer made of tungsten having a predetermined thickness on the inner surface of the opening by physical vapor deposition using an ionized metal plasma; Depositing a tungsten layer by chemical vapor deposition on the barrier metal layer to fill the opening, and forming a plug; And forming an upper wiring on the insulating layer so as to contact the plug. The method according to claim 1, And wherein the barrier layer has a thickness of 500 mW or less. The method according to claim 1, And wherein the barrier layer is formed through titanium. The method according to claim 1, And the upper wiring is formed of Ti / Al / Ti / TiN. The method according to claim 1, And the lower wiring is an upper electrode or a bit line of a capacitor.