KR20010075083A - Method and apparatus for accessing a complex vector located in a dsp memory - Google Patents

Abstract

Methods and apparatus for efficiently accessing the real and imaginary parts of complex vector components in digital signal processor memory are realized through the combination of new processor addressing and fixed displacement modes. Additional registers, fixed displacement registers, and additional control flags, fixed displacement configuration bits are required. The usage requires only a single address register and does not require the use of a general purpose offset register used for index addressing, but allows the offset register to be used for simultaneous post-correction and / or bit inversion. Dual memory spaces that share a common address space are not required, which simplifies memory management, and the method and apparatus are compatible with all addressing.

Description

METHOD AND APPARATUS FOR ACCESSING A COMPLEX VECTOR LOCATED IN A DSP MEMORY}

1 shows an address generation unit (AGU) 102 which is a typical prior art for a processor such as a digital signal processor. The term “processor” herein refers to any data processing device, but is not limited to digital signal processors. In general, AGU 102 contains a set of registers for memory data access. Typically each register set 110 includes three registers:

1. an address register (pointer) 104, denoted by Rn;

2. Offset register 106, denoted by Nn;

3. Buffer Length Register 108, denoted by Mn

Where n = 1 ... K is the set index and K is the number of sets present in the processor address generation unit.

The term "array" herein refers to any of a plurality of locations in the processor memory so that every individual location can be accessed for an index relative to a fixed base address, where the index is all multiples of a constant. The term "vector" herein refers to any plurality of data values stored in such an array, and the term "component" refers to any data value of such a vector. The term "complex number" herein means any pair of data represented by "Part 1" and "Part 2" including, but not limited to, a pair of numbers consisting of "real part" and "imaginary part" in a general mathematical sense. The term “complex vector” herein refers to any pair of vectors having the same number of components The term “first array” herein refers to the first portion (or vector) of a vector pair of complex vectors. Refers to an array in the containing processor memory, and the term “second array” refers to an array in the processor memory containing the second portion (or vector) of a vector pair of complex vectors, the complex vector being a complex number in a general mathematical sense. Real numbers of complex vectors are stored in a first array and imaginary numbers of complex vectors are stored in a second array. It may consist of a vector of complex numbers, where the real number of the complex vector is stored in the second array and the imaginary number of the complex vector is stored in the first array In another variant, the complex vector according to the present invention inevitably represents a complex number in a general mathematical sense. It may consist of two vectors of arbitrary data values that are not represented, and " access " in processor memory indicates address generation in processor memory, and not only retrieves stored data values from processor memory, Storage of data values.

When working with complex vectors, the first and second arrays are typically placed at different addresses in memory or in different memory spaces, depending on the processor memory architecture. Two different address registers are required to access the complex vector in indirect addressing, namely the address register for the first array and the address register for the second array. The limitation of this approach is that the address register is a very expensive resource in digital signal processor applications. If the first array and the second array are placed in the same memory, a single address register and offset register can be used for access. This method can be used where the address register itself points to the first array and the offset register contains the offset between the first array and the second array. In this case, the first array is accessed by indirect addressing using an address register (Rn) and by indexed indirect addressing using an address register and an offset register (ie, Rn + Nn). It is possible to access the second array. However, in bit-reversal and post-modification-by-step addressing, an offset register is used but cannot be used for index indirect addressing. Thus, when using index indirect hydrogen specification, two address registers are required for complex vector access. This situation arises from the FFT algorithm using bit inversion addressing, the demultiplexing of complex signals using sequential post-correction addressing, and so on. (A review of the field and description of existing digital signal processor architectures can be found in Buyer's Guide to DSP Processors , Berkeley Design Technology Inc., 1995).

Most of the existing digital signal processors do not solve this memory access problem, so when the offset register is used, two different address registers are usually required to access the complex vector. One existing solution for the Motorola DSP56xxx processor series is shown in FIG. This method uses two data memories, namely X memory 202 and Y memory 204, having the same address space 206. Also required are dedicated assembly language syntax (not shown in FIG. 2) and an address generation unit (shown in FIG. 1). A complete description of this architecture is given in the DSP56000 24-Bit Digital Signal Processor Family Manual , Motorola, Inc. (DSP Division, Austin City, Texas), for all purposes as fully described herein. Is reflected. In this prior art solution, the address generation architecture is such that the address register 208 (R0) points to the same address of the X memory 202 and the Y memory 204. Thus, by placing the first and second arrays for complex vectors at the same address in different memory spaces, the use of address registers 208 (R0) is enabled to access both the first and second arrays simultaneously. As shown in FIG. 2, address register 208 (R0) points to address 0x0002 but has no specific relationship to memory space. Direction to a particular memory space is implemented by assembly language opcode. For example, if the first array is placed in X memory 202 and the second array is placed in Y memory 204, and the first array stores the real part of the complex vector and the second array is the imaginary part of the complex vector. When storing, moving the real part of address (0x0002) to register A and the imaginary part to register B are performed by the following assembly code:

move X: (R0), A;

move Y: (R0), B;

This solution has two drawbacks: First, two parts of the vector (indicating the first array and the second array respectively) must be located at the same address but with different memories. This can lead to inefficient memory usage (holes in the memory) and make it difficult to implement memory relocation if necessary. For example, if it is necessary to relocate the first array in X memory 202, it is also necessary to relocate the second array in Y memory 204 to maintain two arrays at the same address.

Thus, there is a widespread need for an efficient way to access complex vectors in processor memory that requires only a single address register, does not require the use of offset registers, and does not require the use of multiple memories that share a single address space. It is recognized and it is also very advantageous to have this method. This goal is met by the present invention.

The present invention relates to a processor memory addressing method and a memory address generation method, and more particularly, to a method of accessing a complex vector stored in a digital signal processor (DSP).

The invention is explained by way of example with reference to the accompanying drawings.

1 illustrates an address generation unit for a prior art digital signal processor.

2 is a diagram showing a memory configuration of a digital processor of the prior art.

3 shows a new feature of an address generation unit for a digital signal processor according to the invention;

4 is a flowchart of the algorithm for fixed displacement address generation.

5 shows an example of a memory state.

6 illustrates a two data memory space architecture.

Summary of the Invention

The present invention relates to a method and apparatus for accessing a complex vector placed in processor memory and generating a valid memory address using a single address register (pointer) at any addressing. This is done by incorporating a new register into the address generating unit, which is referred to as a "fixed displacement register" and denoted by Rf. This fixed displacement register is used only for index indirect addressing and provides a memory offset at this addressing. This method allows access to two different arrays and sequential post-increment with the same address register without reprogramming the address generation unit.

Thus, the present invention successfully addresses the shortcomings of the presently known configurations and methods. Firstly, the present invention makes it possible to access a complex vector with one addressing unit register set using any kind of addressing. Secondly, the present invention places no restrictions on the real and imaginary memory allocations, memory spaces, and addresses of complex vectors (e.g., the first array and the second array).

Thus, according to the present invention, an address generating unit for calculating an address for memory access to a complex vector by a processor, comprising: (a) an address register; (b) an offset register; (c) means for implementing the index indirect addressing capability; (d) fixed displacement resistors; (e) means for entering a fixed displacement mode having a selectable state from the group consisting of an enabled state and a disabled state; And (f) a fixed displacement configuration bit indicative of the state of the fixed displacement mode.

Furthermore, in accordance with the present invention, a method of implementing a fixed displacement mode in a processor having an address register, a fixed displacement register, and a fixed displacement configuration bit, the processor having a type of addressing including index indirect addressing, and a current instruction (A) loading the base address into the address register and the fixed displacement into the fixed displacement register; (b) checking the current instruction for index indirect addressing; (c) checking the fixed displacement configuration bit; And (d) generating a memory address equal to the sum of the base address and the fixed displacement only if the current instruction includes index indirect addressing and the fixed displacement bit is set. .

The principle and operation of the method and apparatus according to the present invention can be understood with reference to the accompanying drawings and the description. An important embodiment of the address generation unit of the device according to the invention is shown in FIG. 3. The steps of the method of the present invention executed in operation of a digital signal processor or other processor according to the present invention are shown in the flowchart of FIG. These steps implement a fixed displacement mode, a new processor mode according to the present invention.

As shown in FIG. 3, it is essential to first provide some additional hardware capability. In particular, the processor should have a fixed displacement register 310, denoted Rf1, in the address generation unit 302. The fixed displacement register 310 must be software-programmable like all other registers of the address generation unit 302. It is also possible, but not necessary, to use one or more fixed displacement registers, where additional multiple fixed displacement registers 312, 314, 316 are represented by Rf2, Rf3, ..., Rru as shown by the dashed outline. Ellipses (...) indicate that additional displacement registers may be incorporated. Register set 322 includes Rn, Nn, Mn, and Rf1. The present invention requires the processor to have index indirect addressing capabilities, which can be implemented through any means well known. It is noted that the fixed displacement register 310 is distinguished from the offset register 306. The fixed displacement register 310 and the offset register 306 perform different functions and are used independently of each other.

It is also essential that the processor have a new mode, referred to herein as a "fixed displacement mode". The fixed displacement mode has two states, the enabled state and the disabled state, which can be controlled by incorporating the fixed displacement configuration bit 320 into the control register 318. The fixed displacement configuration bit may be used as a control flag. The operation of the fixed displacement mode is described in the method according to the invention as detailed below. Control register 318 may be an existing control register in an existing processor design being modified, or may be a new control register. It is also essential that the processor be provided with the hardware necessary to implement the steps of the fixed displacement mode (below) during execution. The hardware facility for performing the following steps can be implemented through a variety of well known techniques.

The steps of a method executed by a processor to implement a fixed displacement mode for memory address generation in accordance with the present invention are as follows and are shown in FIG.

1. In the loading step 402, the register set 322 (FIG. 3) is loaded into the address generating unit 302 (FIG. 3). This step loads the base address into the address register 304, the address offset into the offset register 306, the buffer length into the buffer length register 308, and the fixed displacement into the fixed displacement register 310.

2. Check to see if the current instruction uses index indirect addressing at decision point 404.

3. If index indirect addressing is not in use, then address generation step 408, as is well known, generates the address in a conventional manner.

4. However, if index indirect addressing is used, check to see if fixed displacement configuration bit 320 (FIG. 3) is set at decision point 406.

5. If the fixed displacement configuration bit 320 is not set, the fixed displacement mode is in the disabled state, and the address generating unit 302 operates in a conventional manner in the memory address generating step 410. That is, the new features described herein do not operate and access to the address Rn + Nn is made without changing the value of the Rn register 304 (FIG. 3). When the fixed displacement configuration bit 320 is cleared, the offset register Nn 306 (FIG. 3) is the source for all post modification and indirect indexing.

6. However, if the fixed displacement configuration bit 320 is set, the fixed displacement mode is enabled, and the offset source for all index indirect addressable memory address generation is generated by the offset register Nn (memory address generation step 412). In place of 306 is a fixed displacement register 310 (Rfn). The generated address is the sum of the contents of the fixed displacement register 310 and the contents of the address register 304. Access to the address Rn + Rfn is accomplished without changing the value of the Rn register 304 (FIG. 3).

The memory address generation method according to the present invention ends at return step 414.

The fixed displacement configuration bit may be used as a control flag at the point where the fixed displacement configuration bit sets the fixed displacement mode to the enabled state and the erase displacement configuration bit to the disabled state. However, fixed displacement mode is only active if the current instruction uses index indirect addressing. If the current instruction uses an address other than index indirect addressing, the fixed displacement mode will not be active even if it is in the enabled state. As is well known, there are other addressing capabilities other than index indirect addressing, including but not limited to direct addressing and post-modification addressing. It is possible to include any addressing of various types within a command. The term "non-indexed indirect addressing" herein refers to any such addressing that does not involve indexed indirect addressing.

It is noted that the assembly syntax may support fixed displacement register 310 (Rf1) in the memory address generation instruction but need not be. The term "assembly syntax" herein refers to assembly language divisions as well as the resulting machine instruction constructs. If the assembly syntax supports fixed displacement registers, the assembly syntax activates the fixed displacement as a modifier for the individual instructions rather than as a processor mode with enable and disable states. If the assembly syntax does not support fixed displacement registers, it is sufficient to limit the instruction to only the offset register 306 (Nn), because it limits the addressing. The hardware automatically takes an offset register 306 or a fixed displacement register 310 for memory address generation depending on the state of the fixed displacement fixed displacement configuration bit 320. Calling different memory arrays “first array” versus “second array” is arbitrary and their contents are completely arbitrary.

It is readily seen that the method according to the invention allows the processor to efficiently access both parts of the complex vector. For example, assume that the address generation unit and the memory are in the following states.

R1 = 1000 (address register 304 in Figure 3)

N1 = 2 (offset register 306 in Figure 3)

M1 = programmed for linear addressing (buffer length register 308 in FIG. 3-actual programming depends on manufacturer)

Rf1 = 50 (fixed displacement register 310 in FIG. 3)

Then execute the following assembly (pseudo) code:

Move (R1) + N1, A;

Move (R1 + N1), B;

Where A and B are the general registers of the processor (not the registers of address generation unit 302). Note that (R1) + N1 is post-modification addressing, memory access is at location R1, and R1 is increased by Ni after memory access. It is also noted that (R1 + N1) is indirectly indexed addressing, that the memory access is not changed to location R1 + N1, and R1 does not change during and after the memory access.

5 illustrates two scenarios for two different values of fixed displacement configuration bit 320, the situation for memory region 502 with addressing 504. In FIG. 5 and the example below, all data values and address locations are shown in decimal. Both scenarios are in the following states:

The area in the memory from address positions 1000 to 1049 is designated as the first array 508, and the area in the memory from address position 1050 is designated as the second array 518.

Prior to execution, there is an initial value 506 for the address register R1, such as 1000. In other words, R1 initially points to location 512 in memory with address 1000 containing data value -348.

After the first instruction ends, register A contains the data value -348 and the address register R1 is equal to 1002. That is, R1 points to location 514 in memory with address 1002 containing data value 4391.

When execution is complete, there is a final value 510 for address register R1, such as 1002. This is because the second command contains only index addressing, and index addressing does not change the value of the address register.

The content of register B after the second command is made depends on the fixed displacement mode. Below, two cases of setting and erasing the fixed displacement mode are described:

Fixed displacement configuration bit is not set

In this scenario, the fixed displacement configuration bit is cleared (not set). As a result, the fixed displacement mode is in a disabled state. Memory address generation is done in a conventional manner, and after the second instruction is executed, register B includes the value 4391 from memory location 514 in the first array 518.

Fixed displacement configuration bit is set

In this scenario, the fixed displacement configuration bit is set. As a result, the fixed displacement mode is in an active state. Since the first instruction does not use index indirect addressing, the memory address generation for the first instruction is done in a conventional manner. However, the second instruction uses index indirect addressing, and because the fixed displacement configuration bit is set (thus making the fixed displacement mode active), memory address generation is performed at memory location 516 containing the value -819. Offset memory search to Rf1 for access. Therefore, in this scenario, after the second command is issued, register B includes the data value -819 from memory location 516 in the second array 520.

Therefore, it is possible to efficiently access both the real part and the imaginary part of the complex vector. For example, if the real part is stored in the second array 520 and the imaginary part is stored in the first array 518, after initially setting the fixed displacement configuration bit and executing the two above instructions, Register A contains an imaginary part, which is one of the components of the complex vector, and register B contains the real part of the complex vector.

In this embodiment, the method according to the invention has been provided under the context of a simple memory architecture, namely a single memory space architecture. Today, advanced DSP algorithms require more complex memory architectures and thus current digital signal processors have a dual memory space architecture. Figure 6 illustrates an example of the method according to the invention for a complex vector where the first and second arrays are located in different memory spaces. Addresses 606 correspond to the contents 608 of the data value. In Figure 6 and the example below, all address locations are shown in octal.

In order to apply the method according to the invention to a dual memory space architecture, the memory arrangement must be contiguous. There is a memory space 602 marked as "X memory address space" for the first array 610 starting at position 0x0000 and a memory space marked as "Y memory address space" for the second array 612 starting at position 0x8000. There is 604. As required, these addresses are contiguous as shown in FIG. In this example, the most significant bit (MSB) of the address identifies which memory space is in use.

In this configuration, the base address of the real part of the complex vector may be located, for example, at address 0x0002 in the X space 602 and the base address of the imaginary part may be located at the address 0x8008 in the Y space 604. In order to operate in the fixed displacement mode, it is necessary to set the fixed displacement register Rf to 0x8006 (0x8008-0x0002) and set the fixed displacement configuration bit 320 in the control register 318 (FIG. 3).

Although the present invention has been described with respect to a limited number of embodiments, it will be understood that many variations, modifications and other applications of the invention may be made.

Claims (8)

An address generating unit for calculating an address for memory access to a complex vector by a processor, the address generating unit comprising: (a) an address register; (b) means for implementing the index indirect addressing capability; (c) means for entering a fixed displacement mode having a selectable state from the group consisting of an enable state and a disable state; And (d) a fixed displacement configuration bit indicating the state of the fixed displacement mode Address generation unit comprising a. The method of claim 1, And an offset register, wherein said fixed displacement register is distinct from said offset register. An address generation unit for computing an address for memory access to a complex vector by a processor having an assembly syntax that includes a fixed displacement modifier, (a) an address register; (b) means for implementing the index indirect addressing capability; (c) fixed displacement resistors; (d) means for performing a fixed displacement; (e) means for detecting a fixed displacement modifier; And (f) means for activating said fixed displacement upon detection of said fixed displacement modifier Address generation unit comprising a. The method of claim 3, wherein And an offset register, wherein said fixed displacement register is distinct from said offset register. An improved device for an address generating unit that calculates an address for memory accessing a complex vector by a processor, The address generating unit includes an address register and an offset register, (a) means for implementing a fixed displacement mode having a selectable state from the group consisting of an enable state and a disable state; (b) a fixed displacement register, distinct from an offset register, containing an offset to an address register when the fixed displacement mode is implemented; And (c) a fixed displacement configuration bit indicating the state of the fixed displacement register mode Improved device of the address generation unit comprising a. A method of implementing a fixed displacement mode in a processor having an address register, a fixed displacement register, and a fixed displacement configuration bit, The processor has instructions that can use index indirect addressing, executes the current instructions, (a) loading the base address into the address register and the fixed displacement into the fixed displacement register; (b) checking the current instruction for index indirect addressing; (c) checking the fixed displacement configuration bit; And (d) generating a memory address equal to the sum of the base address and the fixed displacement only if the current instruction uses index indirect addressing and the fixed displacement bit is set. Fixed displacement mode implementation method comprising a. A method of accessing a component of a complex vector by a processor having a fixed displacement mode and an address register with a fixed displacement register, the method comprising: The component has a first part containing a base address and a second part offset from the base address by a fixed displacement, wherein the fixed displacement mode has a selectable state from a group consisting of an enable state and a disable state, and for a processor The instruction has a selectable addressing from the group consisting of index indirect addressing and non-index indirect addressing, (a) loading the base address into an address register; (b) loading the fixed displacement into the fixed displacement register; (c) selecting an enable state for the fixed displacement mode; (d) accessing a first portion containing instructions having non-indexed indirect addressing; And (e) accessing part 2 containing instructions with index indirect addressing A method of accessing a component of a complex vector comprising a. The method of claim 7, wherein The processor further has a configurable fixed displacement configuration bit and index indirect addressing, and selecting an enabled state for the fixed displacement mode. i) setting a fixed displacement configuration bit; And ii) using index indirect addressing A method of accessing a component of a complex vector comprising a.