KR20010064322A - Method for generating automated column address in SDRAM - Google Patents

Abstract

PURPOSE: A method for generating an auto column address of an SDRAM is provided to simplify the interface between a chip set and a memory by selecting a column address using a row address signal without generating a column address selecting signal when a data access of a memory cell is performed. CONSTITUTION: In the method, a row address signal outputted from a row address generator enabled in response to a /CS(Chip Selection) and a /RAS(Row Address Strobe) inputted by a column address generating circuit. The inputted row address signal is used as a column address signal of the same address as the inputted row address signal. The row address generator is enabled in response to a DQM signal when the row address signal is used as the column address signal of the same address as the row address signal.

Description

Method for generating automated column address in SDRAM

The present invention relates to a synchronous dynamic random access memory (SDRAM), and more particularly, to an automatic column address generation method of an SDRAM in which a column address can be selected only by a row address signal when row addresses and column addresses of the same address are selected. .

In memory devices used to temporarily or permanently store data and instructions in computers, communication systems, image processing systems, and the like, DRAM (Dynamic Random Access Memory) has recently been synchronized with a clock as much as possible to improve speed. SDRAM is designed to lock the DRAM speed to an integer multiple of the clock, eliminating the time required for clock synchronization by the DRAM controller and adding time to interleaving control.

The features of this SDRAM include: 1) input / output circuits synchronized with an external clock, 2) burst access (high speed of continuous data access), 3) multi-bank configuration, 4) instruction type access (mode register programming), 5) Pipeline data paths.

// RAS is "low level" is in the memory is activated and the time corresponding to t _RCD in the SDRAM to as the time until the input of the row address becomes done / CAS command is dropped t _RCD clock cycle in a typical DRAM It is given as an integer multiple of time, and the time until valid data is output after a read command is called CAS latency (hereinafter referred to as CL), which is also given as an integer multiple of the clock cycle time.

1 is a waveform diagram illustrating an operation process of a conventional SDRAM.

As shown in FIG. 1, when the _RCD = 3 and CL = 3 and the burst length BL is 4 by four consecutive data, the operation of the SRDAM is as follows. When the active command ACT and the row address data ROW of the DRAM are input at the rising edge of the C ₁ clock and the memory is set to an active state, the word line is selected by the row address. If the read command (READ) is input from the C ₄ clock after 3 clocks, the column address data (CAS) is also input, so all the addresses for the first data of the burst read are input. Since the clock C is continuously output (B1, B2, B3, B4 ) the data while increasing the column address by one every clock from _7. In DRAM, precharge operation starts when // RAS transitions to a "high level", but in SDRAM, a precharge command PRE is input at clock C ₉ to change the current state to a precharge state. Of course, in the case of the automatic precharge command, after the data of the burst length determined according to the read / write command is automatically read, the precharge state is automatically entered, and thus no additional precharge command is required.

FIG. 2 is a diagram illustrating a method of selecting a column address after activating a row address of a conventional SDRAM. In the conventional SDRAM, a chip set selects a row address in order to access data of a specific memory cell. (1), the word line of the memory cell, for example, Row0 is enabled, and then the column address of the cell is selected (2) to read the cell data.

As described above, when the chip set is the same row and column address, for example, each address has to be generated, which is a burden on the interface.

It is an object of the present invention to select a column address using a row address signal without generating a column address selection signal when accessing data of a memory cell having the same row address and column address, thereby simplifying an interface between the chip set and the memory. An automatic column address generation method of an SDRAM is provided.

1 is a waveform diagram illustrating the operation of a conventional SDRAM;

2 is a view for explaining a method of selecting a column address after activating a row address of a conventional SDRAM;

3 is a waveform diagram illustrating an automatic column address generation method of an SDRAM according to the present invention;

In order to achieve the above object, the present invention provides a method for generating an address of an SDRAM, wherein the column address generation circuit inputs a row address signal output from a row address generator enabled in response to / CS and / RAS. Is used as the column address signal of the same address.

In the automatic column address generation method of the SDRAM of the present invention, it is preferable that the row address is enabled in response to the DQM signal when the row address is used as the column address signal of the same address.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, this embodiment is not intended to limit the scope of the present invention, but is presented by way of example only.

3 is a waveform diagram illustrating an automatic column address generation method of an SDRAM according to the present invention.

The automatic column address generation method of the SDRAM according to the present invention receives a row address signal from a row address generator enabled in response to / CS and / RAS so that the row address signal is stored at the same address without using an external column address generation circuit. It is used as a column address signal.

As shown in FIG. 3, in the SDRAM of the present invention, the memory is enabled at a low level with / CS (chip select) and / RAS (row address strobe) in synchronization with the falling edge of the clock signal CLK. The address strobe (WEB) signal and the WE (write enable) signal become high level and are enabled when the input mask & output enable (DQM) is high level.

Accordingly, the SDRAM of the present invention receives the row address input from the chip set and activates the row address, and then, by using the DQM signal, selects the column address having the same address as the row address signal without using an external column address generation circuit. To store the row address signal input at / RAS activation in SDRAM.

Then, after t _RCD where the row address input is terminated, one column address is automatically selected using the automatically stored column address without the column address command of the chip set to access the data of the memory cell. At this time, RAC_CAE represents a row active command and an automatic column address enable command.

For example, the SDRAM of the present invention selects the row address 000 and the column address 000 of the same address without additional column address command when the row address is input as "000". When the row address is input as "010", the row address 010 and the column address 010 of the same address are selected without additional column address commands.

On the other hand, in the SDRAM of the present invention, when the CS and // RAS are low level and the memory is enabled in synchronization with the falling edge of the clock signal CLK, the CAS and WE signals are high level and the DQM signal is low level. If changed to, the normal operation is performed as in the prior art. That is, as shown in FIG. 1, when the read or write command is input after the word line is selected by the row address, the SDRAM executes data access of the memory by receiving column address data through the chip set. In the waveform diagram of FIG. 3, N_RAC represents a normal row active command.

As described above, the present invention automatically stores the row address signal without using the column address command of the chip set, selects the row address signal as the column address, and accesses data in the memory cell, thereby performing t _RCD cycles. In other words, the performance of the system can be improved.

Claims (2)

In the address generation method of the SDRAM, A column address generation circuit inputs a row address signal output from a row address generator enabled in response to / CS and / RAS and uses the input row address signal as a column address signal of the same address. How to generate column address. The method of claim 1, wherein the row address is enabled in response to a DQM signal when the row address is used as a column address signal of the same address.