KR20010061012A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR20010061012A KR20010061012A KR1019990063487A KR19990063487A KR20010061012A KR 20010061012 A KR20010061012 A KR 20010061012A KR 1019990063487 A KR1019990063487 A KR 1019990063487A KR 19990063487 A KR19990063487 A KR 19990063487A KR 20010061012 A KR20010061012 A KR 20010061012A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 37
- 238000002955 isolation Methods 0.000 claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 230000004888 barrier function Effects 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 11
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000007517 polishing process Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 abstract description 23
- 230000010354 integration Effects 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 고집적 반도체소자에서 트렌치를 이용한 소자분리공정시 반도체기판 상부에 소자분리영역으로 예정되는 부분을 노출시키는 패드산화막패턴과 질화막패턴의 적층구조를 형성하고, 상기 질화막패턴을 식각마스크로 상기 반도체기판을 식각하여 트렌치를 형성한 다음, 상기 트렌치 표면을 산화시킨 후 상기 질화막패턴을 제거하여 애스펙트비(aspect ratio)를 감소시킨 다음, 소정 두께의 다결정실리콘층을 증착하고 그 상부에 매립절연막을 증착하고, 상기 다결정실리콘층을 식각장벽으로 상기 매립절연막을 제거한 다음, 열처리공정을 실시하여 상기 다결정실리콘층을 산화시켜 애스펙트비가 높은 트렌치를 보이드없이 매립할 수 있으므로, 소자의 신뢰성 및 전기적 특성을 향상시키고, 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for manufacturing a semiconductor device, in which a stacked structure of a pad oxide film pattern and a nitride film pattern is formed on a semiconductor substrate to expose a predetermined portion as a device isolation region in a device isolation process using a trench in a highly integrated semiconductor device, The semiconductor substrate is etched using the nitride film pattern as an etch mask to form a trench, the oxide surface is oxidized, the nitride film pattern is removed to reduce an aspect ratio, and a polysilicon layer having a predetermined thickness is formed. After depositing and depositing a buried insulating film thereon, removing the buried insulating film with an etch barrier as the polysilicon layer, and then performing a heat treatment process to oxidize the polysilicon layer to fill a trench having a high aspect ratio without voids. Improve the reliability and electrical characteristics of the device, It is a technology that enables integration.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 고집적 반도체소자의 소자분리공정에서 애스펙트비가 높은 트렌치를 보이드없이 매립하는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a trench having a high aspect ratio is buried without voids in a device isolation process of a highly integrated semiconductor device.
고집적화라는 관점에서 소자의 집적도를 높이기 위해서는 각각의 소자 디멘젼(dimension)을 축소하는 것과, 소자간에 존재하는 분리영역의 폭과 면적을 축소하는 것이 필요하며, 이 축소정도가 셀의 크기를 좌우한다는 점에서 소자분리 기술이 메모리 셀 사이즈(memory cell size)를 결정하는 기술이라고 할 수 있다.In order to increase the integration of devices from the viewpoint of high integration, it is necessary to reduce each device dimension and to reduce the width and area of the separation region existing between devices, and the degree of reduction depends on the size of the cell. In this regard, device isolation technology may be used to determine memory cell size.
일반적으로 소자분리 기술에서 디자인 룰이 감소함에 따라 작은 버즈빅 길이와 큰 체적비를 요구하고 있다.In general, as the design rule decreases in device isolation technology, a small buzz length and a large volume ratio are required.
그러나, 종래의 로코스(LOCOS : LOCal Oxidation of Silicon, 이하에서 LOCOS 라 함) 공정방법은 소자분리막이 얇아지는 문제와 버즈빅현상으로 기가(Giga DRAM)급 소자에서는 적용하는데 한계가 있다.However, the conventional LOCOS (LOCOS: LOCOS) process method has a limitation in that it is applied to a giga DRAM device due to a problem of thinning an isolation layer and a buzz big phenomenon.
또한, 트렌치 소자분리 공정도 공정의 복잡성뿐만 아니라 디자인 룰이 감소할수록 애스펙트비(aspect ratio)가 높은 트렌치 영역을 매립하는 것이 어려워지므로 실제로 디자인 룰이 0.1 ㎛ 에 접근하면 트렌치 소자분리 공정도 적용하기가 어려워 질 것이다.In addition, the trench isolation process is difficult to fill the trench region with high aspect ratio as the design rule decreases as well as the complexity of the process. Therefore, when the design rule approaches 0.1 μm, it is difficult to apply the trench isolation process as well. Will be difficult.
이하, 첨부된 도면을 참고로 종래기술에 대하여 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described with respect to the prior art.
도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 제조방법을 도시한 단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
먼저, 반도체기판(11) 상부에 패드산화막과 질화막의 적층구조를 형성하고, 상기 질화막 상부에 소자분리영역으로 예정되는 부분을 노출시키는 감광막 패턴을 형성한다.First, a lamination structure of a pad oxide film and a nitride film is formed on the semiconductor substrate 11, and a photoresist pattern is formed on the nitride film to expose a portion intended as an isolation region.
다음, 상기 감광막 패턴을 식각마스크로 사용하여 상기 질화막과 패드산화막을 식각하여 질화막 패턴(15)과 패드산화막 패턴(13)을 형성하고, 상기 감광막 패턴을 제거한다.Next, the nitride layer and the pad oxide layer are etched using the photosensitive layer pattern as an etching mask to form the nitride layer pattern 15 and the pad oxide layer pattern 13, and the photosensitive layer pattern is removed.
그 다음, 상기 질화막 패턴(15)을 식각마스크로 사용하여 상기 반도체기판(11)을 식각하여 트렌치(16)를 형성한다.Next, the semiconductor substrate 11 is etched using the nitride film pattern 15 as an etching mask to form the trench 16.
다음, 상기 트렌치(16)의 표면을 열산화시켜 희생산화막을 성장시킨 후 습식식각을 실시하여 제거함으로써 상기 트렌치 형성공정시 발생된 상기 트렌치 표면의 결함을 제거한다.Next, the surface of the trench 16 is thermally oxidized to grow a sacrificial oxide film, followed by wet etching to remove defects on the trench surface generated during the trench formation process.
그 후, 다시 열산화공정을 실시하여 상기 트렌치(16)의 표면에 열산화막(17)을 형성한다.Thereafter, a thermal oxidation process is performed again to form a thermal oxide film 17 on the surface of the trench 16.
다음, 전체표면 상부에 상기 트렌치를 매립하는 CVD산화막(19)을 형성한다. (도 1b 참조)Next, a CVD oxide film 19 filling the trench is formed over the entire surface. (See FIG. 1B)
그 후, 도시되어 있지는 않지만 상기 질화막패턴(15)을 식각방지막으로 사용하여 상기 CVD산화막(19)을 화학적기계적연마(chemical mechanical polishing, 이하 CMP 라함)공정으로 제거하여 소자분리절연막을 형성한다.Thereafter, although not shown, the CVD oxide film 19 is removed by a chemical mechanical polishing (CMP) process using the nitride film pattern 15 as an etch stop film to form a device isolation insulating film.
다음, 소자분리영역과 반도체기판(11)과의 단차를 줄이기 위하여 상기 소자분리절연막을 습식식각방법으로 제거한다.Next, in order to reduce the step difference between the device isolation region and the semiconductor substrate 11, the device isolation insulating film is removed by a wet etching method.
그 후, 상기 질화막패턴(15)을 제거한다.Thereafter, the nitride film pattern 15 is removed.
상기와 같이 종래기술에 따른 반도체소자의 제조방법은, 반도체소자가 고집적화되어 감에 따라 디자인룰이 작아져서 소자분리영역이 협소해지는 반면에 깊이가 깊어져서 매립하기 어려워 도 1b 의 ⓧ부분과 같이 보이드가 발생하여 누설전류가 발생하는 등의 전기적 특성이 저하되는 문제점이 있다.As described above, in the method of manufacturing a semiconductor device according to the related art, as the semiconductor device becomes more integrated, the design rule becomes smaller and the device isolation region becomes narrower, while the depth becomes difficult to fill the void, as shown in FIG. There is a problem that the electrical characteristics such as the occurrence of a leakage current is reduced.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 트렌치를 형성하고, 소자분리마스크로 사용되는 질화막패턴을 제거한 다음, 전체표면 상부에 소정 두께의 다결정실리콘층을 형성하고, 그 상부에 매립절연막을 형성한 다음, 상기 다결정실리콘층을 식각장벽으로 상기 매립절연막을 CMP공정으로 제거한 후, 열처리공정을 실시하여 상기 다결정실리콘층을 산화시켜 상기 트렌치를 보이드의 발생없이 매립함으로써 소자의 전기적 특성 및 공정수율을 향상시키는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the trench is formed, the nitride film pattern used as the device isolation mask is removed, a polysilicon layer having a predetermined thickness is formed on the entire surface, and the buried insulating film is formed thereon. And then remove the buried insulating film by the CMP process with the polysilicon layer as an etch barrier, and then perform a heat treatment process to oxidize the polysilicon layer and bury the trench without generation of voids. It is an object of the present invention to provide a method for manufacturing a semiconductor device for improving the yield.
도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 제조방법을 도시한 단면도.1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 2a 내지 도 2d 는 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
11, 21 : 반도체기판 13, 23 : 패드산화막 패턴11, 21: semiconductor substrate 13, 23: pad oxide film pattern
15, 25 : 질화막 패턴 16, 26 : 트렌치15, 25: nitride film pattern 16, 26: trench
17, 27 : 제1열산화막 19, 31a : 매립절연막17, 27: first thermal oxide film 19, 31a: buried insulating film
29a : 다결정실리콘층 29b : 제2열산화막29a: polysilicon layer 29b: second thermal oxide film
31b : 소자분리절연막31b: device isolation insulating film
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은,Method for manufacturing a semiconductor device according to the present invention for achieving the above object,
소자분리영역으로 예정되는 부분의 반도체기판을 식각하여 트렌치를 형성하는 공정과,Forming a trench by etching a semiconductor substrate in a portion of the device isolation region;
상기 트렌치의 표면에 제1열산화막을 형성하는 공정과,Forming a first thermal oxide film on a surface of the trench;
전체표면 상부에 소정 두께의 도전층을 형성하는 공정과,Forming a conductive layer having a predetermined thickness on the entire surface;
상기 도전층 상부에 매립절연막을 형성하는 공정과,Forming a buried insulating film on the conductive layer;
상기 매립절연막을 화학적 기계적 연마공정으로 제거하되, 상기 화학적 기계적 연마공정은 상기 도전층을 식각장벽으로 사용하여 실시하는 공정과,Removing the buried insulating film by a chemical mechanical polishing process, wherein the chemical mechanical polishing process is performed by using the conductive layer as an etching barrier;
상기 도전층을 열산화시켜 제2열산화막으로 형성하는 공정과,Thermally oxidizing the conductive layer to form a second thermal oxide film;
상기 제2열산화막을 제거하는 공정을 포함하는 것을 특징으로 한다.And removing the second thermal oxide film.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d 는 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도이다.2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
먼저, 반도체기판(21) 상부에 패드산화막 및 질화막을 형성하고, 상기 질화막 상부에 소자분리영역으로 예정되는 부분을 노출시키는 감광막패턴을 형성한다.First, a pad oxide film and a nitride film are formed on the semiconductor substrate 21, and a photoresist pattern is formed on the nitride film to expose a portion intended as an isolation region.
다음, 상기 감광막패턴을 식각마스크로 상기 질화막 및 패드산화막을 식각하여 질화막패턴(25) 및 패드산화막패턴(23)을 형성하고, 상기 감광막패턴을 제거한다.Next, the nitride layer and the pad oxide layer are etched using the photoresist pattern as an etch mask to form the nitride layer pattern 25 and the pad oxide layer pattern 23, and the photosensitive layer pattern is removed.
그 다음, 상기 질화막패턴(25)을 하드마스크로 사용하여 상기 반도체기판(21)을 식각하여 트렌치(26)를 형성한다.Next, the trench 26 is formed by etching the semiconductor substrate 21 using the nitride film pattern 25 as a hard mask.
다음, 상기 트렌치(26)의 측벽을 열산화시켜 제1열산화막(27)을 형성하되, 상기 제1열산화막(27)은 700 ∼ 1200℃의 온도에서의 열산화공정으로, 상기 트렌치(26) 측벽에 50 ∼ 200Å 두께로 형성된다. (도 2a참조)Next, the sidewalls of the trench 26 are thermally oxidized to form a first thermally oxidized film 27. The first thermally oxidized film 27 is thermally oxidized at a temperature of 700 to 1200 ° C. ) 50-200 mm thick on the sidewalls. (See Figure 2A)
그 다음, 상기 질화막패턴(25)을 제거하되, 상기 질화막패턴(25)은 인산(H3PO4)용액을 식각용액으로 이용한 습식식각방법으로 제거한다. 이때, 상기 질화막패턴(25)을 제거하는 이유는 상기 트렌치(26)의 높이를 낮추어 후속공정에서 상기 트렌치(26)를 매립하는 공정을 용이하게 실시하기 위해서이다. (도 2b 참조)Next, the nitride film pattern 25 is removed, and the nitride film pattern 25 is removed by a wet etching method using a phosphoric acid (H 3 PO 4 ) solution as an etching solution. In this case, the reason for removing the nitride layer pattern 25 is to lower the height of the trench 26 so as to easily perform the process of filling the trench 26 in a subsequent process. (See Figure 2b)
다음, 전체표면 상부에 다결정실리콘층(29a)을 200 ∼ 600Å두께로 형성한다. 이때, 상기 다결정실리콘층(29a)은 비정질실리콘층으로 형성할 수도 있다.Next, a polysilicon layer 29a is formed on the entire surface at a thickness of 200 to 600 GPa. In this case, the polysilicon layer 29a may be formed of an amorphous silicon layer.
그 다음, 상기 다결정실리콘층(29a) 상부에 매립절연막(31a)으로 CVD산화막또는 PVD산화막을 형성한다. (도 2c 참조)Next, a CVD oxide film or a PVD oxide film is formed on the polysilicon layer 29a as a buried insulating film 31a. (See Figure 2c)
그 후, 상기 매립절연막(31a)을 CMP공정으로 제거하되, 상기 CMP공정은 상기 다결정실리콘층(29a)을 식각장벽으로 사용하여 실시한다.Thereafter, the buried insulating film 31a is removed by a CMP process, and the CMP process is performed using the polysilicon layer 29a as an etch barrier.
다음, 상기 CMP공정으로 노출된 상기 다결정실리콘층(29a)을 희생산화시켜 제2열산화막(29b)으로 형성한다. 상기 열산화공정은 700 ∼ 1200℃의 온도에서 실시한다. 상기 다결정실리콘층(29a)은 열산화공정시 부피가 약간 팽창하기 때문에 상기 매립절연막(31a)이 상기 트렌치 내부를 완전히 매립시키지 못하더라도 트렌치 내부에 보이드가 발생하는 것을 방지할 수 있다. (도 2d 참조)Next, the polysilicon layer 29a exposed by the CMP process is sacrificially oxidized to form a second thermal oxide film 29b. The thermal oxidation step is carried out at a temperature of 700 to 1200 ℃. Since the polysilicon layer 29a slightly expands in volume during the thermal oxidation process, voids may be prevented from occurring in the trench even when the buried insulating layer 31a does not completely fill the trench. (See FIG. 2D)
그 후, 상기 제2열산화막(29b)을 불산(HF)용액 또는 BOE(buffered oxide etchant)용액을 식각용액으로 사용하는 습식식각공정으로 제거하여 활성영역을 노출시킨다.Thereafter, the second thermal oxide layer 29b is removed by a wet etching process using a hydrofluoric acid (HF) solution or a buffered oxide etchant (BOE) solution as an etching solution to expose the active region.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 제조방법은, 고집적 반도체소자에서 트렌치를 이용한 소자분리공정시 반도체기판 상부에 소자분리영역으로 예정되는 부분을 노출시키는 패드산화막패턴과 질화막패턴의 적층구조를 형성하고, 상기 질화막패턴을 식각마스크로 상기 반도체기판을 식각하여 트렌치를 형성한 다음, 상기 트렌치 표면을 산화시킨 후 상기 질화막패턴을 제거하여 애스펙트비를 감소시킨 다음, 소정 두께의 다결정실리콘층을 증착하고 그 상부에 매립절연막을 증착하고, 상기 다결정실리콘층을 식각장벽으로 상기 매립절연막을 제거한 다음, 열처리공정을 실시하여 상기 다결정실리콘층을 산화시켜 애스펙트비가 높은 트렌치를 보이드없이 매립할 수 있으므로, 소자의 신뢰성 및 전기적 특성을 향상시키고, 반도체소자의 고집적화를 가능하게 하는 이점이 있다.As described above, the method of manufacturing a semiconductor device according to the present invention includes a stacked structure of a pad oxide film pattern and a nitride film pattern exposing a portion intended as an isolation region on an upper portion of a semiconductor substrate during a device isolation process using a trench in a highly integrated semiconductor device. To form a trench by etching the semiconductor substrate using the nitride film pattern as an etch mask, oxidizing the trench surface, removing the nitride film pattern to reduce the aspect ratio, and then forming a polysilicon layer having a predetermined thickness. After depositing and depositing a buried insulating film thereon, removing the buried insulating film with an etch barrier as the polysilicon layer, and then performing a heat treatment process to oxidize the polysilicon layer to fill a trench having a high aspect ratio without voids. Improve the reliability and electrical properties of devices, There is an advantage that enables a party integration.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980019185A (en) * | 1996-08-29 | 1998-06-05 | 히가시 데쓰로 | SUBSTRATE TREATMENT SYSTEM SUBSTRATE TRANSFER SYSTEM, SUBSTRATE TRANSFER METHOD |
| KR19990055199A (en) * | 1997-12-27 | 1999-07-15 | 김영환 | Method of forming device isolation film in semiconductor device |
| KR100214917B1 (en) * | 1996-08-28 | 1999-08-02 | 다니구찌 이찌로오, 기타오카 다카시 | Semiconductor device and method of manufacturing the same |
| KR20010061047A (en) * | 1999-12-28 | 2001-07-07 | 박종섭 | A method for forming trench type isolation layer using ceria-based slurry |
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| KR19980019185A (en) * | 1996-08-29 | 1998-06-05 | 히가시 데쓰로 | SUBSTRATE TREATMENT SYSTEM SUBSTRATE TRANSFER SYSTEM, SUBSTRATE TRANSFER METHOD |
| KR19990055199A (en) * | 1997-12-27 | 1999-07-15 | 김영환 | Method of forming device isolation film in semiconductor device |
| KR20010061047A (en) * | 1999-12-28 | 2001-07-07 | 박종섭 | A method for forming trench type isolation layer using ceria-based slurry |
Cited By (1)
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|---|---|---|---|---|
| KR100476691B1 (en) * | 2002-04-18 | 2005-03-18 | 삼성전자주식회사 | Method for Shallow Trench Isolation and Method of manufacturing Non-Volatile Memory Device comprising the same |
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