KR20010060529A - A method of manufacturing a transistor in a semiconductor device - Google Patents
A method of manufacturing a transistor in a semiconductor device Download PDFInfo
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- KR20010060529A KR20010060529A KR1019990062926A KR19990062926A KR20010060529A KR 20010060529 A KR20010060529 A KR 20010060529A KR 1019990062926 A KR1019990062926 A KR 1019990062926A KR 19990062926 A KR19990062926 A KR 19990062926A KR 20010060529 A KR20010060529 A KR 20010060529A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 32
- 150000004767 nitrides Chemical class 0.000 claims abstract description 17
- 238000005468 ion implantation Methods 0.000 claims abstract description 12
- 125000006850 spacer group Chemical group 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 10
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 238000002347 injection Methods 0.000 abstract description 5
- 239000007924 injection Substances 0.000 abstract description 5
- 230000000694 effects Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000036962 time dependent Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 소자의 트랜지스터 제조방법에 관한 것으로, 특히 핫 캐리어 주입 특성(Hotr Carrier Injection;HCI)을 개선할 수 있는 반도체 소자의 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor manufacturing method of a semiconductor device, and more particularly, to a transistor manufacturing method of a semiconductor device capable of improving hot carrier injection characteristics (HCI).
일반적으로, 저전압 N-채널 금속산화물 반도체 전계 효과 트랜지스터(low voltage NMOSFET) 소자는 핫 캐리어 특성을 개선하기 위하여 LDD(Lightly Doped Drain) 접합 구조로 형성하고 있다.In general, a low voltage N-channel metal oxide semiconductor field effect transistor (low voltage NMOSFET) device is formed of a lightly doped drain (LDD) junction structure to improve hot carrier characteristics.
핫 캐리어 효과(Hot Carrier Effect)는 고온 전자 효과(Hot Electron Effect) 내지 열전자 효과라고도 하는데, 트랜지스터에서 드레인과 소오스 사이에 가하는 전압을 일정하게 유지해 두고 채널 길이를 짧게 해 가면 채널의 드레인 단에 있는 공핍층 내의 전계가 커진다.The Hot Carrier Effect, also known as the Hot Electron Effect or the Thermo-Electron Effect, is a technique that maintains a constant voltage between the drain and the source in a transistor and shortens the channel length, leaving the void at the drain end of the channel. The electric field in the pip layer increases.
그 때문에 전자가 고속으로 가속되어 원자와 충돌해서 애벌런시 현상을 일으키고, 발생한 고속 전자의 일부는 게이트 산화막 속에 진입하고 포획되어 트랜지스터의 임계전압(VT)을 변화시킨다(NMOS 인헨스먼트형에서는 임계전압이 높아지게 된다). 이것이 트랜지스터의 동작을 불안정하게 하므로 드레인 단부의 공핍층 내 전계를 약하게 하여 애벌란시 채널측(N 채널일때)에 가볍게 도핑한 N층을 둔다. 이것을 가볍게 도핑한 드레인(Lightly Doped Drain, LDD)이라 한다.As a result, electrons are accelerated at high speed and collide with atoms, causing avalanche phenomenon, and some of the generated high-speed electrons enter and are trapped in the gate oxide film to change the threshold voltage (VT) of the transistor (critical in NMOS enhancement type). Voltage rises). This destabilizes the operation of the transistor, thus weakening the electric field in the depletion layer at the drain end, leaving a lightly doped N layer on the avalanche channel side (when N channel). This is called lightly doped drain (LDD).
이하에서는 도 1a 내지 도 1c를 참조하여 종래의 반도체 소자의 트랜지스터제조방법을 설명하도록 한다.Hereinafter, a transistor manufacturing method of a conventional semiconductor device will be described with reference to FIGS. 1A to 1C.
도 1a를 참조하면, 반도체기판(1)의 상부에 60 내지 65Å의 두께로 게이트 산화막(2)이 형성되고, 그 게이트 산화막(2)의 상부에 게이트(3)를 형성한다. 게이트(3)를 형성한 후에는 LDD영역(4)을 형성한다.Referring to FIG. 1A, a gate oxide film 2 is formed on the semiconductor substrate 1 to a thickness of 60 to 65 Å, and a gate 3 is formed on the gate oxide film 2. After the gate 3 is formed, the LDD region 4 is formed.
도 1b를 참조하면, 게이트(3) 이외의 부분에 남아있는 게이트 산화막(2)을 제거한 후, 전체 상부에 질화막(5)을 증착한다.Referring to FIG. 1B, after removing the gate oxide film 2 remaining in portions other than the gate 3, the nitride film 5 is deposited on the entire upper portion.
도 1c를 참조하면, 질화막(5)을 전면 식각공정을 통해 식각하고, 이로 인하여 게이트(3)의 양측벽에 질화막스페이서(5a)가 형성된다. 이후, 소오스/드레인 이온주입공정을 실시하여 접합부(6)가 형성된다.Referring to FIG. 1C, the nitride film 5 is etched through the entire surface etching process, whereby the nitride film spacers 5a are formed on both sidewalls of the gate 3. Thereafter, the junction 6 is formed by performing a source / drain ion implantation process.
그런데, 전술한 핫 캐리어 효과에 의하여 게이트 산화막에 영향을 미치는 TDDB(Time Dependent dielectric Breakdown)와, 소자의 신뢰성 특성에 영향을 주는 RD(Radiation, Damage) 및 ESD(Electrostatic Discharge)를 유발시키는 등의 문제점이 있었다.However, problems such as TDDB (Time Dependent dielectric Breakdown) affecting the gate oxide film and RD (Radiation, Damage) and Electrostatic Discharge (ESD) affecting the reliability characteristics of the device are caused by the aforementioned hot carrier effect. There was this.
따라서, 본 발명은 핫 캐리어 주입 특성을 개선하기 위하여 DLDD접합으로 형성된 구조를 가지는 반도체 소자의 트랜지스터 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a transistor of a semiconductor device having a structure formed by a DLDD junction in order to improve hot carrier injection characteristics.
이러한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 트랜지스터 제조방법은, 반도체기판의 상부에 게이트 산화막 및 게이트를 형성하는 단계, 상기 게이트의 양측의 상기 게이트 산화막 하부에 제 1 LDD영역을 형성하는 단계, 상기 전체 상부에 산화막을 증착한 후 제 2 LDD영역을 형성하는 단계, 상기 산화막이 증착된 전체 상부에 질화막을 증착한 후 전면식각공정을 통해 상기 질화막 및 산화막을 식각하여 상기 게이트의 양측벽에 2중 스페이서를 형성하는 단계, 소오스/드레인 이온주입공정으로 접합부를 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a transistor of a semiconductor device, the method comprising: forming a gate oxide film and a gate on an upper surface of a semiconductor substrate, and forming a first LDD region under the gate oxide film on both sides of the gate; Forming a second LDD region after depositing an oxide film on the entire upper surface; depositing a nitride film on the entire upper surface on which the oxide film is deposited; and etching the nitride film and the oxide film through an entire surface etching process on both sides of the gate Forming a double spacer, forming a junction by a source / drain ion implantation process characterized in that it comprises a.
도 1a 내지 도 1c는 종래의 반도체 소자의 트랜지스터 제조방법을 설명하기 위한 단면도.1A to 1C are cross-sectional views illustrating a transistor manufacturing method of a conventional semiconductor device.
도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 트랜지스터 제조방법을 설명하기 위한 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a transistor of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 및 10:반도체 기판 2 및 20:게이트산화막1 and 10: semiconductor substrate 2 and 20: gate oxide film
3 및 30:게이트 4:LDD영역3 and 30: gate 4: LDD region
40:제 1 LDD영역 50:산화막40: first LDD region 50: oxide film
50a:산화막 스페이서 60:제 2 LDD영역50a: oxide film spacer 60: second LDD region
5 및 70:질화막 5a 및 70a:질화막스페이서5 and 70: nitride film 5a and 70a: nitride film spacer
6 및 80:접합부6 and 80: junction
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 2d는 본 발명에 따른 반도체 소자의 트랜지스터 제조방법을 설명하기 위한 단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a transistor of a semiconductor device according to the present invention.
도 2a를 참조하면, 반도체기판(10)의 상부에 게이트 산화막(20)이 형성되고, 그 게이트 산화막(20)의 상부에 게이트(30)를 형성한다. 게이트(30)를 형성한 후에는 제 1 경사이온주입공정으로 제 1 LDD영역(40)을 형성한다.Referring to FIG. 2A, a gate oxide film 20 is formed on the semiconductor substrate 10, and a gate 30 is formed on the gate oxide film 20. After the gate 30 is formed, the first LDD region 40 is formed by the first gradient ion implantation process.
상기한 제 1 경사이온주입공정은 농도가 1.0e13 내지 0.5e13정도인 인(P31)을 20KeV의 에너지로 주입하는데, 제 1 LDD영역(40)이 게이트(30)와 충분히 겹칠 수 있도록 주입각도를 7° 내지 25°사이의 각도로 주입한다. 게이트(30)는 폴리실리콘으로 이루어진 단일 구조 혹은 폴리실리콘과 텅스텐 실리사이드로 이루어진 적층구조로 구성될 수 있는데, 적층구조일 경우에는 다음과 같은 공정에 의하여 형성된다. 게이트(30)로 사용될 폴리실리콘을 약 1000Å의 두께로 증착하고, 증착된 폴리실리콘의 상부에 텅스텐 실리사이드(WSix)를 약 1500Å의 두께로 증착한 후, 게이트 마스크를 이용하여 게이트를 형성하는데, 딥유브이스텝퍼(Deep UV stepper)에 의해 패터닝을 할 경우에는 딥유브이의 반사를 방지하기 위하여 텅스텐 실리사이드의 상부에 반사방지막인 옥시나이트라이드(oxynitride)를 약 600Å의 두께로 증착한다. 반사방지막의 증착후에는 패터닝을 하여 게이트(30)를 형성하는데 DICD는 0.35±0.03 미만이다.In the first gradient ion implantation process, phosphorus (P31) having a concentration of about 1.0e13 to 0.5e13 is implanted with an energy of 20 KeV, and the implantation angle is adjusted so that the first LDD region 40 can sufficiently overlap the gate 30. Inject at an angle between 7 ° and 25 °. The gate 30 may be formed of a single structure made of polysilicon or a laminated structure made of polysilicon and tungsten silicide. In the case of the laminated structure, the gate 30 is formed by the following process. Polysilicon to be used as the gate 30 is deposited to a thickness of about 1000 GPa, tungsten silicide (WSix) is deposited to a thickness of about 1500 GPa on top of the deposited polysilicon, and then a gate is formed using a gate mask. In the case of patterning by a deep UV stepper, an antireflection film, oxynitride, is deposited on the top of tungsten silicide to a thickness of about 600 kW in order to prevent reflection of the deep UV. After deposition of the antireflection film, patterning is performed to form the gate 30 with a DICD of less than 0.35 ± 0.03.
도 2b를 참조하면, 제 1 LDD영역(40)을 형성한 후에는 후술하는 산화막을 증착하기전의 공정으로 게이트(30) 이외의 부분에 남아있는 게이트 산화막을 제거한다. 이때 클리닝은 BOE 및 플르오르화수소(HF)를 이용하여 남아있는 게이트 산화막을 제거한다. 고온산화공정(High Temperature Oxidation)을 통하여 전체 상부에 HTO산화막(이하 산화막이라 칭함)(60)을 증착한다.Referring to FIG. 2B, after the first LDD region 40 is formed, the gate oxide film remaining in the portions other than the gate 30 is removed by a process before depositing the oxide film described later. The cleaning removes the remaining gate oxide layer using BOE and hydrogen fluoride (HF). A HTO oxide film (hereinafter referred to as an oxide film) 60 is deposited over the entirety through a high temperature oxidation process.
제 2 경사이온주입공정에 의하여 제 2 LDD영역(60)을 형성한다. 상기 제 2 경사이온주입공정은 농도가 2.5e13 내지 3.5e13정도인 인(P31)을 30KeV 이하의 에너지로 주입하여 제 2 LDD영역(60)을 형성하는데, 주입각도는 약 7°이다. 이때, 전술한 제1LDD(40)와 제 2 LDD영역(60) 형성시 인(P31) 대신 비소(As75)를 이용할 수도 있다.The second LDD region 60 is formed by the second gradient ion implantation process. In the second gradient ion implantation process, phosphorus (P31) having a concentration of about 2.5e13 to 3.5e13 is implanted with energy of 30 KeV or less to form the second LDD region 60, and the implantation angle is about 7 °. In this case, arsenic (As75) may be used instead of phosphorus (P31) when the first LDD 40 and the second LDD region 60 are formed.
후술하는 질화막 스페이서를 만들기 위하여 산화막(60)이 형성된 전체 상부에 질화막(70)을 약 400Å의 두께로 증착한다. 전체 식각을 통하여 산화막(50)과 질화막(70)을 식각한다. 그에 따라서 산화막(50)이 식각되어 산화막스페이서(50a)가 형성되고, 질화막(70)이 식각되어 질화막스페이서(70a)가 형성된다. 이때 남아있는 산화막은 50±10Å을 유지시켜 후속공정인 주입 공정시 버퍼 산화막으로 사용한다.In order to form a nitride film spacer to be described later, the nitride film 70 is deposited to a thickness of about 400 kPa on the entire upper portion of the oxide film 60. The oxide film 50 and the nitride film 70 are etched through the entire etching. Accordingly, the oxide film 50 is etched to form the oxide film spacer 50a, and the nitride film 70 is etched to form the nitride film spacer 70a. At this time, the remaining oxide film is maintained at 50 ± 10Å and used as a buffer oxide film during the subsequent injection process.
소오스/드레인이온주입공정으로 접합부(80)를 형성한다. 이때 소오스/드레인이온주입공정은 농도가 6.0e15인 고농도의 비소(As75)를 30KeV 이하의 에너지로 주입각도 0°로 주입하여 접합부(80)를 형성한다.The junction portion 80 is formed by a source / drain ion implantation process. At this time, in the source / drain ion implantation process, a high concentration of arsenic (As75) having a concentration of 6.0e15 is injected at an injection angle of 0 ° with energy of 30 KeV or less to form a junction 80.
상술한 바와 같이, 본 발명에 의하면 산화막스페이서와 질화막스페이서의 2중 구조에 의하여 제 1 LDD영역 및 제 2 LDD영역을 형성함에 따라 채널 필드간의 저항을 크게 하여 핫 캐리어의 발생을 억제함으로써, 소자의 신뢰도와 수율을 향상시킬 수 있다.As described above, according to the present invention, since the first LDD region and the second LDD region are formed by the double structure of the oxide spacer and the nitride spacer, the resistance between the channel fields is increased to suppress the occurrence of hot carriers. It can improve the reliability and yield.
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| KR100724146B1 (en) * | 2001-12-21 | 2007-06-04 | 매그나칩 반도체 유한회사 | Manufacturing Method of Semiconductor Device |
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| KR100897821B1 (en) * | 2007-07-26 | 2009-05-18 | 주식회사 동부하이텍 | Semiconductor device manufacturing method |
| KR100916120B1 (en) * | 2002-12-27 | 2009-09-08 | 매그나칩 반도체 유한회사 | Most transistor manufacturing method |
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| KR100724146B1 (en) * | 2001-12-21 | 2007-06-04 | 매그나칩 반도체 유한회사 | Manufacturing Method of Semiconductor Device |
| KR100881410B1 (en) * | 2002-06-03 | 2009-02-05 | 매그나칩 반도체 유한회사 | Manufacturing Method of Semiconductor Device |
| KR100873814B1 (en) * | 2002-07-05 | 2008-12-11 | 매그나칩 반도체 유한회사 | Semiconductor device having double LED structure and manufacturing method |
| KR100916120B1 (en) * | 2002-12-27 | 2009-09-08 | 매그나칩 반도체 유한회사 | Most transistor manufacturing method |
| KR100897821B1 (en) * | 2007-07-26 | 2009-05-18 | 주식회사 동부하이텍 | Semiconductor device manufacturing method |
| CN114783861A (en) * | 2022-03-11 | 2022-07-22 | 上海华力集成电路制造有限公司 | Method for improving HCI (hydrogen contact interface) effect of MOSFET (metal-oxide-semiconductor field effect transistor) device and MOSFET device |
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