KR20010055917A - Method for smoothing of method for manufacturing semiconductor - Google Patents
Method for smoothing of method for manufacturing semiconductor Download PDFInfo
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- KR20010055917A KR20010055917A KR1019990057252A KR19990057252A KR20010055917A KR 20010055917 A KR20010055917 A KR 20010055917A KR 1019990057252 A KR1019990057252 A KR 1019990057252A KR 19990057252 A KR19990057252 A KR 19990057252A KR 20010055917 A KR20010055917 A KR 20010055917A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract
목적 : 하부막질의 손상 및 변화를 최소화함과 동시에 우수한 단차도포성을 얻기 위해 리플로우시 가열과 동시에 울트라소닉(Ultrasonic) 또는 메가소닉(Megasonic)을 웨이퍼 주변에서 발생시킴으로써 균일한 리플로우(reflow) 및 우수한 단차도포성(step coverage)을 갖는 반도체소자 제조방법의 평탄화방법에 대해 개시한다.Purpose: Uniform reflow by generating ultrasonic or megasonic around the wafer simultaneously with heating during reflow in order to minimize damage and change of the underlying film and to achieve excellent step coverage. And a planarization method of a method of manufacturing a semiconductor device having excellent step coverage.
구성 : 본 발명의 반도체소자 제조방법의 평탄화방법은, 웨이퍼 상에 소정의 패턴을 형성하는 단계와; 소정의 패턴 상에 평탄화용 박막을 형성시키는 단계와; 평탄화용 박막에 열처리를 진행함과 동시에 소정의 주파수를 발생시켜 평탄화용 박막을 진동시키는 단계;를 포함하여 이루어진 것을 특징으로 한다.Configuration: The planarization method of the semiconductor device manufacturing method of the present invention comprises the steps of: forming a predetermined pattern on a wafer; Forming a planarization thin film on a predetermined pattern; And vibrating the planarizing thin film by generating a predetermined frequency while performing heat treatment on the planarizing thin film.
효과 : 제너레이터에서 발생된 주파수에 의해 평탄화 박막에 진동을 가하여 우수한 단차도포성을 갖는 반도체소자를 제조할 수 있으므로 고가열에 의한 하부막질의 손상을 방지할 수 있어서 반도체소자의 열화를 방지할 수 있다. 또한, 더욱 고단차화되고 있는 차세대 반도체소자 제조에 적용될 수 있는 장점이 있다.Effect: Since a semiconductor device having excellent step coverage can be manufactured by applying vibration to the flattening thin film by the frequency generated by the generator, damage to the lower film quality due to high heating can be prevented, thereby preventing deterioration of the semiconductor device. In addition, there is an advantage that can be applied to the manufacturing of the next-generation semiconductor device is becoming higher step.
Description
본 발명은 반도체소자 제조방법에 관한 것으로, 특히 하부막질의 손상 및 변화를 최소화함과 동시에 우수한 단차도포성을 얻기 위해 리플로우시 가열과 동시에 울트라소닉 또는 메가소닉을 웨이퍼 주변에서 발생시킴으로써 균일한 리플로우 및우수한 단차도포성을 갖는 반도체소자 제조방법의 평탄화방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor device, and in particular, to minimize damage and change of the underlying film and at the same time, to achieve excellent step coverage, a uniform ripple is generated by generating an ultrasonic or megasonic around the wafer at the same time as the heating during reflow. A flattening method of a method of manufacturing a semiconductor device having low and excellent step coverage.
반도체 장치의 집적도가 증가함에 따라, 이를 충족하기 위한 연구가 다각도에서 진행되어 오면서 다층 배선의 필요성이 점차 증대되었다. 다층 배선을 형성함에 있어서, 하부층의 배선과 상부층의 배선을 절연시키기 위한 금속배선간 층간 절연막(IMD: Inter Metal Dielectric)의 역할은 대단히 중요하며, 이러한 층간 절연막의 평탄화는 후속으로 형성되는 상부층의 사진 공정에 있어서, 스테퍼(stepper)의 촛점심도에 영향을 주어서 마진이 좁아지는 원인이 되기 때문에 그 중요성이 더욱 강조되고 있다. 또한 이러한 문제는 절연막간의 층간절연막(ILD: Inter Layer Dielectric)에서도 동일하게 적용된다.As the degree of integration of semiconductor devices increases, the necessity of multi-layered wiring has gradually increased as researches for satisfying this progress from various angles. In forming the multi-layered wiring, the role of the inter-metal dielectric (IMD) to insulate the wiring of the lower layer and the wiring of the upper layer is very important, and the planarization of the interlayer insulating film is a picture of the subsequently formed upper layer. In the process, the importance is further emphasized because it affects the depth of focus of the stepper and causes the margin to narrow. This problem also applies to interlayer dielectrics (ILD).
이러한 층간절연막을 평탄화 하기 위한 방법으로는 크게, 붕소와 인이 도핑된 실리케이트 글라스(Boro-Phosphor SilicateGlass : BPSG)를 침적한 후 리플로우(Reflow)하는 방법, 스핀 온 글라스(Spin On Glass ; SOG)를 침적한 후 에치백(Etchback)하는 방법, 층간절연막을 침적한 후 화학기계적 연마(Chemical Mechanical Polishing ; CMP)를 진행하는 방법 등이 있다.As a method for planarizing the interlayer insulating film, a method of depositing boron and phosphorus doped silicate glass (Boro-Phosphor SilicateGlass: BPSG) and then reflowing the spin on glass (SOG) Etch back after deposition and a method of chemical mechanical polishing (CMP) after depositing the interlayer insulating film.
그러면 여기서 종래의 평탄화방법에 대해 도면을 참조하여 설명하기로 한다.Now, the conventional planarization method will be described with reference to the drawings.
도 2는 소정의 패턴이 형성된 상부에 평탄화막이 증착된 상태를 나타낸 도면이고, 도 3은 종래의 평탄화 과정을 수행한 결과물을 개략적으로 나타낸 도면이다. 도 2 참조하면, 웨이퍼(10) 상에 소정의 공정을 수행한 결과물인 패터닝된박막(20)이 형성되어 있고, 그 상부로 절연막(30)이 증착되어 있음을 알 수 있다.2 is a view showing a state in which a planarization film is deposited on a predetermined pattern is formed, Figure 3 is a view schematically showing the result of performing a conventional planarization process. Referring to FIG. 2, it can be seen that the patterned thin film 20, which is a result of performing a predetermined process on the wafer 10, is formed, and the insulating film 30 is deposited thereon.
상기와 같이, 패터닝된 박막(20) 상에 절연막(30)이 증착된 상태에서, 후속하는 사진공정 등을 진행을 위해 단차를 감소시키는 리플로우공정을 진행한다.As described above, in a state in which the insulating film 30 is deposited on the patterned thin film 20, a reflow process for reducing the step difference is performed for the following photographic process.
이 리플로우 공정을 사용하는 단계는 주로 막질간의 층간절연막(ILD) 산화공정, 금속막 공정에서 알루미늄 증착공정에서 사용되어 진다. 상기 산화공정은 보론과 포스포러스의 농도로 조절하여 단차도포성을 향상시키고, 알루미늄은 온도를 제어하여 단차도포성을 향상시키고 있다. 상기한 과정에 의해 평탄화된 상태를 도 3에 잘 도시하고 있다.The steps using this reflow process are mainly used in the interlayer dielectric film (ILD) oxidation process and the aluminum deposition process in the metal film process. The oxidation process is controlled by the concentration of boron and phosphorus to improve step coverage, and aluminum to control the temperature to improve step coverage. The planarized state by the above process is well illustrated in FIG. 3.
그러나, 종래에는 평탄화공정을 위해 주로 공정온도를 조절하여 평탄화를 조절하였고, 평탄화를 더욱 향상시키기 위해 상기 공정온도를 너무 높일 경우에는 하부막질에 손상을 주거나 리플로우가 많이 되어 오히려 막질이 끊어지는 현상이 발생하는 문제점이 있었다.However, conventionally, the planarization is mainly controlled by adjusting the process temperature for the planarization process, and when the process temperature is increased too much to further improve the planarization, the film quality is damaged due to damage to the lower film or a lot of reflow. There was a problem that occurred.
또한, 산화막 내의 보론과 포스포러스의 농도를 지나치게 높게 할 경우에도 하부막질의 전기적 특성을 변화시키는 단점이 있었다.In addition, even when the concentration of boron and phosphorus in the oxide film is too high, there is a disadvantage in changing the electrical properties of the lower film quality.
따라서, 본 발명의 목적은 하부막질의 손상 및 변화를 최소화함과 동시에 우수한 단차도포성을 얻기 위해 리플로우시 가열과 동시에 울트라소닉 또는 메가소닉을 웨이퍼 주변에서 발생시킴으로써 균일한 리플로우 및 우수한 단차도포성을 갖는 반도체소자 제조방법의 평탄화방법을 제공하는데 있다.Therefore, an object of the present invention is to generate a uniform reflow and excellent step by generating ultrasonic or megasonic around the wafer simultaneously with heating during reflow to minimize damage and change of the underlying film and at the same time to obtain excellent step coverage. It is to provide a planarization method of a semiconductor device manufacturing method having a foam.
도 1a 및 도 1b는 본 발명의 일 실시예로서, 평탄화 과정을 나타낸 도면,1A and 1B illustrate an planarization process according to an embodiment of the present invention.
도 2는 소정의 패턴이 형성된 상부에 평탄화막이 증착된 상태를 나타낸 도면,2 is a view showing a state in which a planarization film is deposited on an upper portion of a predetermined pattern;
도 3은 종래의 평탄화 과정을 수행한 결과물을 개략적으로 나타낸 도면이다.3 is a view schematically showing a result of performing a conventional planarization process.
**도면의 주요부분에 대한 부호의 설명**** Description of the symbols for the main parts of the drawings **
100 : 웨이퍼 200 : 패턴100: wafer 200: pattern
300 : 절연막300: insulating film
상기한 목적을 달성하기 위해 본 발명의 반도체소자 제조방법의 평탄화방법은, 웨이퍼 상에 소정의 패턴을 형성하는 단계와; 상기 소정의 패턴 상에 평탄화용 박막을 형성시키는 단계와; 상기 평탄화용 박막에 열처리를 진행함과 동시에 소정의 주파수를 발생시켜 상기 평탄화용 박막을 진동시키는 단계;를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the planarization method of the semiconductor device manufacturing method of the present invention comprises the steps of: forming a predetermined pattern on the wafer; Forming a planarization thin film on the predetermined pattern; And vibrating the planarizing thin film by generating a predetermined frequency while performing heat treatment on the planarizing thin film.
이 때, 상기 주파수 발생에 있어서, 가스분위기를 사용하는 설비일 경우에 울트라소닉 및 메가소닉을 발생시키는 제너레이터를 상기 설비에 장착하여 주파수를 발생시키고, 진공분위기를 사용하는 설비일 경우에는 상기 제너레이터를 웨이퍼에 물리적으로 접촉시켜 주파수를 발생시키는 것이 바람직하다.In this case, in the frequency generation, a generator generating ultrasonic and megasonic in a facility using a gas atmosphere is installed in the facility to generate a frequency, and in the case of a facility using a vacuum atmosphere, the generator is It is desirable to generate a frequency by physically contacting the wafer.
또한, 상기 주파수는 20㎐ ∼ 20㎔ 범위 내에서 설정되는 것이 더욱 바람직하다.Further, the frequency is more preferably set within the range of 20 Hz to 20 Hz.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명한다.Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.
도 1a 및 도 1b는 본 발명의 일 실시예로서, 평탄화 과정을 나타낸 도면이다. 도 1a 및 도 1b를 참조하면, 웨이퍼(100)에 소정의 패턴(200)을 형성한 후, 상기 패턴(200) 상부로 절연막(300)을 형성시킨다.1A and 1B illustrate a planarization process according to an embodiment of the present invention. 1A and 1B, after forming a predetermined pattern 200 on the wafer 100, an insulating film 300 is formed on the pattern 200.
상기와 같이, 패턴 상에 절연막(300)이 증착된 상태에서, 후속하는 사진공정 등의 원활한 진행을 위해 단차를 감소시키는 리플로우공정을 진행한다.As described above, in a state in which the insulating film 300 is deposited on the pattern, a reflow process for reducing the step difference is performed for the smooth progress of the subsequent photographic process.
이 때, 장비에 추가로 부착한 울트라소닉 또는 메가소닉 제너레이터(미도시)를 이용하여 소정의 주파수를 발생시킴과 동시에 종래에 설정된 온도로 가열한다. 이 때, 주파수는 20㎐ ∼ 20㎔ 범위 내에서 설정되는 것이 바람직하다.At this time, an ultrasonic or megasonic generator (not shown) additionally attached to the equipment is used to generate a predetermined frequency and to heat to a conventionally set temperature. At this time, the frequency is preferably set within the range of 20 Hz to 20 Hz.
한편, 리플로우 전용장비의 경우에 주로 가스분위기에서 일정온도를 가하여 리플로우를 진행할 수도 있고, 몇몇 인시튜(in-situ)장비들은 진공중에서 일정온도만을 가열하여 리플로우를 진행할 수도 있다.On the other hand, in the case of reflow-only equipment, the reflow may be performed mainly by applying a constant temperature in a gas atmosphere, and some in-situ equipment may perform reflow by heating only a predetermined temperature in a vacuum.
상기 가스분위기를 사용하는 장비의 경우에는 반응챔버 근처에 울트라소닉 또는 메가소닉 제너레이터를 부착하여 사용하는 것이 바람직하며, 진공상태에서 온도만을 제어하는 장비의 경우에는 웨이퍼 홀더아래에 제너레이터를 설치하여 물리적으로 접촉하여 사용하는 것이 바람직하다.In the case of the equipment using the gas atmosphere, it is preferable to attach the ultrasonic or megasonic generator near the reaction chamber, and in the case of the equipment that controls only the temperature in a vacuum state, the generator is installed under the wafer holder to physically install the generator. It is preferable to use in contact.
상기한 과정을 거쳐 평탄화된 결과를 도 1b에 잘 도시하고 있다. 이와 같이, 기존의 리플로우시의 공정온도를 유지하면서 외부에서 울트라소닉이나 메가소닉 등의 주파수를 이용하여 절연막을 진동시킴으로써 균일한 리플로우가 가능하며, 평탄화가 더 양호하게 이루어짐을 알 수 있다.The planarization result through the above process is well illustrated in FIG. 1B. As such, it can be seen that uniform reflow is possible by vibrating the insulating film using a frequency such as ultrasonic or megasonic from the outside while maintaining the process temperature during the conventional reflow, and the planarization is better.
상술한 바와 같이, 본 발명에 따른 반도체소자 제조방법의 평탄화방법은, 제너레이터에서 발생된 주파수에 의해 평탄화 박막에 진동을 가하여 우수한 단차도포성을 갖는 반도체소자를 제조할 수 있으므로 고가열에 의한 하부막질의 손상을 방지할 수 있어서 반도체소자의 열화를 방지할 수 있다. 또한, 더욱 고단차화되고 있는 차세대 반도체소자 제조에 적용될 수 있는 장점이 있다.As described above, the planarization method of the semiconductor device manufacturing method according to the present invention can produce a semiconductor device having excellent step coverage by applying vibration to the planarizing thin film by the frequency generated in the generator, so that the lower film quality due to high heating Damage can be prevented and deterioration of the semiconductor element can be prevented. In addition, there is an advantage that can be applied to the manufacturing of the next-generation semiconductor device is becoming higher step.
본 발명은 상술한 실시예에 한정되지 않으며, 본 발명의 기술적 사상 내에서 당분야에서 통상의 지식을 가진 자에 의하여 많은 변형이 가능함은 명백하다.The present invention is not limited to the above-described embodiment, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.
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| KR1019990057252A KR20010055917A (en) | 1999-12-13 | 1999-12-13 | Method for smoothing of method for manufacturing semiconductor |
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