KR20010053792A - 반도체 패키지 제조용 리드프레임 - Google Patents
반도체 패키지 제조용 리드프레임 Download PDFInfo
- Publication number
- KR20010053792A KR20010053792A KR1019990054304A KR19990054304A KR20010053792A KR 20010053792 A KR20010053792 A KR 20010053792A KR 1019990054304 A KR1019990054304 A KR 1019990054304A KR 19990054304 A KR19990054304 A KR 19990054304A KR 20010053792 A KR20010053792 A KR 20010053792A
- Authority
- KR
- South Korea
- Prior art keywords
- lead
- frame
- semiconductor package
- tie bar
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
Claims (1)
- 프레임 몸체부와,상기 프레임 몸체부로부터 그 내측으로 연장형성된 다수의 아웃터리드(outer lead)와,상기 아웃터리드로부터 그 내측으로 연장형성된 다수의 인너리드(inner lead)와,상기 인너리드의 내부 둘레를 따라 부착되어 각 인너리드의 위치를 고정하는 리드락 테이프(lead lock tape)와,상기 인너리드의 내부 중심에 위치하여 그 상부면에 반도체칩이 탑재되는 다이패드(die pad)와,일단 끝부분은 상기 리드락 테이프에 부착됨과 함께 다른 일단 끝부분은 다이패드에 연결된 타이바를 포함하여서 됨을 특징으로 하는 반도체 패키지 제조용 리드프레임.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019990054304A KR20010053792A (ko) | 1999-12-01 | 1999-12-01 | 반도체 패키지 제조용 리드프레임 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019990054304A KR20010053792A (ko) | 1999-12-01 | 1999-12-01 | 반도체 패키지 제조용 리드프레임 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20010053792A true KR20010053792A (ko) | 2001-07-02 |
Family
ID=19623068
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019990054304A Ceased KR20010053792A (ko) | 1999-12-01 | 1999-12-01 | 반도체 패키지 제조용 리드프레임 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR20010053792A (ko) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006091032A1 (en) * | 2005-02-23 | 2006-08-31 | Lg Micron Ltd. | Lead frame |
KR100888885B1 (ko) * | 2007-04-19 | 2009-03-17 | 삼성전자주식회사 | 리드프레임 및 이를 갖는 반도체 장치 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0738040A (ja) * | 1993-07-23 | 1995-02-07 | Sony Corp | リードフレームとその製造方法 |
JPH0936295A (ja) * | 1995-04-28 | 1997-02-07 | Matsushita Electron Corp | リードフレームおよびその製造方法ならびに樹脂封止型半導体装置およびその製造方法 |
KR970013277A (ko) * | 1995-08-30 | 1997-03-29 | 김광호 | 패키지를 불량 방지용 홈이 형성된 리드프레임 |
JPH11204716A (ja) * | 1998-01-09 | 1999-07-30 | Hitachi Ltd | 半導体装置およびその製造方法 |
-
1999
- 1999-12-01 KR KR1019990054304A patent/KR20010053792A/ko not_active Ceased
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0738040A (ja) * | 1993-07-23 | 1995-02-07 | Sony Corp | リードフレームとその製造方法 |
JPH0936295A (ja) * | 1995-04-28 | 1997-02-07 | Matsushita Electron Corp | リードフレームおよびその製造方法ならびに樹脂封止型半導体装置およびその製造方法 |
KR970013277A (ko) * | 1995-08-30 | 1997-03-29 | 김광호 | 패키지를 불량 방지용 홈이 형성된 리드프레임 |
JPH11204716A (ja) * | 1998-01-09 | 1999-07-30 | Hitachi Ltd | 半導体装置およびその製造方法 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006091032A1 (en) * | 2005-02-23 | 2006-08-31 | Lg Micron Ltd. | Lead frame |
US8072054B2 (en) | 2005-02-23 | 2011-12-06 | Lg Micron Ltd. | Lead frame |
US8198711B2 (en) | 2005-02-23 | 2012-06-12 | Lg Micron Ltd. | Lead frame |
KR100888885B1 (ko) * | 2007-04-19 | 2009-03-17 | 삼성전자주식회사 | 리드프레임 및 이를 갖는 반도체 장치 |
US8188582B2 (en) | 2007-04-19 | 2012-05-29 | Samsung Electronics Co., Ltd. | Lead frame, semiconductor device using the lead frame, and methods of manufacturing the same |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH05226564A (ja) | 半導体装置 | |
US20040217450A1 (en) | Leadframe-based non-leaded semiconductor package and method of fabricating the same | |
KR0141952B1 (ko) | 반도체 패키지 및 그 제조방법 | |
KR0185790B1 (ko) | 반도체 장치의 제조방법 | |
JPH09129808A (ja) | 樹脂封止型半導体装置およびその製造方法 | |
KR20010053792A (ko) | 반도체 패키지 제조용 리드프레임 | |
JPH05243455A (ja) | 半導体装置及びその製造方法 | |
KR20020093250A (ko) | 리드 노출형 리드 프레임 및 그를 이용한 리드 노출형반도체 패키지 | |
JPH0653266A (ja) | 半導体装置 | |
KR0167276B1 (ko) | 비엘피 패키지 및 그 제조방법 | |
JPH04317363A (ja) | ダイパッドレス樹脂封止型半導体装置とその製造方法 | |
JP4356960B2 (ja) | 樹脂封止型半導体装置 | |
KR200331876Y1 (ko) | 반도체리드프레임의타이바와인너리드고정구조 | |
JP2001358279A (ja) | 半導体装置及びリードフレーム | |
KR100258876B1 (ko) | 반도체 시험용 패키지의 제조방법 | |
JPH0738036A (ja) | 半導体装置の製造方法 | |
KR19990034731A (ko) | 리드 온 칩형 리드 프레임과 그를 이용한 패키지 | |
KR200337333Y1 (ko) | 반도체 패키지 제조시의 히트 스프레드 유동방지구조 | |
KR19980027397A (ko) | 버틈 리드 패키지의 제조방법 | |
KR200313831Y1 (ko) | 바텀리드패키지 | |
JP2714002B2 (ja) | 樹脂封止型半導体装置の製造方法 | |
KR0152577B1 (ko) | 각형 위치 정렬 핀을 이용한 외부리드의 언더 컷 방지 방법 | |
KR20020039933A (ko) | 패키지 균열 방지용 더미 리드를 가지는 리드 프레임과그를 이용한 반도체 칩 패키지 | |
JPH08274205A (ja) | 半導体装置及びその製造方法 | |
JP2004200719A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19991201 |
|
N231 | Notification of change of applicant | ||
PN2301 | Change of applicant |
Patent event date: 20000502 Comment text: Notification of Change of Applicant Patent event code: PN23011R01D |
|
A201 | Request for examination | ||
PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 20001206 Comment text: Request for Examination of Application Patent event code: PA02011R01I Patent event date: 19991201 Comment text: Patent Application |
|
PG1501 | Laying open of application | ||
E902 | Notification of reason for refusal | ||
PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20020923 Patent event code: PE09021S01D |
|
E601 | Decision to refuse application | ||
PE0601 | Decision on rejection of patent |
Patent event date: 20030129 Comment text: Decision to Refuse Application Patent event code: PE06012S01D Patent event date: 20020923 Comment text: Notification of reason for refusal Patent event code: PE06011S01I |