KR20010036806A - Forming method for storage node of semiconductor device - Google Patents
Forming method for storage node of semiconductor device Download PDFInfo
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- KR20010036806A KR20010036806A KR1019990043973A KR19990043973A KR20010036806A KR 20010036806 A KR20010036806 A KR 20010036806A KR 1019990043973 A KR1019990043973 A KR 1019990043973A KR 19990043973 A KR19990043973 A KR 19990043973A KR 20010036806 A KR20010036806 A KR 20010036806A
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000010410 layer Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000011229 interlayer Substances 0.000 claims abstract description 6
- 238000001312 dry etching Methods 0.000 claims abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 238000001039 wet etching Methods 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 42
- 239000003990 capacitor Substances 0.000 description 12
- 238000005530 etching Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 235000001674 Agaricus brunnescens Nutrition 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer
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Abstract
본 발명은 반도체소자의 저장전극 형성방법에 관한 것으로, 고집적 반도체소자에서 소정의 하부구조물이 형성되어 있는 반도체기판 상부에 저장전극 콘택플러그가 구비된 층간절연막을 형성하고, 전체표면 상부에 저장전극으로 예정되는 부분을 노출시키면서, 상기 저장전극 콘택플러그를 노출시키는 제1희생절연막 패턴을 형성하되, 습식 및 건식식각공정을 순차적으로 형성하여 언더컷이 형성되도록 형성하고, 상기 저장전극 콘택플러그와 접속되는 제1도전층을 선택적으로 형성한 다음, 다시 상기 제1도전층을 노출시키는 제2희생절연막 패턴을 형성하고, 제2도전층을 선택적으로 형성하는 일련의 공정을 다수번 반복하여 단차를 줄이면서, 원하는 정전용량을 확보하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a storage electrode of a semiconductor device, wherein an interlayer insulating film having a storage electrode contact plug is formed on a semiconductor substrate on which a predetermined substructure is formed, and the storage electrode is formed on an entire surface of the semiconductor device. Forming a first sacrificial insulating film pattern exposing a predetermined portion, exposing the storage electrode contact plug, and sequentially forming wet and dry etching processes to form an undercut, and connecting the storage electrode contact plug. After the first conductive layer is selectively formed, a second sacrificial insulating film pattern for exposing the first conductive layer is formed again, and a series of steps for selectively forming the second conductive layer are repeated a plurality of times to reduce the step, It is a technology to secure the desired capacitance.
Description
본 발명은 반도체소자의 저장전극 형성방법에 관한 것으로, 특히 중복패턴형성과 선택적 증착막을 사용하여 저장전극을 형성하여 저장전극의 단차를 줄이면서 원하는 정전용량을 확보하는 반도체소자의 저장전극 형성방법에 관한 것이다.The present invention relates to a method of forming a storage electrode of a semiconductor device, and more particularly, to a method of forming a storage electrode of a semiconductor device for securing a desired capacitance while forming a storage electrode using overlapping pattern formation and a selective deposition film to reduce a step of the storage electrode. It is about.
최근 반도체소자의 고집적화 추세에 따라 셀 크기가 감소되어 충분한 정전용량을 갖는 캐패시터를 형성하기가 어려워지고 있으며, 특히 하나의 모스 트랜지스터와 캐패시터로 구성되는 디램 소자는 반도체기판 상에 세로 및 가로 방향으로 워드선들과 비트선들이 직교배치되어 있으며, 두개의 게이트에 걸쳐 캐패시터가 형성되어 있고, 상기 캐패시터의 중앙에 콘택홀이 형성되어 있다.Recently, due to the trend toward higher integration of semiconductor devices, it is difficult to form capacitors with sufficient capacitance due to a decrease in cell size. In particular, a DRAM device including one MOS transistor and a capacitor has a word in a vertical and horizontal direction on a semiconductor substrate. Lines and bit lines are orthogonally arranged, a capacitor is formed over two gates, and a contact hole is formed in the center of the capacitor.
이때, 상기 캐패시터는 주로 다결정실리콘을 도전체로 하여 산화막, 질화막 또는 그 적층막인 오.엔.오.(oxide-nitride-oxide)막을 유전체로 사용하고 있는데, 칩에서 많은 면적을 차지하는 캐패시터의 정전용량을 크게 하면서, 면적을 줄이는 것이 디램소자의 고집적화에 중요한 요인이 된다.In this case, the capacitor mainly uses an oxide film, a nitride film, or an O.O. (oxide-nitride-oxide) film as a dielectric, using polycrystalline silicon as a conductor, and a capacitance of a capacitor that occupies a large area in a chip. While reducing the area, reducing the area becomes an important factor in the high integration of the DRAM device.
따라서, C=(ε0 × εr × A) / T (여기서, ε0 은 진공 유전율(permitivity of vaccum), εr 은 유전체막의 유전상수(dielectric constant), A 는 캐패시터의 표면적, T 는 유전체막의 두께) 로 표시되는 캐패시터의 정전용량(C)을 증가시키기 위하여 유전상수가 높은 물질을 유전체로 사용하거나, 유전체막을 얇게 형성하거나 또는 캐패시터의 표면적을 증가시키는 증가시키는 등의 방법이 있다.Therefore, C = (ε0 × εr × A) / T, where ε0 is the vacuum permittivity of vaccum, εr is the dielectric constant of the dielectric film, A is the surface area of the capacitor, and T is the thickness of the dielectric film. In order to increase the capacitance (C) of the displayed capacitor, a material having a high dielectric constant is used as the dielectric, a thin dielectric film is formed, or the surface area of the capacitor is increased.
그러나, 이러한 방법들은 모두 각각의 문제점을 가지고 있다.However, these methods all have their problems.
즉, 높은 유전상수를 갖는 유전물질, 예를 들어 Ta2O5, TiO2또는 SrTiO3등이 연구되고 있으나, 이러한 물질들의 접합 파괴전압 등과 같은 신뢰도 및 박막특성 등이 확실하게 확인하게 확인되어 있지 않아 실제소자에 적용하기가 어렵고, 유전체막 두께를 감소시키는 것은 소자 동작시 유전체막이 파괴되어 캐패시터의 신뢰도에 심각한 영향을 준다.That is, dielectric materials having high dielectric constants, such as Ta 2 O 5 , TiO 2 or SrTiO 3 , have been studied, but reliability and thin film characteristics such as junction breakdown voltage of these materials have not been confirmed with certainty. Therefore, it is difficult to apply to a real device, and reducing the thickness of the dielectric film seriously affects the reliability of the capacitor because the dielectric film is destroyed during operation of the device.
더욱이, 캐패시터의 저장전극의 표면적을 증가시키기 위하여, 다결정실리콘층을 다층으로 형성한 후, 이들을 관통하여 서로 연결시키는 핀(pin)구조로 형성하거나, 콘택의 상부에 실린더형의 저장전극을 형성하는 등의 방법을 사용하기도 한다.Furthermore, in order to increase the surface area of the storage electrode of the capacitor, a polysilicon layer is formed in a multi-layer and then formed into a pin structure through which they are connected to each other, or a cylindrical storage electrode is formed on the contact. Other methods may be used.
그러나, 반도체소자가 고집적화되어감에 따라 저장전극은 이너실린더형 저장전극과 아우터(outter) 실린더형 저장전극으로 구분된다.However, as semiconductor devices are highly integrated, storage electrodes are classified into inner cylinder type storage electrodes and outer cylinder type storage electrodes.
특히, 상기 이너실린더형 저장전극은 제1희생절연막으로 저장전극이 형성될 부분을 노출시키는 패턴을 형성하고, 전체표면에 저장전극용 도전층을 형성한 다음, 제2희생절연막을 형성하여 평탄화시킨 후 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP 라 함)공정으로 식각공정을 실시하여 상기 저장전극용 도전층의 상부를 분리시킨 다음, 상기 제2희생절연막과 제1희생절연막을 제거하여 형성된다.In particular, the inner cylinder type storage electrode may be formed by forming a pattern exposing a portion of the storage electrode to be formed as a first sacrificial insulating film, forming a conductive layer for the storage electrode on the entire surface thereof, and then planarizing the second sacrificial insulating film. An etching process is then performed by a chemical mechanical polishing (CMP) process to separate the upper portion of the conductive layer for the storage electrode, and then remove the second sacrificial insulating film and the first sacrificial insulating film.
상기와 같이 종래기술에 따른 반도체소자의 저장전극 형성방법은, 상기와 같이 저장전극용 도전층을 분리시키기 위하여 사용되는 CMP공정은 식각균일도가 불량하여 공정후 웨이퍼 내 또는 웨이퍼간에 두께 구배가 발생하여 소자 외곽지역은 과다 연마되어 정상적인 소자가 형성되지 못하고, 공정 단가가 매우 높은 단점이 있다. 또한, 캐패시터 형성후 셀영역과 주변회로영역의 단차가 증가하여 후속 노광공정에서 단차에 의한 디포커스(defocus)로 패턴 형성에 어려움을 유발시킨다.As described above, in the method of forming the storage electrode of the semiconductor device according to the prior art, the CMP process used to separate the conductive layer for the storage electrode as described above has a poor etching uniformity, resulting in a thickness gradient in the wafer or between the wafers after the process. The outer region of the device is excessively polished, so that a normal device cannot be formed, and the process cost is very high. In addition, the step difference between the cell region and the peripheral circuit region increases after the capacitor is formed, which causes difficulty in pattern formation due to defocus due to the step difference in the subsequent exposure process.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 저장전극 콘택플러그를 형성하고, 절연막을 이용하여 저장전극패턴을 형성한 후 도전층을 선택적으로 증착하는 공정을 반복하여 저장전극을 형성함으로써 셀영역의 최종적인 단차를 감소시키고, 연마공정을 사용하지 않고 상기 저장전극패턴을 형성시 평탄화가 잘되는 물질을 사용하여 균일한 소자를 형성할 수 있는 반도체소자의 저장전극 형성방법을 제공하는데 그 목적이 있다.The present invention, in order to solve the above problems of the prior art, by forming a storage electrode contact plug, by forming a storage electrode pattern using an insulating film and then repeatedly depositing a conductive layer to form a storage electrode by forming a cell The purpose of the present invention is to provide a method for forming a storage electrode of a semiconductor device capable of reducing a final step of a region and forming a uniform device using a material that is well planarized when forming the storage electrode pattern without using a polishing process. have.
도 1 내지 도 6 은 본 발명에 따른 반도체소자의 저장전극 형성방법에 의해 형성된 저장전극의 단면도.1 to 6 are cross-sectional views of a storage electrode formed by a method of forming a storage electrode of a semiconductor device according to the present invention.
〈 도면의 주요부분에 대한 부호의 설명 〉<Description of the reference numerals for the main parts of the drawings>
11 : 반도체기판 13 : 워드라인11: semiconductor substrate 13: word line
15 : 비트라인 17 : 층간절연막15 bit line 17 interlayer insulating film
18 : 저장전극 콘택플러그 19 : 제1희생절연막18: storage electrode contact plug 19: the first sacrificial insulating film
21 : 제1감광막 패턴 22 : 홈21: first photosensitive film pattern 22: groove
23 : 제1도전층 25 : 제2희생절연막23: first conductive layer 25: second sacrificial insulating film
27 : 제2감광막 패턴 29 : 제2도전층27: second photosensitive film pattern 29: second conductive layer
31 : 제3도전층31: third conductive layer
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 저장전극 형성방법은,In order to achieve the above object, the storage electrode forming method of the semiconductor device according to the present invention,
소정의 하부구조물이 형성되어 있는 반도체기판 상부에 저장전극 콘택플러그가 구비된 층간절연막을 형성하는 공정과,Forming an interlayer insulating film having a storage electrode contact plug on the semiconductor substrate having a predetermined lower structure formed thereon;
전체표면 상부에 희생절연막을 형성하고, 상기 희생절연막 상부에 저장전극으로 예정되는 부분을 노출시키는 감광막 패턴을 형성하는 공정과,Forming a sacrificial insulating film on the entire surface, and forming a photoresist pattern on the sacrificial insulating film to expose a portion intended as a storage electrode;
상기 감광막 패턴을 식각마스크로 사용하여 상기 희생절연막을 소정 두께 습식식각하여 언더컷을 형성하고, 계속해서 건식식각공정을 실시하여 상기 저장전극 콘택플러그를 노출시키는 공정과,Using the photoresist pattern as an etch mask to wet-etch the sacrificial insulating layer to a predetermined thickness to form an undercut, and subsequently performing a dry etching process to expose the storage electrode contact plugs;
상기 감광막 패턴을 제거하고, 상기 저장전극 콘택플러그와 접속되는 도전층을 선택적으로 형성하여 버섯모양의 저장전극을 형성하는 공정에 있어서,Removing the photoresist pattern and selectively forming a conductive layer connected to the storage electrode contact plug to form a mushroom-shaped storage electrode;
상기의 공정을 다수번 실시하여 다층구조의 저장전극을 형성하는 공정을 포함하는 것을 특징으로 한다.It characterized in that it comprises a step of forming a storage electrode of a multi-layer structure by performing the above process a plurality of times.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1 내지 도 6 은 본 발명에 따른 반도체소자의 저장전극 형성방법을 도시한 단면도이다.1 to 6 are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor device according to the present invention.
먼저, 반도체기판(11) 상부에 워드라인(13) 및 비트라인(15) 등 소정의 하부구조물을 형성하고, 상기 반도체기판(11) 전체표면 상부에 저장전극 콘택플러그(18)가 구비된 층간절연막(17)을 형성한다.First, a predetermined lower structure such as a word line 13 and a bit line 15 is formed on the semiconductor substrate 11, and an interlayer having storage electrode contact plugs 18 provided on the entire surface of the semiconductor substrate 11. The insulating film 17 is formed.
다음, 전체표면 상부에 제1희생절연막(도시안됨)을 형성하고, 상기 제1희생절연막 상부에 제1감광막(도시안됨)을 형성한다. 이때, 상기 제1희생절연막은 별도의 평탄화공정이 필요없는 플로우 특성이 우수한 물질을 사용하여 형성한다.Next, a first sacrificial insulating film (not shown) is formed over the entire surface, and a first photosensitive film (not shown) is formed over the first sacrificial insulating film. In this case, the first sacrificial insulating film is formed using a material having excellent flow characteristics without a separate planarization process.
그 다음, 저장전극으로 예정되는 부분을 노출시키는 저장전극 마스크를 노광마스크로 사용하여 상기 제1감광막을 노광시킨 후 현상공정을 실시하여 제1감광막 패턴(21)을 형성한다. (도 1 참조)Subsequently, the first photoresist film is exposed using a storage electrode mask exposing a portion intended as a storage electrode as an exposure mask, followed by a development process to form a first photoresist pattern 21. (See Figure 1)
그리고, 상기 제1감광막 패턴(21)을 식각마스크로 사용하여 상기 제1희생절연막을 식각하여 상기 저장전극 콘택플러그(18)를 노출시키는 홈(22)이 구비된 제1희생절연막 패턴(19)을 형성한다. 이때, 상기 제1희생절연막 패턴(19)은 습식식각공정으로 언더컷을 형성하고, 이어서 건식식각공정을 실시하여 상기 저장전극 콘택플러그(18)를 노출시키는 홈(22)을 형성하여 표면적을 증가시킨다.In addition, the first sacrificial insulating layer pattern 19 having the groove 22 exposing the storage electrode contact plug 18 by etching the first sacrificial insulating layer by using the first photoresist pattern 21 as an etching mask. To form. In this case, the first sacrificial insulating pattern 19 is formed undercut by a wet etching process, and then performs a dry etching process to form a groove 22 exposing the storage electrode contact plug 18 to increase the surface area. .
다음, 상기 제1감광막 패턴(21)을 제거한다. (도 2 참조)Next, the first photoresist pattern 21 is removed. (See Figure 2)
그 다음, 상기 홈(22)에 매립되면서 상기 저장전극 콘택플러그(18)에 선택적으로 증착되는 제1도전층(23)을 형성한다. 이때, 상기 제1도전층(23)은 상기 홈(22)에 형성된 언더컷에 의해 상부 및 하부가 라운딩되어 표면적이 증가된 버섯모양의 저장전극이 형성되고, 저장전극으로 예정되는 부분보다 넓은 부분이 노출되기 때문에 후속공정에서 중첩마진이 증가된다. (도 3 참조)Next, a first conductive layer 23 is formed in the groove 22 to be selectively deposited on the storage electrode contact plug 18. In this case, the first conductive layer 23 is rounded by the undercut formed in the groove 22 to form a mushroom-shaped storage electrode having an increased surface area, and a portion wider than that intended as the storage electrode. The exposure increases the overlap margin in subsequent processes. (See Figure 3)
다음, 전체표면 상부에 제2희생절연막을 형성하고, 상기 제2희생절연막 상부에 제2감광막을 도포한다. 상기 제2희생절연막도 상기 제1희생절연막과 같이 플로우 특성이 우수한 박막을 사용하여 형성한다.Next, a second sacrificial insulating film is formed on the entire surface, and a second photosensitive film is coated on the second sacrificial insulating film. The second sacrificial insulating film is also formed using a thin film having excellent flow characteristics like the first sacrificial insulating film.
그리고, 상기 저장전극 마스크를 노광마스크로 사용하여 상기 제2감광막을 노광한 다음, 현상하여 제2감광막 패턴(27)을 형성한다.The second photoresist film is exposed using the storage electrode mask as an exposure mask, and then developed to form a second photoresist pattern 27.
다음, 상기 제2감광막 패턴(27)을 식각마스크로 사용하여 상기 제2희생절연막을 식각하여 상기 제1도전층(23)을 노출시키는 제2희생절연막 패턴(25)을 형성한다. 이때, 상기 식각공정은 상기 제1희생절연막의 식각방법과 동일하다. (도 4 참조)Next, the second sacrificial insulating layer pattern is etched by using the second photoresist layer pattern 27 as an etching mask to form the second sacrificial insulating layer pattern 25 exposing the first conductive layer 23. In this case, the etching process is the same as the etching method of the first sacrificial insulating film. (See Figure 4)
그 후, 상기 제2감광막 패턴(27)을 제거하고, 상기 제1도전층(23) 상부에만 제2도전층(29)을 버섯모양으로 선택적으로 형성한다. (도 5 참조)Thereafter, the second photosensitive film pattern 27 is removed, and the second conductive layer 29 is selectively formed in a mushroom shape only on the first conductive layer 23. (See Figure 5)
다음, 상기와 같은 방법을 반복하여 제3도전층(31)을 형성한 후, 상기 제3희생절연막 패턴(도시안됨), 제2희생절연막 패턴(25) 및 제1희생절연막 패턴(19)을 제거하여 저장전극을 형성한다. (도 6 참조)Next, the third conductive layer 31 is formed by repeating the above method, and then the third sacrificial insulating film pattern (not shown), the second sacrificial insulating film pattern 25, and the first sacrificial insulating film pattern 19 are removed. To form a storage electrode. (See Figure 6)
한편, 상기 공정은 저장전극의 정전용량에 따라 반복회수가 감소될 수도 있고, 증가할 수도 있다.On the other hand, the process may be reduced or increased in accordance with the capacitance of the storage electrode.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 저장전극 형성방법은, 고집적 반도체소자에서 소정의 하부구조물이 형성되어 있는 반도체기판 상부에 저장전극 콘택플러그가 구비된 층간절연막을 형성하고, 전체표면 상부에 저장전극으로 예정되는 부분을 노출시키면서, 상기 저장전극 콘택플러그를 노출시키는 제1희생절연막 패턴을 형성하되, 습식 및 건식식각공정을 순차적으로 형성하여 언더컷이 형성되도록 형성하고, 상기 저장전극 콘택플러그와 접속되는 제1도전층을 선택적으로 형성한 다음, 다시 상기 제1도전층을 노출시키는 제2희생절연막 패턴을 형성하고, 제2도전층을 선택적으로 형성하는 일련의 공정을 다수번 반복하여 단차를 줄이면서, 원하는 정전용량을 확보함으로써 중첩되는 부분을 크게 형성할 수 있어 중첩오차에 대한 문제점을 해결할 수 있고, 저장전극 형성에 필요한 레티클의 개수를 줄여 공정을 단순화시키며 그에 따른 소자의 공정 수율 및 특성을 향상시키는 이점이 있다.As described above, in the method of forming a storage electrode of a semiconductor device according to the present invention, an interlayer insulating film having a storage electrode contact plug is formed on a semiconductor substrate on which a predetermined lower structure is formed in a highly integrated semiconductor device, and the upper surface of the entire surface is formed. Forming a first sacrificial insulating film pattern exposing the storage electrode contact plug to expose the predetermined portion to the storage electrode, and sequentially forming wet and dry etching processes to form an undercut, and forming the storage electrode contact plug. Selectively forming a first conductive layer connected to the second conductive layer, and again forming a second sacrificial insulating film pattern exposing the first conductive layer, and repeatedly forming a second conductive layer selectively a plurality of steps By reducing the capacitance and securing the desired capacitance, it is possible to form a large overlapping portion, thereby reducing the overlapping error. One problem can be solved, and the number of reticles required for the formation of the storage electrode can be reduced to simplify the process, thereby improving the process yield and characteristics of the device.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990043973A KR20010036806A (en) | 1999-10-12 | 1999-10-12 | Forming method for storage node of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019990043973A KR20010036806A (en) | 1999-10-12 | 1999-10-12 | Forming method for storage node of semiconductor device |
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