KR20010022895A - Vertical interconnect process for silicon segments with thermally conductive epoxy preform - Google Patents

Abstract

The present invention provides an apparatus for vertical interconnection of silicon segments. Each segment has a plurality of adjacent dies located on a semiconductor wafer. A plurality of dies on the segment are interconnected on the segment using one or more metal interconnect layers extending to all four sides of the segment to provide edge bonding pads for external connection points. After the dies are interconnected, each segment is cut from the wafer backside using an oblique cut to provide an inwardly inclined edge wall on each segment. After the segments are cut from the wafer, the segments are placed on top of each other to form a stack. Vertically adjacent segments of the stack are electrically interconnected by attaching an electrically conductive epoxy to one or more sides of the stack. Inwardly inclined edge walls of each segment of the stack provide a recess for the electrically conductive epoxy to access the peripheral circuits and edge bonding pads on each segment. Thermally conductive epoxy preforms are provided between the segment stacks so that the segment stacks are epoxy bonded to each other. In an embodiment, the thermally conductive epoxy preform includes a plurality of glass spheres randomly dispersed within the preform to maintain the distance between the segment stacks.

Description

VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH THERMALLY CONDUCTIVE EPOXY PREFORM}

This invention is a partial priority application of US patent application Ser. No. 08 / 374,421, filed Jan. 19, 1995 and given the name "Conductive Epoxy Flip Chip", whose applicant is the same as the applicant of the present application Is a reference.

For many years, electrical devices such as transistors and integrated circuits have been fabricated using semiconductor materials including silicon and germanium. Integrated circuits are provided on a wafer using various techniques known for etching, doping and wiring. The individual integrated circuits provided on the wafer are called dies, which include a compact location called a bonding pad for external connection. Typically, the dies on the wafer are separated from each other by cutting the wafer along the boundary that forms the die. Once the dies are cut from the wafer, they are called chips and packed for use. In recent years, the proliferation of one or more powerful electronic systems has increased the need for high density integrated circuit packages.

One method for fabricating high density packages is attempting to fabricate an entire computer system on a single wafer using wafer scale integration (WSI) technology. WSI technology attempts to interconnect the die by wiring all the die on the wafer laterally using wires. However, many wires must be made extremely fine to make the required interconnect between dies, which is difficult to manufacture.

The second method for manufacturing high density packages is to physically stack the chips vertically to reduce the area required to place the chips on the circuit board. Single chip stack technology mounts individual chips on ceramic carriers, encapsulates both dies and carriers, and stacks the carriers on a printed circuit board. In this technique, all dies in the stack are interconnected by connecting the leads of the die to the printed circuit board via metal pins. Many pin counts can increase the likelihood that one of many pins may be disconnected from the circuit board, thereby significantly reducing the pin count on the circuit board, which reduces the reliability of the circuit.

Other chip stack methods, such as US Pat. No. 5,104,820, filed April 14, 1992, use a more complex process to stack dies. As shown in FIG. 1, the method modifies the individual chips 10 such that the individual chips 10 are stacked by adding a metallization pattern, called a rerouting lead, to the wafer surface. The rerouting lead 12 extends from the bonding pad 14 on the chip 10 to the newly formed bonding pad 11 and is arranged such that all rerouting leads 12 terminate on one side of the modified chip 10. As indicated by the dotted lines, each modified chip 10 is cut from the wafer and assembled into a stack (not shown). The stack is assembled so that all leads 12 of the modified chip 10 are assigned along the same side of the stack. The stack face with leads 12 is etched and polished so that the modified cross section of lead 12 of each chip 10 can be accessed. After lead 12 is exposed, a metallization layer is attached to lead 12 along the face of the stack to electrically connect each modified chip 10 of the stack. The stack is mounted and connected to a substrate to which a normal circuit is connected.

This method of rerouting leads provides an improvement in circuit density over the prior art, but is complex and expensive. In addition, as shown in Figure 1, the rerouting leads 12 extend on five adjacent dies 15 to 19, which are broken when the modified chip 10 is cut from the wafer. In this method, five die are sacrificed every 10 modified chips.

In another method of fabricating high density circuits, the stack is fabricated from the entire wafer rather than individual chips to form a wafer array. In some devices, the stack's wafers are electrically interconnected using solid vertical columns of metal conductive feed openings, such as copper. Using solid feed openings to interconnect wafers can cause damage to the wafer array due to differences in coefficients of thermal expansion during thermal cycles. In addition, the process is expensive and it is difficult to separate the wafer for repair.

For example, US Pat. No. 4,897,708, registered June 30, 1990, and US Pat. No. 4,954,875, registered September 4, 1990, also disclose other methods for interconnecting the wafer stack. These methods provide conical through holes for each wafer of the stack that expose the bonding pads on the wafer. In the stack, wafer bonding pads are electrically connected by embedding the through holes with an electrically conductive liquid or inserting electrically conductive flowable materials into the through holes to provide continuous vertical electrical connection between the wafers. While avoiding the disadvantage of interconnecting solid vertical column metal to the wafer, the use of electroconductive liquids and conductive materials requires specific tools to embed through holes. Also, in some applications, it may not be desirable to use a stack of entire wafers due to the size limitations of the electrical device.

FIELD OF THE INVENTION The present invention relates to devices for stacking and interconnecting silicon segments, and more particularly to stacking segments having a plurality of dies and sloped edge walls and to interconnecting segments on the edges of the stack using thermally conductive epoxy. It relates to a device for.

BRIEF DESCRIPTION OF THE DRAWINGS The drawings, which are attached and combined in the specification, illustrate embodiments of the invention in order to illustrate the main principles of the invention in conjunction with the description.

1 illustrates a conventional method for providing rerouting leads along one side of a chip.

2 shows a typical silicon wafer having a plurality of dies.

Figure 3 shows two segments, each segment comprising a 2x2 array die in accordance with the present invention.

4 shows a plurality of segment layouts on a wafer.

5A-5H illustrate a cross-sectional view of the wafer, showing a multilayered material attached to the wafer for interconnecting the die of the segment.

6A and 6B show the edge wall profile of the polyimide layer.

7A and 7B illustrate a metal lift-off process for providing a metal interconnect on a wafer.

8A shows the segment backside with four sloped sidewalls after the segment has been cut from the wafer.

8B shows the inclined sidewalls and front side of the three segments after being cut from the wafer.

9 shows a segment stack and a bonding process in which the segments are stacked and epoxy bonded to each other.

10A and 10B illustrate a method for providing a vertical electrical path between segments of a stack in accordance with the present invention.

Figure 11 shows the mechanism by which epoxy traces are distributed along the edge of the stack.

Figure 12 illustrates a signal transfer substrate having a plurality of stacks surface mounted in accordance with the present invention.

Fig. 13 shows a method for electrically connecting a surface mount stack to a circuit board.

Thermal Conductive Epoxy Preform Drawing

FIG. 14 is a cross-sectional view of two layers of VIP stacks mechanically bonded to each other with epoxy containing glass spheres in the epoxy for the purpose of maintaining the distance between the layers.

Figure 15 is a cross sectional view of a two layer VIP stack with a thermally conductive epoxy preform comprising glass spheres in accordance with the present invention.

Figure 16 is a plan view of a die and a glass sphere surrounded by the epoxy of Figure 14;

FIG. 17 is a plan view of the die and the thermally conductive epoxy preform of FIG.

It is therefore an object of the present invention to provide an improved device for stacking and interconnecting silicon segments.

The present invention provides an apparatus for vertically interconnecting a silicon segment stack. Each segment includes a plurality of adjacent dies on a semiconductor wafer. A plurality of dies on the segment are interconnected on the segment using one or more layers of metal interconnects extending to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the dies are interconnected, each segment is cut at the back of the wafer using oblique cutting to provide four inwardly inclined edge walls on each segment.

After the segments are cut from the wafer, the segments are placed on top of each other to form a stack that distinguishes both the stack of individual chips and the entire wafer stack. Vertically adjacent segments of the stack are electrically interconnected by attaching an electrically conductive epoxy filament or conductor to one or more stack faces. Once the segments are stacked, the inwardly inclined edge walls of each segment of the stack provide a recess for the electrically conductive epoxy to access the peripheral circuitry and edge bonding pads on each segment.

According to another aspect of the present invention, a thermally conductive epoxy preform sheet is provided such that the segment stacks are epoxy bonded to each other. The thermally conductive epoxy preform includes a plurality of glass spheres randomly dispersed within the preform.

Other objects, features and advantages of the present invention will become apparent from the following detailed description with reference to the drawings.

Hereinafter, with reference to the drawings will be described in detail an embodiment of the present invention. The invention will be described in detail with reference to the examples, but these examples should not be understood as limiting the invention. On the contrary, it is to be understood that the invention includes other modifications, modifications and equivalents that may be included within the spirit and scope of the invention as defined by the claims.

VIP process

As described above, the present invention is a partial priority application of US patent application Ser. No. 08 / 265,081, filed June 23, 1994 and given the name "vertical interconnect process for silicon segments." An overview of this VIP process will first be described in detail.

Referring to Fig. 2, a vertical interconnect process will be described in detail, starting from the standard wafer 30 provided by the manufacturer. The rectangles on the wafer 30 indicate the location of the individual die 32 on the wafer 30. Wafer 30 is typically reached from the manufacturer with ink dots 34 representing non-functional or defect free dies. In an embodiment of the invention, wafer 30 is made of silicon. However, wafer 30 can also be made using other materials such as gallium arsenide. Typically, die 32 is cut from wafer 30 to provide individual chips such as, for example, memory chips. Instead, a plurality of adjacent dies 32 on the wafer 30 gather to form the so-called segment 32 as shown in FIG. However, the dies can be cut individually according to the present invention and conventional VIP processes.

FIG. 3 is a plan view showing two segments 36A and 36B (hereinafter referred to as segment 36) on wafer 30, where each square represents one die 32. FIG. Each segment 36 is defined by a vertical border 38 and a horizontal border 40 where each segment 36 comprises groups of adjacent dies 32 on the wafer 30, thereby obtaining a segment 36 having a particular size and shape. In an embodiment of the present invention, segment 36 includes four adjacent dies 32 arranged in a 2x2 matrix as shown. This segment 36 is called a 2x2 segment. However, segment 36 may include any pattern or arrangement of adjacent die 32, such as, for example, 2 × 1 segment, 2 × 4 segment, or 4 × 4 segment die 32. Each segment 36 is provided with edge bonding pads 42 on one or more sides of the segment 36, which are used for electrical connection points for external connection. Similarly, each die 32 includes an internal bonding pad 44 for connecting the internal circuitry of die 32. Individual segments 36 are separated from wafer 30 by cutting the wafer 30 along a vertical boundary 38 and a horizontal boundary 40, typically called streets. The process of cutting segment 36 from wafer 30 will be described in more detail below.

One feature of the VIP process is that the individual dies 32 on the segment 36 are interconnected using multiple layers of die interconnect circuitry. The die interconnect circuit includes a plurality of metal traces directed in the x and y directions on the surface of segment 32. The metal traces, referred to as x-interconnect 46 and y-interconnect 48, are responsible for communicating power and signals from edge bonding pads 42 of segment 36 to selected internal bonding pads 44 of individual die 32.

4 shows a plurality of segment 36 layouts of wafer 30. At the periphery of wafer 30, the bonding pads of the individual dies 32 (see Figures 2 and 3) are routed appropriately to create a 1x1 segment 50.

Referring to Figure 3, in order to attach the metal x- and y-interconnect 46 and 48 on the wafer 30 surface to interconnect the individual die 32, the ink point 34 (FIG. 2) representing the defective die is replaced with a conventional embossed resist stripper. Must be removed from the wafer 30 first so that the ink point 34 does not affect the metal interconnects 46 and 48. Ink dot 34 is removed from wafer 30 using a conventional relief resist stripper. Embossed resist strippers are well known in the art for dissolving and removing unwanted materials from certain surfaces without damaging the original surface. After ink point 34 is removed, metal interconnects 46 and 48 are attached to wafer 30 during the wafer interconnect process.

5A-5H, a partial cross-sectional view of wafer 30 is shown. As described above, the surface of the wafer 30 includes a plurality of internal bonding pads 42 (see FIGS. 2 and 3) belonging to individual die 32 and a plurality of external bonding pads belonging to segment 36. In order to insulate die 32 from the metal interconnect to be attached to the wafer 30 surface, polyimide layer 60 is first deposited on wafer 30 as shown in FIG. 5B. Although the wafer manufacturer provides a protective film on the wafer 30 surface that insulates the circuit, polyimide layer 60 ensures that there are no holes in the protective film. Polyimide layer 60 also helps to embed Streets 38 and 40 (see FIG. 3) between die 32 of wafer 30. In an embodiment of the present invention, the polyimide layer is a standard spin that rotates horizontally such that the polyimide is centered on the wafer 30 and the wafer 30 provides a thin polyimide layer 60 on the wafer 30 to a thickness of about 2 microns on the spin motor. Attached by a coating process.

5C, the wafer 30 surface is coated with polyimide layer 60 or other insulating material, and then polyimide layer 60 is removed from the surface of wafer 30 on bonding pads 44 and 42. In an embodiment, polyimide layer 60 is removed over bonding pads 44 and 42 using standard photography processes.

During the photographing process, a photosensitive material layer called embossed photoresist is deposited on the surface of the polyimide layer 60 and baked. Next, a mask having openings forming the positions of the bonding pads 44 and 42 on the wafer 30 is placed on the photoresist using a conventional alignment device. Ultraviolet irradiation light is applied to the mask, and uncoated portions of the photoresist on the bonding pads 44 and 42 are exposed to the irradiation light. The exposed photoresist is then peeled off from the bonding pads 44 and 42 and developed in the diluted developer. After the bonding pads 44 and 42 are exposed, the remaining photoresist is removed from the wafer 30 using acetone or other embossed photoresist stripper material. Acetone is a material that cleans the photoresist but does not damage polyimide layer 60.

After the photoresist is removed, the wafer is baked to cure polyimide layer 60. Typically, the polyimide is cured at 400 ° C. for half an hour. In an embodiment of the present invention, polyimide layer 60 is cured at 350 ° C. for 6 hours to reduce the likelihood of damage to the circuit on wafer 30.

6A and 6B, in an embodiment, as shown in FIG. 6A, polyimide is used in insulating layer 60 to create a rounded edge wall 70 at the area from which polyimide layer 60 has been removed. The rounded edge wall 70 of polyimide layer 60 is preferred to facilitate deposition of layer metal 48 to be attached to polyimide layer 60. In contrast, the photoimageable polyimide 61 provides an edge wall with angled edges 72 causing discontinuities in the metal layer 49 as shown in FIG. 6B.

Referring to FIG. 5D, after polyimide layer 60 is opened on bonding pads 44 and 42, the next step in the vertical interconnect process is to electrically connect each die 32 where the first metal layer 48 is attached to wafer 30 and positioned on segment 36. Interconnect is a metal lift-off process. The first metal layer 48 deposited on the wafer 30 connects the bonding pads 44 and 42, which corresponds to the metal y-interconnect 48 of FIG. 3. The path of the metal y-interconnect 48 of the wafer 30 is determined using standard photography processes.

7A and 7B, the first step of the metal lift-off process is to attach a lift-off photoresist 74 layer on the polyimide layer 60. In an embodiment, a commercially available image reversal photoresist is attached on the wafer 30 in a known manner. Photoresist 74 is then removed at the selected area to form a metal y-interconnect 48 path. An overlying edge over which the image reversal photoresist 74 is called the receding edge wall 76 is made along the metal y-interconnect 48 path as shown in FIG. 7A.

After the selected area of photoresist 74 is removed to form a metal y-interconnect 48 path, wafer 30 is placed in a standard sputtering apparatus (not shown) that is used to deposit metal layer 48 over the entire wafer 30. In an embodiment, metal layer 48 includes a stack of chromium, titanium-tungsten, and gold. Chromium and titanium-tungsten are first combined with gold for adhesion purposes, but other metal laminations are also possible. In a conventional VIP process, about 2000 kW of chromium, 5000 kW of titanium-tungsten, and about 1200 kW of gold are deposited on the wafer 30. In an embodiment, about 6000 GPa of gold is deposited on wafer 30.

Once metal deposition is performed, the remaining photoresist 74 is removed from the wafer 30 surface. The photoresist is typically removed by immersing the wafer 30 in another embossed photoresist stripper that dissolves acetone or photoresist 74. Referring to FIG. 7B, photoresist 74 is dissolved and metal layer 48 is removed from the first polyimide layer 60 surface, leaving metal interconnect 48 (see FIG. 3). The purpose of the receding edge wall 76 is to allow acetone to flow around the edge of the metal y-interconnect 48 to effectively dissolve the photoresist 74.

After acetone is removed from the photoresist 74, the wafer 30 is baked to evaporate the acetone absorbed in the polyimide layer 60. After this step, a layer of gold remains on the polyimide layer 60 surface forming the y-interconnect 48 in contact with bonding pads 44 and 42 as shown in FIG. 5D.

After the metal y-interconnect is provided on the wafer 30 surface, a second metal layer 46 is formed on the wafer by essentially repeating the process described above. The second metal layer 46 corresponds to the x-interconnect 46 shown in FIG.

Referring to FIG. 5E, a second polyimide deposition is performed to form the polyimide layer 80 on the wafer 30. The second polyimide layer 80 is attached in the same manner as in the first polyimide layer 60 but need not be thin. After the second polyimide layer 80 is attached, holes are opened on the second layer 80 at the point on the metal y-interconnect 48 that electrically connects the metal x-interconnect 46 as shown in FIG. 5F. Once the segment 36 is stacked, the second polyimide layer 80 is also removed from the edge bonding pads 42 on each segment 36 such that the second metal interconnect 46 layer electrically connects the edge bonding pads 42.

In another embodiment, the first metal layer 48 is used to connect the edge bonding pads 42 instead of the second metal layer 46. After the second polyimide layer 80 has been removed at selected points on the wafer 30, the second polyimide layer 80 is low to prevent undesirable insulating material-producing interactions between the gold interconnect 48 and the aluminum bonding pads 44 and 42. Cures at temperature.

After the second polyimide deposition, a second metal lift-off process is performed to form the second layer of interconnect 46, as shown in FIG. 5G. Again, an image reversal photoresist is attached on the wafer 30 and the photoresist is removed at the position forming the second layer path of the gold interconnect 48 on the wafer 30. As described above, this process creates a photoresist layer that forms a path with a recessed edge wall. In an embodiment, a metal layer comprising a chromium, titanium-tungsten, and gold stack is then sputter deposited onto the photoresist. Chromium is unnecessary in the second layer 48 but can be used for standardization of the manufacturing process. After the second gold deposition has been performed, a lift-off step is performed to remove the unwanted photoresist and metal leaving the x-interconnect of FIG.

After the second metal layer 46 was deposited. A third polyimide layer 90 is deposited on the wafer 30 as shown in FIG. 5H to protect the metal x-interconnect 46 from scratch and act as a mechanical protective film for the outside world. The third polyimide layer 90 is removed around the edge of each segment 36 to expose the edge bonding pads 42 which are then electrically connected with the edge bonding pads of the other segments. Conventional photoimageable polyimide 90 or matte imageable materials can be used to protect the metal x-interconnect 46.

As shown in FIG. 5H, the first polyimide layer 60 protects the circuit on wafer 30 with the first layer of metal interconnect 48 in contact with bonding pads 44 and 42. The second polyimide layer 80 insulates the second layer 48 of the metal interconnect from the first layer 36 of the metal interconnect except for the portion where the two layers contact. Finally, a third polyimide layer 90 insulates and protects the second layer 48 of the metal interconnect.

Two layers of metal interconnects 46 and 48 provided by the wafer interconnect process add flexibility in connecting along wafer 30 to interconnect die 32 on each segment 36. Interconnecting die 32 on the segment 36 and stacking the next segment 36 is much cheaper and more reliable than prior art methods of cutting individual chips from the wafer 30, stacking the chips, and interconnecting the chips on the circuit board. .

After the wafer 30 interconnect process, a segment formation process is performed on the wafer 30. Referring again to FIG. 3, wafer 30 is separated into individual segments 36 by cutting along vertical and horizontal streets 38 and 40 between segments 36. After segment 36 is cut from wafer 30, the segment will be placed in a stacked structure. In order to reduce the overall size of this structure, the back material of segment 36 is ground and first thinned. To aid in this thinning process, the entire wafer 30 is thinned before the segment 36 is cut from the wafer 30. The thinning process reduces the wafer 30 and segment 36 height from 25 millimeters to about 8-10 millimeters.

Typically, wafer 10 is cut off on the front side where the circuit is placed so that the circuit is easily visible and not damaged in the sawing process. However, in the present invention, wafer 30 is cut along streets 38 and 40 on the backside of wafer 30 using oblique cutting. 8A shows the back side of segment 36 after the back side 100 of segment 36 has been cut from the wafer using oblique cutting. As shown, the oblique cut provides segment 36 with an inwardly inclined edge wall 102 on all four sides of segment 36.

In a conventional VIP process, in order to cut the wafer at the back side 100, a pattern of streets 38 and 40 forming a segment boundary is provided on the back side 100 of the wafer 30 to guide the saw. A pattern of segment boundaries is provided on the backside 100 for positioning the wafer 30 in a device including a video camera and a felt-tipped writing device. The wafer is mounted so that the front side of the wafer 30 faces the camera with the writing device positioned in contact with the backside 100 of the wafer 30. An image of the front side of the wafer 30 is displayed on the monitor and the operator draws the pattern on the back side 100 of the wafer 30 by moving the wafer 30 below the writing device along the pattern of segment boundaries.

Alternatively, in a conventional VIP process, a pattern of segment boundaries may also be provided on the backside of wafer 30 using conventional photography techniques. In this process, the backside 200 of the wafer 30 is applied with a photoresist, the front side of the wafer 30 is irradiated with infrared light so that the circuit appears on the backside 100 of the wafer 30 and the pattern of the segment boundaries is aligned so that the saw can be guided 30 is developed on the surface of the back 100.

After the pattern of segment boundaries is provided on the backside 100 of the wafer 30 and before the wafer is sawed, a tape layer is attached to the front side of the wafer 30 to support the segment 36 during sawing. After the wafer front side is tapered, the oblique cutting is done along the segment boundary on the back side 100 of the wafer 30. In an embodiment of the present invention, the segment edge wall 102 is made at a 45 degree angle by oblique cutting. After the segment 36 is cut, the tape is carefully removed from the front side of the wafer 30 and the segment 36 is cleaned to remove residues by sawing process and taping.

FIG. 8B shows three segments 36 positioned vertically above each other just before the segments are cut from the wafer 30 and the segments are permanently assembled and stacked. As shown, the front face 104 of each segment 36 includes metal interconnects 48 and 46 and edge bonding pads 42. Once segment 36 is assembled and stacked, the edge bonding pads 42 of segment 36 will be electrically connected with the edge bonding pads 42 of segment 36 that are vertically adjacent in the stack. The purpose of the inclined edge wall 102 is to provide a suitable for ensuring a vertical electrical connection between the edge bonding pad 42 of one segment 36 and the edge bonding pad 42 of segment 36 just below the first of the stack.

As with the conventional VIP process described above, after ensuring electrical connection, the backside 100 and the beveled edge 102 of segment 36 are insulated using a sputtered nitride process. The sputtered nitride process is similar to metal film sputtering except that silicon nitride is sputtered on the backside 100 of segment 36 instead of metal. Silicon nitride isolation is necessary to prevent noise and interference signals from being absorbed into the silicon substrate base of die 32 on segment 36.

After segment 36 has been cut and insulated from wafer 30, the circuit on segment 36 is tested for operation. Since the die 32 portion of the wafer 30 state in the prior art does not operate and the defective die is discarded without being cut from the wafer 30, the defective die must be disconnected in die 32 operation inspection. The defective die may be disconnected by using a laser to vaporize the top layer of metal interconnect 46 connected between the edge bonding pad 42 of segment 36 and the circuit of the defective die. The defective die may be disconnected by mechanically rubbing or electrically removing the top layer of metal interconnect 46. Once the top layer of the metal interconnect 46 is opened between the edge bonding pad 42 of the segment 36 and the circuit of the defective die, the defective die is no longer electrically connected to the segment 36.

Apart from disconnecting the defective die, each segment 36 is made specifically to allow each segment 36 access to a decoding circuit that may interfere with the final stack. In a conventional VIP process, each segment 36 is made specifically during a process called level programming in which a plurality of control signals are burned on each segment using a laser. Referring again to Figure 3, a plurality of control signals are provided on each segment by burning specific patterns on the control bonding pads 106 on each segment 36, although certain patterns may also be formed by electrically blowing the fuses. Can be.

After each segment 36 is made specific to each other, segment 36 is programmed. For purposes of disclosure, for programming, a redundant function die 32 refers to a routing circuit process that replaces a defective die that is disconnected. This is done by providing a replacement die 32 with the appropriate control signal intended to disconnect the original die. Programming is needed once segment 36 is up and running so that a computer or the like can access the disconnected die of the stack. Thus, segment 36 with the defective die must be programmed so that the operating die 32 is accessed instead when there is an attempt to access the defective die of the stack. The actual programming of segment 36 takes place during the manufacture of the stack as described below.

Referring to FIG. 9, a segment adhesive fixing part 110 to which a stack 112 is assembled in a stack process in which the segments 36 are stacked and adhered to each other is illustrated. In a conventional VIP process, during the stack process, the stack 112 is assembled using six adjacent segments 36 to provide six logic levels. Stack 112 is assembled by providing an epoxy 114 membrane between each pair of adjacent segments 36 and placing the next segment 36 face 104 on the alignment fixture 116. The alignment fixture 116 squeezes the stack in a horizontal plane against the fixed wall of the fixture and uses three closed void forming urethane rubber stamps 118, 119, and 120 to squeeze the stack 112 in a plane perpendicular to the base of the fixture. do. The stack 112 is then cured at 120 ° so that what remains in the fixture solidifies the stack 112. The curing cycle consists of a settling period of 15 minutes, 60 minutes of curing, and 10 minutes of cooling. In the VIP process, the segments 36 that make up the stack 112 of the present invention can have various thicknesses and can be stacked in any order, which is an advantage over the prior art in which individual dies 32 are stacked.

After the stack 112 is solidified, the edge bonding pads 42 (see FIG. 8B) on each of the segments 36 are electrically vertically connected to the stack 112 to provide an electrically operating stack 112. Conventional methods of vertically connecting elements for stacks connect electrical elements with metal rods, provide a plurality of vias in the elements and insert an electrically conductive material into the vias or embed the vias with a conductive liquid to establish electrical paths between the elements of the stack. The method of providing is included.

10A and 10B, a method according to the present invention for providing a vertical electrical path between segments 36 of a stack 112 is shown. 10A shows stack 112 from backside 100 of segment 36 with the stack positioned on its face. 10B shows the stack 112 from the front face 104 of segment 36 with the stack positioned vertically. In order to provide a vertical electrical path between segments 36 of the stack 112, a silver-embedded conductive epoxy trace 130 is distributed by the distribution mechanism 132 along the sloped edge wall 102 of the segment 36. The dispensing mechanism 132 moves epoxy traces on the stack 112 to move in the x and y directions and align with the outer bonding pads 42 of the segment 36. Epoxy trace 130 is attached to a pre-programmed position of all four edges of the stack 112 and the epoxy trace 130 flows to vertically connect the exposed metal of the bonding pad 42. The sloped edge wall 102 of segment 36 facilitates access to the outer bonding pad 42 by epoxy trace 130. The use of the inclined edge wall 102 and the epoxy trace 130 of the VIP process is an advantage in the prior art compared to using a metallization layer to provide vertical electrical connections to the stack.

As shown in Figures 10A and 10B, epoxy trace 130 is selectively distributed to different layers of stack 112 in accordance with some programming. Various epoxy traces 130 form circuit paths for specific devices and route circuits around disconnected defective dies. When segments 36 stack on top of each other to form an assembled stack 112, the position of each die 32 on segment 36 forms a vertical row of stack 112. For example, if each segment 36 of the stack 112 includes six die 32, the stack 112 will have six vertical rows of die 32. For example, to operate a circuit such as a memory circuit, a predetermined number of operating dies 32 are needed in each vertical column of segment 36. In a conventional VIP process as described above, the circuit of stack 112 comprising six segments is routed during programming to provide four operating die 32 in each column of the stack. However, other configurations are also possible according to the invention. For example, eight to twelve adjacent segment stacks may be configured to form eight logic levels of die in each column of the stack.

Referring to Figure 11, the mechanism by which the epoxy trace 130 is dispensed is shown. The dispensing mechanism 140 includes a rotating indexing vacuum chuck 134, a dispensing mechanism 132, an encapsulating rotating vacuum joint 138, a motor 142, and a 90 ° indexing mechanism 144. The encapsulation rotating vacuum joint 138 is coupled to a vacuum pump (not shown) to operate to create a vacuum at the end of the vacuum chuck 134 located below the dispensing mechanism 132. Stack 112 is positioned horizontally on vacuum chuck 134, which chuck 134 supports stack 112 on the front face 104 of the stack by vacuum. After the stack 112 is positioned above with respect to the chuck 134, the dispensing mechanism 132 rises over one edge of the stack 112 to distribute the predetermined programmed channel of the epoxy trace 130 under one side of the stack 112 as described above. The dispensing mechanism 132 moves and the vacuum chuck 134 then rotates 90 ° by the 90 ° indexing mechanism 144 so that the epoxy can be dispensed along the other edge of the stack 112. This process is repeated until all the edges of the stack 112 are epoxy applied. In an embodiment, the epoxy dispensing mechanism 132 is a 30 gage, Luer-tip 5cc hypodermic syringe with 1/1000 inch resolution and mounted on a programmable robot (not shown).

After the epoxy trace 130 has been dispensed, because the epoxy 130 is wet, the stack 112 is removed from the chuck 134 and placed in a support area with specific handling. Epoxy segment stack 112 is then placed in a convection oven for curing, which consists of 15 minutes preheating, 60 minutes curing and 10 minutes cooling. Once the electrical function of the stack 112 is tested, the stack 112 process is completed and the stack 112 is ready for mounting on a circuit receiving substrate, such as a printed circuit board.

In a conventional VIP process, the stack 112 may be connected to the circuit board by the surface mount stack 112 on the circuit board. 12, a cross-sectional view of a circuit board 150 having a plurality of stacks 112 surface mounted in accordance with a VIP process is shown. In order to surface mount the stack 112 on the circuit board 150, a plurality of holes 154 slightly larger than the circumference of the stack 112 are opened in the circuit board 150. After the hole 154 is opened in the circuit board 150, the circuit board 150 is located in the clamping fixture 152. The stack 112 is then positioned in the hole 154 of the circuit board 150 such that the front face 104 of the upper segment 36 of the stack 112 is coplanar with the printed circuit board 150. Stack 112 is fixed in place by the following operation applying a small amount of a quick cure position epoxy (not shown) at various locations around stack 112.

Stack 112 can be mounted on top of a circuit board by epoxy, but surface mounting solves problems that may occur when attaching epoxy to a circuit board around stack 112 and attaching epoxy to the vertical plane of stack 112 . The surface mount stack 112 of the circuit board 150 allows the coefficient of thermal expansion, reduces the overall height of the stack 112 on the circuit board 150 so that the stack 112 grows at an increased density, and as described below the stack 112 and the circuit board 150. It offers a number of advantages, including the ability to simplify the electrical connection between them.

Referring to Figure 13, a method for electrically connecting a stack 112 to a circuit board 150 is shown for a conventional VIP process. After attaching the epoxy 158 so that the stack 112 is secured to the circuit board 150, the stack 112 is electrically connected to the metal traces 160 on the circuit board 150 so that the computer circuits can access the die 32 on each level of the stack 112. Each stack 112 is positioned such that the edge bonding pads 42 around the upper segment 36 coincide with the positions of the metal traces 160 on the circuit board 150. To bridge the gap between the bonding pads 42 and the metal traces 160 on the circuit board 150, a silver-containing conductive epoxy whisker 162 was attached from each bonding pad 42 to the opposite metal trace 160 on the circuit board 150 using the distribution mechanism 132. do. As shown in Fig. 13, the position epoxy 158 used to secure the stack 112 to the circuit board 150 is attached so as not to interfere with the conductive epoxy whisker 162. One feature of the VIP process is that the electrical connection between the stack 112 and the metal traces 160 on the circuit board 150 is made by a conductive epoxy whisker 162 in substantially the same plane as the circuit board 150.

A horizontal epoxy whisker 162 of a conventional VIP process attaches between the circuit board 150 and the edge bonding pads 42 of the upper segment 36 of the stack 112 and below the edge of the stack 112 to interconnect the edge bonding pads 42 and segment 36 of the upper segment 36. Electrical connections between vertical epoxy traces. Horizontal and vertical conductive epoxy traces 160 and 132 attached to the stack 112 enable circuitry of the circuit board 150 to be accessed by any segment 36 of the stack 112.

In a conventional VIP process, after segments are vertically interconnected using epoxy traces (see FIGS. 10A and 10B), another program level may be employed at circuit board level 150 to correct errors of any die on segment 36. Can be. The die error is corrected by deselecting the control signal for the defective die at the circuit board level and replacing the signal with the control signal of the operating die 32 of the stack 112. This is accomplished by interconnecting a suitable metal trace 160 on the circuit board 150 with the conductive epoxy whisker 162.

After the epoxy whisker 162 is attached to the circuit board 150, the substrate 150 assembly is placed in a convection oven for final curing. This curing consists of 15 minutes of preheating, 60 minutes of curing and 15 minutes of cooling. After curing, the substrate 150 assembly is tested and encapsulated with a polyimide layer. In a conventional VIP process, the completed circuit board 150 assembly of the present invention can be used for various purposes, such as the Personal Computer Memory Card International Association (PCMCIA) card. PCMCIA cards are small credit-card size devices that can be inserted into notebooks and portable computers to provide additional input / output capabilities and increased storage capacity. The stack in the VIP process can be mounted on a PCMCIA card and used, for example, as an external memory circuit in a notebook computer.

Thermally Conductive Epoxy Preform

Since the detailed aspects of the vertical interconnect process (VIP) described in the related patent applications have been described so far, the heat conductive epoxy molded body features of the present invention will be described in detail below.

Thermally Conductive Epoxy Preform

The aspect of the thermally conductive epoxy preform of the present invention will be described in detail. In an embodiment, thermally conductive epoxy preforms may be used in the VIP process described above.

Figure 14 shows a stack product of the VIP process described in the VIP patent application associated with each other. FIG. 16 is a top view of FIG. 14 wherein glass spheres 244 are individually located below the upper die 242 with a small amount of epoxy 246 around each of the glass spheres 244.

In Fig. 14, die stacks 240 and 242 are separated by glass sphere 244 having glass epoxy 246 around glass sphere 244. In Figure 14, after liquid epoxy curing, glass sphere 244 prevents dies 240 and 242 from touching each other. The glass spheres allow the dies 240 and 242 to be separated by a predetermined distance (ie, 4-6 millimeters). This distance provides access between dies 240 and 242 to be electrically connected to a pad that lies on die 240 and 242 faces. In the absence of such separation, the two dies 240, 242 are in contact with each other, which prevents access between the dies. An electrically conductive epoxy may be inserted between the dies 240 and 242 to contact the pads. Precise separation or distance between dies is interposed in the electrically conductive epoxy as described above to form an electrical connection.

Figure 15 illustrates a thermally conductive epoxy preform in accordance with the present invention. In Figure 15, preformed epoxy 156 includes a plurality of glass spheres 254 embedded in epoxy preform 256. Preferably, glass spheres 254 are randomly dispersed within preform 256. A preferred process for forming the epoxy preform 256 is to whip the glass sphere 254 into the liquid epoxy, which is then roll shaped to form a thermally conductive epoxy sheet 256 comprising the glass sphere 254 as shown in FIG. The thermally conductive epoxy preform 256 sheet has a size between and between dies 250 and 252 (the epoxy preform 256 is shown separated into dies 250 and 252 in FIG. 19 for illustrative convenience).

Figure 17 is a plan view of a thermally conductive epoxy preform sheet of the present invention having an epoxy preform 256 located on top of die 252. Epoxy preform 73 blocks glass sphere 254 embedded in preform 256. Glass sphere 254 is preferably randomly dispersed within preform 156 as shown in FIG.

One feature of the thermally conductive epoxy preform according to the present invention is that the preform provides a stronger package strength that distributes the force more uniformly. Another preferred feature of the thermally conductive epoxy preform according to the present invention is that the thermal aspect is greatly improved such that the present invention provides a significant thermal improvement to the VIP stack. The conductive epoxy preform according to the present invention utilizes a thermally conductive material to ensure that heat can be more effectively removed between VIP layers as opposed to conventional approaches where air is conventionally used as a heat removal medium and air has relatively poor thermal conductivity. to provide.

In addition, the VIP stack is stronger because the forces are better distributed within the VIP stack. Conventional mechanical stress has concentrated on individual glass spheres. According to the invention, it is possible for the conductive epoxy preform to allow the force to be more evenly distributed throughout the stack.

The foregoing description of specific embodiments of the present invention has been disclosed for purposes of illustration and description. It is to be understood that these descriptions are not intended to be exhaustive or to limit the invention to the precise form disclosed, and that many modifications and variations are possible in the present invention. The embodiments have been selected and described as best illustrating the principles and practical application of the invention, whereby various modifications may be made to suit a particular use intended by one of ordinary skill in the art to which the invention pertains. It is possible to use the embodiment. The scope of the invention is defined by the claims and their equivalents.

Claims (47)

As a stack of electrical circuits, A stack of segments vertically located on top of each other, each stack having a plurality of edges, a plurality of dies having a circuit, and a stack of segments having electrically conductive connection points; First interconnect means for interconnecting a plurality of dies on each segment and connecting the at least one plurality of dies to the electrically conductive connection points on each segment; Access means for providing access to the electrically conductive connection point on each segment; A second interconnect adapted to said access means for electrically interconnecting said electrically conductive connection point on each said segment of said stack and providing peripheral electrical connection to said plurality of dies located in said respective segment of said stack; Way; And And a thermally conductive epoxy preform disposed between each of the segments to epoxy bond the segments to each other. The electrical circuit stack of claim 1, wherein the preform comprises a plurality of glass spheres randomly dispersed in the preform. 3. The electrical circuit stack of claim 2 wherein the electrically conductive connection points are located along one or more of the edges of each segment. 4. The electrical circuit stack of claim 3 wherein said first interconnect means comprises one or more layers of metal traces. 5. The electrical circuit stack of claim 4 wherein the metal trace layer comprises a stack of chromium, titanium-tungsten, and gold. 6. The electrical circuit stack of claim 5 wherein the access means comprises an inwardly inclined edge wall along each edge of the segment. 7. The electrical circuit stack of claim 6 wherein the interconnect means comprises an electrically conductive epoxy. 8. The electrical circuit of claim 7, wherein each segment comprises a control bonding pad and the segments are made specific to each other by having a specific pattern formed on the control bonding pad of each segment. Stack. 9. The method of claim 8, wherein the segment comprises interconnected functional dies and non-functional dies, wherein the non-functional dies are disconnected from the functional dies, and the metal traces on each segment indicate that a particular one of the functional dies is non-functional. Wherein the electrical circuit stack is routed to replace the functional die. 10. The stack of claim 9 wherein said stack comprises at least two said segments, each of said two segments comprising at least one said die, said stack having at least one vertical row of said dies having two heights. And the die is an electrical circuit stack. 11. The apparatus of claim 10, wherein the stack has at least six said segments, each of said six segments comprising at least four said dies, said stack having four vertical rows of said die, each of said vertical columns Wherein the height of the die is six, and the electrically conductive epoxy is attached to the six segments such that the four functional dies are connected to each of the four vertical rows of the die of the stack. 12. The electrical circuit stack of claim 11, wherein the stack comprises eight to twelve of the segments, each segment having four vertical rows of die to form four stacks of eight functional dies. As a stack of electrical circuits, A stack of segments located on top of each other, the stack of segments having at least three edges, each segment forming a respective one of said segments; A plurality of dies on each segment each including a plurality of first bonding pads; A plurality of edge bonding pads positioned on at least one said edge of each segment for external electrical connection; A layer of metal traces connected between the plurality of first bonding pads for interconnecting the die, the layer of metal traces connected between the plurality of edge bonding pads and the plurality of first bonding pads for connecting the die to the external electrical connection Also connected is a layer of metal traces; And And a thermally conductive epoxy preform disposed between each of the segments to epoxy bond the segments to each other. 14. The electrical circuit stack of claim 13, wherein the preform comprises a plurality of glass spheres randomly dispersed within the preform. As a stack of electrical circuits, A stack of segments located on top of each other, each stack having at least three edges, a plurality of dies having a circuit, and a stack of segments having electrically conductive connection points; First interconnect means for interconnecting a plurality of dies on each segment and connecting the at least one plurality of dies to at least one electrically conductive connection point on each segment; Access means for providing access to the electrically conductive connection point on each segment; A second interconnect adapted to said access means for electrically interconnecting said electrically conductive connection point on each said segment of said stack and providing peripheral electrical connection to said plurality of dies located in said respective segment of said stack; Means, wherein the segment comprises a functional die and a non-functional die interconnected, wherein the non-functional die is disconnected from the functional die, and the metal traces on each segment indicate that a particular one of the functional die is connected to the non-functional die. Second interconnect means routed to substitute; And And a thermally conductive epoxy preform disposed between each of the segments to epoxy bond the segments to each other. 16. The electrical circuit stack of claim 15, wherein the preform comprises a plurality of glass spheres randomly dispersed within the preform. As a stack of electrical circuits, A stack of segments vertically located on top of each other, each stack having a plurality of edges, at least one die having circuitry, and a stack of segments having electrically conductive connection points; First interconnect means for interconnecting the die on each segment and connecting the at least one die to the at least one electrically conductive connection point on each segment; Access means for providing access to the electrically conductive connection point on each segment; A second interconnect adapted to said access means for electrically interconnecting said electrically conductive connection point on each said segment of said stack and providing peripheral electrical connection to said plurality of dies located in said respective segment of said stack; Means, wherein the segment comprises a functional die and a non-functional die interconnected, wherein the non-functional die is disconnected from the functional die, and the metal traces on each segment indicate that a particular one of the functional die is connected to the non-functional die. Second interconnect means routed to substitute; And And a thermally conductive epoxy preform sheet disposed between each of the segments to epoxy bond the segments to each other. 18. The electrical circuit stack of claim 17, wherein the preform sheet comprises a plurality of glass spheres randomly dispersed within the preform sheet. As a stack of electrical circuits, A stack of segments vertically located on top of each other, each stack having a plurality of edges, at least one die having circuitry, and a stack of segments having electrically conductive connection points; First interconnect means for interconnecting the die on each segment and connecting the at least one die to the at least one electrically conductive connection point on each segment; Access means for providing access to the electrically conductive connection point on each segment; A second interconnect adapted to said access means for electrically interconnecting said electrically conductive connection point on each said segment of said stack and providing peripheral electrical connection to said plurality of dies located in said respective segment of said stack; Way; And A thermally conductive epoxy preform sheet disposed between each of the segments to epoxy bond the segments to each other, Wherein said preform sheet comprises a plurality of glass spheres randomly dispersed within said preform sheet. A stack of die located on top of each other, the stack of die each having one or more edges and electrically conductive connection points; Interconnect means for electrically interconnecting at least one said die to at least one said electrically conductive connection point; And And a thermally conductive epoxy preform sheet disposed between each of the dies to epoxy bond the dies to each other. 21. The electrical circuit stack of claim 20, wherein the preform sheet comprises a plurality of glass spheres randomly dispersed within the preform sheet. As a method for forming a stack of electrical circuits, Vertically positioning a stack of segments on top of each other, each segment having a plurality of edges, a plurality of dies having circuitry, and electrically conductive connection points; Interconnecting a plurality of dies on each segment and connecting the plurality of dies to the at least one electrically conductive connection point on each segment; Providing access to the electrically conductive connection points on each segment; Electrically interconnecting the electrically conductive connection points on each segment of the stack and providing peripheral electrical connections to the plurality of dies located in the respective segments of the stack; And Disposing a thermally conductive epoxy preform between the segments to epoxy bond the segments. 23. The method of claim 22, comprising randomly dispersing a plurality of glass spheres in the preform. 24. The method of claim 23, comprising positioning the electrically conductive connection points along the one or more edges of each segment. 25. The method of claim 24, comprising providing one or more layers of metal traces. 27. The method of claim 25, wherein in the providing of the metal trace layer, the metal trace layer comprises chromium, titanium-tungsten, and gold. 27. The method of claim 26 including providing an inwardly inclined edge wall along each of said edges of said segment. 28. The method of claim 27, comprising providing an electrically conductive epoxy. 29. The method of claim 28, wherein each segment comprises a control bonding pad and the segments are made specific to each other by having a specific pattern formed on the control bonding pad of each segment. How to. 30. The non-functional die of claim 29, wherein the segments comprise interconnected functional dies and non-functional dies, the non-functional dies disconnected from the functional dies, and the metal traces on each segment indicate that a particular one of the functional dies is non-functional. Routed to displace the functional die. 31. The device of claim 30, wherein the stack comprises at least two of the segments, each of the two segments including at least one die, and wherein the stack having at least one vertical row of dies has two heights. And the die. 32. The device of claim 31, wherein the stack has at least six said segments, each of said six segments comprising at least four said dies, said stack having four vertical rows of said die, each of said vertical columns being The six heights of the die, and the electrically conductive epoxy is attached to the six segments such that the four functional dies are connected to each of the four vertical rows of the die of the stack. 33. The method of claim 32, wherein the stack comprises eight to twelve of the segments, each of which has four vertical rows of die to form four stacks of eight functional dies. Positioning a stack of segments located on top of each other, each having at least three edges forming each segment; Providing a plurality of die on said segment, each having a plurality of first bonding pads; Providing a plurality of edge bonding pads located on one or more of said edges of said segment for external electrical connection; And Connecting a metal trace layer between the first bonding pads to interconnect the die, the metal traces connecting the die to the external electrical connection with the plurality of edge bonding pads and the plurality of first bondings; Also connected between the pads; And Disposing a thermally conductive epoxy preform between each segment to epoxy bond the segments. 35. The method of claim 34, comprising randomly dispersing a plurality of glass spheres in the preform. Placing a stack of segments on top of each other, each segment having at least three edges, a plurality of dies having circuitry, and electrically conductive connection points; Interconnecting a plurality of dies on each segment and connecting the at least one plurality of dies to at least one electrically conductive connection point on each segment; Providing access to the electrically conductive connection points on each segment; Electrically interconnecting the electrically conductive connection points on each segment of the stack and providing peripheral electrical connections to the plurality of dies located in the respective segments of the stack, wherein the segments are interconnected. A die and a non-functional die, the non-functional die disconnected from the functional die, and the metal traces on each segment route such that a particular one of the functional die replaces the non-functional die; And Disposing a thermally conductive epoxy preform between the segments to epoxy bond the segments. 37. The method of claim 36, comprising randomly dispersing a plurality of glass spheres in the preform. Positioning a stack of segments each of which has a plurality of edges, at least one die having a circuit, and electrically conductive connection points on top of each other; Interconnecting the die on each segment and connecting the at least one die to at least one electrically conductive connection point on each segment; Providing access to the electrically conductive connection points on each segment; Electrically interconnecting the electrically conductive connection points on each segment of the stack and providing a peripheral electrical connection to the die located at each segment of the stack, wherein the segment is interconnected with a non-functional die. A die, wherein said non-functional die is disconnected from said functional die, and said metal traces on each segment route such that a particular one of said functional die replaces said non-functional die; And Disposing a thermally conductive epoxy preform between the segments to epoxy bond the segments. Providing a wafer having a plurality of dies; Providing a plurality of segments, each of the plurality of segments being formed by grouping a plurality of adjacent dies of the die on the wafer; Interconnecting the plurality of adjacent dies on each one of the plurality of segments; Separating each one of said plurality of segments from said wafer; Positioning the plurality of segments on top of each other to form a stack of segments having an outer vertical plane; Electrically interconnecting a stack of the segment; And Disposing a thermally conductive epoxy preform between the segments to epoxy bond the segments. 40. The method of claim 39, comprising randomly dispersing a plurality of glass spheres in the preform. The method of claim 40, Providing an internal electrically conductive connection point on each of the plurality of dies; Providing an external electrically conductive connection point on each of the plurality of segments; Providing a metal trace layer on each one of the plurality of segments, the metal traces extending between the internal electrically conductive connection points of the plurality of dies and the external electrically conductive connection points on each of the plurality of segments; An electrically conductive epoxy is attached to at least one outer vertical face of the stack such that the electrically conductive epoxy is connected with the external electrically conductive connection point on each one of the segments of the stack to thereby electrically connect the plurality of segments to the stack. Segment stack manufacturing method characterized in that it further comprises the step of connecting. 42. The method of claim 41 wherein Providing a control bonding pad on each of the segments; Providing a control signal to the stack from an external source for accessing the segment of the stack; And Making the control signal specific for each of the segments by burning a specific pattern to the control bonding pads on each of the segments. 43. The apparatus of claim 42 wherein the stack comprises an upper segment, Providing a signal transfer substrate having a circuit and a hole; Securing the segment stack in the hole; And Electrically connecting the segment stack to the signal transfer substrate by attaching an electrically conductive epoxy trace between the signal transfer substrate and an electrically conductive connection point on the upper segment of the stack. 44. The method of claim 43, wherein the upper segment is coplanar with the surface of the signal transduction substrate. 45. The method of claim 44, wherein the electrically conductive epoxy trace lies on substantially the same side as the signal transfer substrate. Positioning a stack of die each having one or more edges and electrically conductive connection points on top of each other; Electrically interconnecting at least one of the die to at least one of the electrically conductive connection points; And Disposing a thermally conductive epoxy preform sheet between each of said segments to epoxy bond said segments. 47. The method of claim 46, comprising randomly dispersing a plurality of glass spheres in the preform sheet.