KR20010006983A - Rapid Prototyping Apparatus and Its Input/Output Probing Method, and Mixed Verification Method Using the Same - Google Patents

Abstract

The present invention relates to a rapid prototyping system capable of performing input and output probes capable of performing design verification of a designed digital circuit quickly and accurately, and a probe method thereof.

According to the present invention, a server computer generates a programming pattern for a probe additional circuit that enables the implementation of the digital circuit to be verified and the input / output probe, and the programming pattern is downloaded to each RFPD of the prototyping engine. Allows the circuit to be implemented on prototyping and to perform input and output probes through the added input and output probe additional circuitry.

Description

Rapid Prototyping Apparatus and Its Input / Output Probing Method, and Mixed Verification Method Using the Same}

The present invention relates to an emulation-based design verification technique that verifies a designed digital circuit at high speed, in particular using a rapid prototyping device consisting of programmable elements (or chips) in the same form as real hardware. To quickly implement input and output probes for signal lines in a desired digital circuit or signals present in a hardware description language (HDL) code describing the behavior of a particular digital circuit. will be.

Recently, with the rapid development of integrated circuit design and semiconductor process technology, the scale of digital circuit design is increasing and its configuration is becoming complicated. In addition, competition in the market is getting fiercer, so it is necessary to develop excellent products in a short time. Therefore, there is a growing need for rapid prototyping to efficiently and quickly implement and verify circuits designed in a short time.

Until now, software simulators have been mainly used to verify the designed digital circuits. However, since simulators rely on virtual modeling using software rather than actual circuit implementations, they are different from the actual performance of digital circuits, which are hardware. There is a limitation that it is impossible to integrate and verify the whole system (called ICE, In-Circuit Emulation). In addition, simulation software and computers that rely on a single processor can't keep up with the rapidly increasing complexity of millions or millions of gate-class digital circuits, requiring unimaginable long simulation times for design verification. In order to overcome the shortcomings of this software simulator and to fully verify the designed circuit in a faster time, a hardware emulation-based design verification technique called "fast prototyping" that can perform near-real-time and quick verification is provided. It appeared. Validating digital circuits designed using this rapid prototyping is to verify digital circuits on real-world hardware, enabling fast design verification and verification under more practical hardware conditions than software virtual environments. It can also be integrated with the hardware environment. This digital circuit design verification process using rapid prototyping basically applies the test signal values to the inputs of the target circuit and outputs a number of signal lines in the circuit (all signal lines in the circuit, if necessary). This is to check whether each of the logic values appearing in the field matches the logic value intended by the designer. In addition, the design verification is performed from the state of the circuit by inputting desired state values at the beginning or the middle of the design verification to the memory elements (flip-flops or latches) present in the digital circuit to be subjected to design verification. By doing so, design verification time can be significantly shortened. The technique relates to a new input / output probe method for rapid prototyping systems.

First, the structure of a general rapid prototyping device will be described. Reusable Field Programmable Devices (hereinafter referred to as "RFPDs") are used as a core device of the rapid prototyping device. The RFPD is generally referred to as an interconnection resource (hereinafter referred to as "IR") that connects a basic cell ("BC") 13 and a BC 13 that can be programmed as shown in FIG. 2. ) Since the BC 13 can constitute only a limited simple digital circuit, a general complex digital circuit is implemented by connecting several BCs 13 through an IR. These RFPDs include Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). Due to recent advances in semiconductor technology, RFPD has become highly integrated, resulting in highly complex digital circuits. As a result, it is possible to prototype using only one RFPD or very few RFPDs. This makes prototyping economical, but when prototyping, many of the many signal lines on the digital circuit that are subject to design verification are present inside the RFPD, making the probes more difficult to probe. It caused serious problems. This will become a bigger problem in the future when more integrated RFPD is used. The configuration of a rapid prototyping device that completely solves this problem is as follows. This rapid prototyping device comprises a prototyping engine 44 having one or more RFPDs 12 as shown in FIG. 1, a rapid prototyping system operating software and prototyping engine 44 embedded in the server computer 20 and the server computer. It consists of a relay module 30 for relaying a signal between the (). The digital circuit implementation process using RFPD requires the following steps: mapping, placement and connection, programming pattern generation, and program pattern download. RFPD is a programmable device that can be implemented through programming, and at the same time, such a programming can be repeated many times and other circuits can be implemented by programming using different programming patterns. In the rapid prototyping device, the RFPDs 12 are mapped, arranged and wired, programming patterns are generated, and programming patterns are downloaded according to programming patterns from the server computer 20 to configure circuits designated by the server computer 20 and to configure the circuits. Will perform the operation of. The server computer 20 generates a programming pattern for the circuit designed by the designer and downloads the generated programming pattern to the prototyping engine 44 via the relay module 30 to generate the RFPD ( Implement the circuit on 12). The server computer 20 applies the circuit verification input signals to the prototyping engine 44 through the relay module 30 and then analyzes the signal responses from the prototyping engine 44 via the relay module 30. The validity of the circuit designed by the designer is verified. The relay module 30 transmits the programming pattern from the server computer 20 to the prototyping engine 44 and applies the circuit verification input signals to the prototyping engine 44 and from the prototyping engine 44. The returned signal responses and probe signal values are sent to the server computer 20. In order to relay these probe signal values, the relay module 30 has one or more probes (PL1 to PL6 in the example shown in FIG. 1) connected to the RFPDs 12 in the prototyping engine 44, respectively.

In the rapid prototyping device configured as described above, the probe line is used for the purpose of probing an input / output probe of desired signal lines among all signal lines existing in the digital circuit to be verified on the prototyping engine.

In the existing probe methods, there are only methods for output probes. In this case, a server computer is implemented in all RFPDs 12 in the prototyping engine 44 to detect and verify a signal on a signal line hidden inside the RFPD. The circuit had to be reimplemented entirely. The existing methods required the following process to detect and verify the signal on the signal line hidden inside the RFPD. In other words, the user should secure as many output pins as the number of signal lines for the output probe to the corresponding RFPD which has the corresponding signal line for the output probe, and investigate whether it is possible to connect the corresponding signal lines one by one to each output stage. A separate output pin is connected to each of the probe signal lines by a manual method, and the user repeats the mapping, layout, wiring, and programming processes from the beginning to prepare a new programming pattern for the entire RFPD. In addition, the new programming pattern required reprogramming of the entire RFPD.

In other words, unlike the present method, any signal lines existing in the circuit to be verified can be probed through an automated method on a prototyping engine that implements the same without having to secure as many RFPD input / output pins as the number of signal lines required for the probe. Not all of the methods of input are possible, only the output probe is possible, and the output probe for a specific signal line may not be possible at all. The output probe of must be secured before the output probe could be performed.

Accordingly, an object of the present invention is to provide a rapid prototyping device and a method for inputting / outputting a probe of all signal lines on a circuit or all signals present in an HDL code for rapid verification of a digital circuit. have.

1 is a schematic illustration of a rapid prototyping device of the present invention;

2 is a diagram illustrating an asynchronous circuit example, and is a diagram of a 4-bit asynchronous binary counter.

3 (a) and (b) schematically show symbols and functional functions of a single input D flip-flop having one data input D;

3 (c) and (d) schematically show the symbols and functional functions of a single input D flip-flop having one data input (D) and an asynchronous set / reset (AR / AS) input;

3 (e) and (f) schematically show the symbol and functional functions of a dual input D flip-flop having two data inputs D1 and D2;

4 is a diagram schematically showing an example of a shift register array structure in which a parallel load and a serial load showing an IOP probe additional circuit according to the present invention are possible according to an input / output mode.

FIG. 5 is a schematic illustration of another example of a shift register array structure in which the parallel and serial loads of FIG. 4 are enabled in accordance with an input / output mode. FIG.

FIG. 6 is a schematic illustration of an implementation example of the dual input D-type flip-flop of FIG. 3 (a); FIG.

Fig. 7 (a) is a diagram schematically showing a situation in which an additional circuit for IOP-probe is added to the design verification target circuit in Fig. 2;

Fig. 7 (b) schematically shows the control circuit used in the situation where the IOP-probe additional circuit is added to the design verification subject circuit of Fig. 2 and is defined by a truth table.

Fig. 8 (a) is a schematic diagram showing a situation in which any flip-flop of the design verification target circuit has an asynchronous set and an asynchronous reset.

Fig. 8B is a schematic diagram showing a situation in which the flip-flop of Fig. 8A is converted in the extended design verification target circuit.

Fig. 8 (c) defines the truth table of the control circuit used in Fig. 8 (b).

9 is a flowchart illustrating a design verification method according to an embodiment of design verification using FIG.

FIG. 10 is a flow chart illustrating a design verification method according to another embodiment of design verification using FIG. 1. FIG.

Figure 11 is a schematic illustration of a timing and functional mixing verification apparatus of the present invention.

12 is a flowchart illustrating a design verification method according to an embodiment of design verification using FIG.

FIG. 13 is a flowchart illustrating a design verification method according to another embodiment of design verification using FIG. 11. FIG.

<Description of the code | symbol about the principal part of drawing>

12: RFPD 13: BC

20: server computer 24: probe

26: system interface port 30: relay module

32: Prototyping System Software 34: Simulator

44: Prototyping Engine 74: Multiplexer

75: dual input D flip flop 76: single input D flip flop

77: dual input flip-flop with asynchronous set and asynchronous reset

78: Single Input Flip-Flop with Asynchronous Set and Asynchronous Reset

79: Tri-state buffer

In order to achieve the above object, the rapid prototyping apparatus according to the present invention is a prototyping apparatus having a prototyping engine, a server computer, and a relay module, wherein the prototyping engine includes at least one RFPD, and the server computer If the prototyping engine contains two or more RFPDs, the prototyping system software is executed to divide the design verification circuit, assign the divided partial circuits of the design verification circuit to each RFPD in the engine, and designate the design verification circuit. To generate a programming pattern for the relay module, the relay module provides a prototyping device that is responsible for the interface between the server computer and the prototyping engine.

At this time, the prototyping engine module having one or more RFPDs has an output probe line and an input probe line connected to an input / output terminal of the RFPD, and further includes an IOP probe additional circuit (described below). Moreover, the prototyping system software includes a probe additive circuit synthesizer for generating an IOP probe additional circuit.

Primarily, the rapid prototyping device further comprises an ASIC vendor library, wherein the IOP-probe supplementary circuitry is implemented with the design verification circuitry in each of the RFPDs by executing prototyping system software by the server computer. . Additional circuits for IOP probes refer to any circuit that meets the following definition: That is, the circuit part formed by adding an additional circuit in the output probe mode is a circuit completed by adding the IOP-probe supplementary circuit to the design verification target circuit. In the shifting operation synchronized with the probe clock, the logic value of the shift register immediately before the shifting operation has the logic value of the signal lines to be output probe, and at the same time, the logic value of all flip-flops in the circuit under design verification after the shifting operation is completed. Are maintained to be the same as the logic values immediately before the shifting operation, and in the input probe mode, the circuit portion formed by adding an additional circuit has a shift register structure to perform the shifting operation. Synchronous or asynchronous to flops nchronous) The set and reset operations cause the logic values of the flip-flops to be input probes to be input probe values, and at the same time, the rest of the design verification target circuits not included in the input probe targets after the shifting operation is completed. The logic values of the flip-flops remain the same as the logic values immediately before the shifting operation, and in the normal mode, the functional logical behavior of the circuit to be verified is not modified even if the additional circuit for the IOP probe is added. Is called an additional circuit for IOP probe. Alternatively, when the design verification target is dictated by the HDL code, the HDL additional code representing the behavior of the IOP probe additional circuit is added to the design verification target HDL code so that the completed HDL code is the additional HDL code in the output probe mode. The HDL part formed by adding the represents the shift register behavior, so that the shifting operation synchronized with the probe clock is performed. The signal values of the register HDL code signal lines in the HDL code expressing the shift register behavior immediately before the shifting operation are output probes. The signal values of the signals of the HDL code expressing the flip-flops behavior in the design-verification target HDL code having the target signal values and at the same time after the shifting operation is completed are maintained to be the same as the signal values immediately before the shifting operation. In probe mode, the part of the HDL code formed by adding the additional HDL code It has a presistor structure and performs a shifting operation synchronized with the probe clock. By using this shifting operation, a synchronous or asynchronous set of signals of the HDL code representing the flip-flops of the HDL code that is the input probe target is used. The set and reset operations make the logic values of the signals that are input probe targets the input probe values, and at the same time express the flip-flops of the HDL code that is not included in the input probe targets after the shifting operation is completed. While the signal values of the remaining HDL signals are kept the same as the signal values immediately before the shifting operation, in the normal mode, even if the IOP probe additional circuit is added, the HDL code that does not modify the behavior of the design verification HDL code is also IOP-. Also called probe additional circuit.

An example of one way of implementing the function of such an IOP-probe add-on circuit is that the IOP-probe add-on circuit can be applied to signal-beds and double-input flip-flops in the probe bed in the RFPD on which the design verification target circuit is implemented. By doing so, parallel-load and serial-loads of the same length or more (the length of the number of flip-flops on the shift register array structure) can be a shift register array structure in which both modes can be changed according to the mode conversion. Or the length of the shift register array structure where the longest parallel load and the serial load can both be changed by mode conversion, and the remaining integer multiples of the shift register array structures where the other parallel load and the serial load can be both mode changed are In the output probe mode, one input of each of the dual input flip-flops Is connected to signal lines on the output probe to enable parallel loading of each of the logic values on the signal on the output probe into each of the dual input flip-flops, and then output one flip-flop present in each of the one or more shift register array structures. The logic values of all the flip-flops of the shift register are logically connected to one of the input / output pins (I / O pins) serving as one or more output probe lines of the RFPD, and shifted in synchronization with the probe clock of the shift register. The input of the flip-flop is provided on the input / output pins, which act as output probes, in order.In the input probe mode, as long as one or more parallel loads and serial loads are present in each of the shift register array structures that can be changed according to the mode conversion. Logically on one of the input and output pins The input probe value sequentially supplied from the outside through the input / output pin serving as the input probe line by the shifting operation synchronized with the probe clock to be loaded into the shift register in a serial manner, and the one or more parallel loads. The output of each flip-flop constituting a shift register array that can be used is a system clock (the system clock is a single-user clock that is used globally in the circuit to be verified for design, or the design verification is applied to the clock input of the corresponding flip-flop that is the input probe target. Where the master clock used to generate one or more user clocks used in the target circuit is directly connected, each of which replaces each corresponding flip-flop that drives each of the corresponding input probe target signal lines. To one input of a dual input flip-flop, or If the system clock is not directly connected to the clock input of the flip-flop on the probe, each flip-flop that drives each of the input probe target signal lines is flipped with an asynchronous set and an asynchronous reset. Replace the flop and replace the asynchronous set input and the asynchronous reset input of this flip-flop with the output line of the flip-flop having the input probe value for the flip-flop on this probe in the flip-flops of the shift register array, the operation mode control line and the finite state machine. It can be implemented by controlling the output line of the (Finite State Machine) to set the output of the flip-flop to be the input probe object to 0 or 1. For this purpose, the above-mentioned finite state machine is additionally required. The role of the finite state machine used here is that the signal supplied from the shift register array is required only when the asynchronous set and the asynchronous reset of the flip-flop to be input probe are required. It generates and supplies a set / reset enable signal so that an asynchronous set and an asynchronous reset occur by value. For this purpose, the output line of the flip-flop having the input probe value for the flip-flop which is on the probe in the flip-flops of the shift register array, the set / reset enable signal line from the finite state machine, and the operation mode control ( The probe lines should be used to control the asynchronous set and asynchronous reset of the flip-flops that are the input probe targets, which can define and implement a simple combinatorial function. The functional behavior and role of this finite state machine will be explained in detail later with examples. In addition, if some or all of the flip-flops used in the design verification target circuit already have an asynchronous set and an asynchronous reset and the system clock is not directly connected to the clock inputs of these flip-flops, the corresponding flip-flop as an input probe target. Functional logic of the original design verification circuit while attempting to convert the circuit as mentioned above as an additional IOP probe additional circuit including a control circuit for driving asynchronous set and asynchronous reset inputs while using the It can be considered that it can only be modified in normal mode, which is not difficult, and this will be described later with an example.

In the present invention, the output probe line and the input probe line may exist as separate independent unidirectional probe lines, or the output probe line and the input probe line may exist as a bidirectional probe line in which the output probe line and the input probe line are combined, and the RFPD in the prototyping engine may include a field programmable gate array ( FPGA) or a composite programmable logic device (CPLD).

The prototyping engine module having one or more RFPDs further includes one or more output probes and one or more input probes and an IOP probe additional circuit connected to the input and output terminals of the one or more RFPDs. Is determined if each of the signal line on the probe is an input probe signal line or an output probe signal line, wherein the input step is present on the probe signal lines present in the design verification target circuit, or the design verification HDL code And inputting the signals on the coveter to the server computer, wherein the programming pattern step is such that the signal value at a specific time in the signal lines on the output coveter appears only on the output probe for a certain period of time. Tests assigned to this RFPD to have input probes with signal values applied at specific times Further comprising the step of adding the probe to the adding circuit the circuit to generate an extended target circuit design verification, and constitutes the extended design verification to the circuit implemented on the RFPD.

In addition, for signal lines on the output probe, signal values at specific time points on the signal lines on the output probe are displayed on the output probe of the RFPD having the inside of the probe on the probe using the IOP probe additional circuit. The value shown in the figure is transmitted to the server computer through the system interface port and the relay module, and the transmitted value is analyzed.For the signal line on the input probe, the data for the input probe is generated from the server computer, and then the relay module and the system interface port are Apply to the input probe line of the corresponding RFPD by synchronizing with the probe clock only or by synchronizing with the probe clock and changing the probe mode between the input probe mode and the output probe mode through the probe mode control signal line. The signal value of the signal line on the probe passes through the input probe And having the input probe value transmitted.

The rapid prototyping method according to the present invention comprises the steps of: inputting a design verification target circuit and an ASIC vendor library name into a server computer, inputting the signal-phase signal lines existing in the design verification target circuit into a server computer, and inputting the circuit. If two or more RFPDs on the prototyping engine are allocated and allocated to two or more RFPDs, and if the prototyping engine is composed of one RFPD, the entire design verification circuit is allocated to the RFPD, and assigned to a specific RFPD on the prototyping engine. Determining if each of the probe signal lines is an input probe signal line or an output probe signal line if the probe signal lines are allocated to the RFPD for the circuit, and the signal value at a specific time in the signal lines on the output probe is output. The probe should only appear for a certain period of time and the signal lines on the input probe Adding an additional circuit for IOP probe to the circuit to be assigned to this RFPD so as to have a signal value applied to the output probe at a specific time period, thereby creating an extended design verification circuit; Technology mapping, layout and wiring, and programming pattern generation steps to implement the target circuit in the corresponding RFPD, and the generated programming patterns are downloaded from the server computer to each RFPD in the prototyping engine through the relay module and the system interface port. A circuit that is functionally equivalent to the verification target circuit is implemented on the prototyping engine, and an input waveform is applied to the input of the circuit equivalent to the design verification circuit implemented on the prototyping engine and the output waveform is output from the output. Observe and, if necessary, for the output probe signal line, In this case, when the signal line on the output probe is present in the RFPD, the signal value of the signal line on the output probe is displayed on the output probe of the corresponding RFPD by using the IOP probe additional circuit. Analyzing the transmitted value by transmitting the displayed output probe value to the server computer through the system interface port and the relay module. For the input probe signal line, the signal value of the signal line on the input probe using the IOP probe additional circuit. And having the input probe value transmitted from the server computer to the input probe line through the relay module and the system interface port.

The rapid prototyping method according to the present invention comprises the steps of: inputting a design verification HDL code and ASIC vendor library name into a server computer, inputting a coveted signal present in the design verification HDL code into a server computer; The assigned HDL code is divided and assigned to two or more RFPDs if the RFPD on the prototyping engine is two or more, and if the prototyping engine consists of one RFPD, the entire design-proven HDL code is allocated to the RFPD. If onboard signals are assigned to the HDL code assigned to the RFPD, determining whether each of the onboard signals is an input probe signal or an output probe signal, and at a specific time in the signals on the output probe. So that the signal value of appears on the output probe only for a certain time. The probe part expressing the behavior of the IOP probe additional circuit is added to the HDL code to be assigned to this RFPD so that they have a signal value applied to the input probe at a specific time. Generating HDL code, rapid synthesis, technology mapping, layout and wiring, and programming pattern generation steps for implementing the extended design verification target HDL code in the corresponding RFPD, and generating the programming patterns from the server computer. And downloading each RFPD in the prototyping engine through the system interface port so that a circuit functionally equivalent to the design verification HDL code is implemented on the prototyping engine, and the design verification target HDL implemented on the prototyping engine. Apply the input waveform to the input of the circuit equivalent to the code and the output waveform at the output If necessary, for the output probe signal line, the signal values at a specific time period on the signal probe on the output probe are used.If the signal line on the output probe is present in the RFPD, use the IOP probe additional circuit. Including the signal value appears on the output probe line of the corresponding RFPD, and transmitting the value of the output probe line to the server computer through the system interface port and the relay module and analyzing the transmitted value. Using an additional circuit for the IOP probe to cause the signal value of the signal line on the input probe to have an input probe value transmitted from the server computer to the input probe line through the relay module and the system interface port.

Other objects and advantages of the present invention in addition to the above object will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view schematically showing a rapid prototyping apparatus according to the present invention. In the rapid prototyping apparatus according to the present invention, the prototyping engine 44 is connected to the server computer 20 via the relay module 30. In addition, within the prototyping engine 44, one or more RFPDs 12, which implement various types of digital hardware for the device, are interconnected through an external chip and act as probes 24. It is connected to the system interface port 26 through a specific chip external terminal, and again the system interface port 26 is connected to the relay module.

In the rapid prototyping method according to the present invention, the prototyping system software generates an additional circuit for the IOP probe for the input / output probe of the signal lines of the design verification target circuit which is allocated and implemented inside a specific RFPD and generated the design verification target circuit. In addition to creating an extended circuit for design verification. First, it is assumed that all of the flip-flops are D-type flip-flops when the design verification target circuit uses the flip-flops, and other cases will be described later.

In this step, the circuit designed by adding an additional circuit in the output probe mode is an extended design verification target circuit, which is a circuit made by adding an IOP-probe supplementary circuit to the design verification target circuit. In the synchronized shifting operation, the logic value of the shift register immediately before the shifting operation has the logic value of the signal lines on the output probe, and at the same time, after the shifting operation is completed, the logic values of all flip-flops in the circuit to be verified are shifted. In the input probe mode, the circuit part formed by adding the additional circuit is shifted to the shift register structure, and the flip-flops that are the input probe targets are shifted. Synchronous or asynchronous set / reset By doing this, the logic values of the flip-flops that are the input probe target are set to the input probe values, and at the same time, after the shifting operation is completed, the logic values of the remaining flip-flops in the design verification target circuit not included in the input probe target are the logic immediately before the shifting operation. The values remain the same, and in normal mode, the functional logical behavior of the circuit for design verification does not change even if the additional circuit for IOP probe is added. An example of an asynchronous circuit used to specifically illustrate this is illustrated in FIG. The clock inputs of all the flip-flops in the circuit of FIG. 2 do not physically connect the system clocks of the circuits (as opposed to logically connected in the sense of physically connected), and this is called a gated clock. . The circuit of Figure 2 is a 4-bit asynchronous binary counter, with the clock inputs of the three flip-flops except the flip-flop of the least significant bit, and the system clock of the circuit is not physically connected.

FIG. 3 is a diagram schematically showing symbols and functional functions of various D-type flip-flops, and FIG. 4 is an example of a parallel loadable shift register array structure showing an IOP probe additional circuit according to the present invention. FIG. 5 is a view schematically showing another example of the structure of a shift register array capable of parallel loading in FIG. 4, and FIG. 6 is an example of implementing the dual input D-type flip-flop of FIG. It is a figure which shows schematically. FIG. 7 (a) shows an extended design verification subject circuit in which an IOP probe additional circuit is added to enable input / output probes to all 4-bit output lines of the 4-bit asynchronous binary counter as shown in FIG.

In the output probe mode, the circuit of Fig. 7 (a) is logically 4 in length by the signal line and the double input flip-flops (PFF0, PFF1, PFF2, and PFF3 in Fig. 7 (a)) together with the circuit for design verification. And a parallel-loadable shift register array structure in which a single input of each of the dual input flip-flops is connected to each of the signal lines on the coveter so that the logic values of the signal on the coveter are parallel to the dual input flip-flop. As long as the output is probed, the output of the flip-flop (in this case, the rightmost PFF3) can be logically connected to the input / output probe as long as it exists in the shift register array structure. One input of one flip-flop present in each of the lengthwise parallel-loadable shift register array structures The output of each of the flip-flops (p0, p1, p2, and p3 in Fig. 7 (a)) is connected to the input probe line, and the output of each of the flip-flops constituting the parallel loadable shift register array is input. Dual-input flip-flop (FF0 in Fig. 7 (a)) which is replaced among respective flip-flops (FF0, FF1, FF2, and FF3 in Fig. 2) for driving each of the probe signal lines (here, y0, y1, y2, and y3). Either one is connected to one of the inputs (if the system clock is connected to the clock input of the corresponding flip-flop, so only FF0 is used here) or each flip-flop is a flip-flop with non-synchronous set and asynchronous reset. Alternatively, the flip-flop's asynchronous set input and asynchronous reset input can be controlled to set the output of this flip-flop to 0 or 1 (if no system clock is connected to the clock input of the flip-flop, follow In this case, FF1, FF2, and FF3 can be implemented. To do this, a finite state machine is additionally required. The role of the finite state machine used here is to control the asynchronous set and the asynchronous reset to occur by the signal value supplied from the shift register array only when the asynchronous set and the asynchronous reset of the flip-flop which are the input probe targets are required. For this purpose, signal lines from the shift register array, signal lines from the finite state machine, and operation mode control ( / Probe mode) A combination circuit function as shown in FIG. 7 (b) is required to control the asynchronous set and asynchronous reset of the flip-flop that is the input probe object using the signal lines. In the case of differently coding the meanings of the inputs and outputs of the combination circuit in Fig. 7 (b) (for example, by changing the meaning of 0 and 1 in FSMOut), the truth table in Fig. 7 (b) is of course. Will be different.

Figure 8 (a) shows that any one or more flip-flops in the design verification target circuit already have an asynchronous set and an asynchronous reset and a locally generated local clock without a system clock directly connected to their clock inputs. Or the gated clock is connected. In such a case, the circuit conversion as described above is performed as an additional IOP probe additional circuit including a combination control circuit driving the asynchronous set and asynchronous reset inputs while using the corresponding flip-flops that are the input probe targets as described above. In the normal mode, the functional logic property of the original design verification target circuit is not changed. FIG. 8 (b) shows such a situation, and the truth table of the combined control circuit used at this time is shown in FIG. 8 (c). Is shown. The role of the finite state machine that is driven in synchronization with the probe clock is that in the input probe mode, the asynchronous set input and the asynchronous reset input of the flip-flop that are the input probe target are configured to configure the additional circuit for the IOP probe in the specific cycle of the probe clock. Generates an asynchronous set / reset enable signal, which in this case is activated, controlled by the input probe value stored in a particular flip-flop of the shift register array, causing the input probe to occur only at the specific cycle of the probe clock. In an input probe mode, in cycles other than the specific cycle of the probe clock, an asynchronous set / reset enable signal is generated that disables an asynchronous set and an asynchronous reset of a specific flip-flop to be input probe targets (in this case, Inactive), and the extended design verification circuit is functional in normal operation mode. By generating an asynchronous set / reset enable signal that is equivalent to the original design verification target circuit (in this case, it is disabled), it drives the control circuit connected to the asynchronous set input and asynchronous reset input of the flip-flop on the input probe. do.

The expanded design verification target circuit generated by adding the IOP probe additional circuit to the design verification target circuit is converted into a programming pattern, downloaded from the server computer through the relay module and the system interface port, and then implemented in the corresponding RFPD. If a probe clock is applied to the RFPD after the RFPD is switched from normal mode to the output probe mode under the control of the prototyping system software when the output probe for the signal line on the probe is required, as long as it exists in each of the one or more shift register array structures. Signal values from the signal lines that are probe-shaped through one or more output probes connected to the output of the flip-flop are transmitted to the server computer through the system interface port and the relay module, and present in the RFPD after the application of the probe clock is terminated. Flip-Flops and Fan-Out Flip The signal values of the flops will have the same values as the signal values at the end of the normal mode immediately before the probe mode to ensure correct operation in successive normal modes. In addition, when the input probe is required, the data for the input probe is generated under the control of the prototyping system software, and then switched to the input probe mode, and then the probe clock is applied to the RFPD to exist in each of the one or more shift register array structures. Input probe data transmitted from the server computer through the relay module and the system interface port through one or more input probes logically connected to the input of one flip-flop is stored in the flip-flops present in each of the one or more shift register array structures. As the stored input probe data, the flip-flops on the input probe are synchronously or asynchronously reset and the signal lines on the input probe have the input probe signal values of the input probe data.

All RFPD products currently on the market have a large number of flip-flops inside the device, all of which are D-type flip-flops. If the flip-flops used in the circuit design use RS type, JK type, T type, etc. instead of D type, use a simple combination circuit with D type flip flop to form a functionally equivalent circuit. The equivalent circuit is implemented. Therefore, the method of generating the probe additional circuit in the probe method according to the present invention is a method that can be applied to any type of flip-flop used in the circuit.

9 is a flowchart for explaining a rapid prototyping method step by step according to an embodiment of the present invention, which is performed by the server computer 20 shown in FIG.

In step 50, the server computer 20 inputs an ASIC vendor library name and a circuit designed by the designer using the ASIC vendor library, that is, a design verification target circuit (S50). If there are signal lines requiring the probe in step 52, the server computer 20 inputs the signal lines (S52). Subsequently, the server computer 20 executes the prototyping system software so that when the prototyping engine is composed of two or more RFPDs, the design verification target circuit is divided and assigned to the RFPD, and when the prototyping engine is composed of one RFPD, the design verification is performed. The entire target circuit is allocated to the RFPD (S54). Subsequently, the server computer 20 checks whether a signal line on the coveted bed exists (S58). Then, if it is determined in step 58 that the signal line on the probe is present, in step 60, the server computer 20 executes the prototyping system software to generate the IOP-probe supplementary circuit for each RFPD in the prototyping engine. The additional circuit for IOP probe is allocated to the corresponding RFPD in the prototyping engine (S60). In step 62, the server computer 20 executes the prototyping system software to perform the verification circuit and IOP- assigned to the RFPD for each RFPD. The probe additional circuits are combined together to generate an extended design verification target circuit (S62). However, if it is determined in step 58 that there is no signal line on the coveted bed, the process proceeds to step 64, and the server computer 20 executes a prototyping system software to perform the verification target circuit allocated to this RFPD for each RFPD. To generate (S64). Subsequently, in step 66, the server computer 20 executes a prototyping system software to generate a programming pattern for implementing the extended design verification target circuit for each RFPD in the prototyping engine (S66). The computer 20 executes the prototyping system software to download programming patterns to each RFPD through the relay module 30 and the system interface port 26 to be functionally equivalent to the design verification circuit on the prototyping engine. Implement the (S68). Thereafter, in operation 70, the rapid prototyping apparatus performs a circuit verification process on the circuit implemented on the prototyping engine in the normal mode (S70). Thereafter, it is determined whether the probe needs to be performed in step 72 (S72). If it is determined that the probe needs to be performed, the procedure proceeds to step 74, and if not necessary, the procedure proceeds to step 82. In the 74th step, it is checked whether the necessary probe is an input probe or an output probe (S74). If the input probe is an input probe, the process proceeds to a 76th step and, in the case of an output probe, a 80th step. In the 80th step, the server computer 20 executes the prototyping system software when the output probe is needed, switches to the output probe mode, and applies the probe clock using the IOP probe additional circuit implemented in the RFPD. After transmitting the signal values appearing at one or more output probes in a certain time period to the server computer 20 through the system interface port 26 and the relay module 30, the output probed signals using the prototyping system software. The values are analyzed (S80). In step 76, the server computer 20 generates input probe data at the point in time when the input probe is needed (S76). Thereafter, in step 78, the server computer 20 switches to the input probe mode by executing the prototyping system software and inputs the input probe data to the input probe through the relay module 30 and the system interface 26. In step S78, the input probe is applied accordingly. On the other hand, if the above-mentioned probe is completed (S78, S80), or it is determined that the probe is not necessary, in step 82, the server computer 20 checks whether the design verification is completed (S82), and if the completion of the whole process End (S84), not complete, and proceeds to step 70.

10 is a flowchart for explaining a rapid prototyping method step by step according to another embodiment of the present invention, which is performed by the server computer 20 shown in FIG.

In step 250, the RFPD vendor library name and the design verification target HDL code are input using the server computer 20 (S250). If there are signals requiring a probe in operation 252, the input using the server computer 20 is input (S252). Subsequently, the server computer 20 executes the prototyping system software to divide and assign the design verification HDL code to the RFPD if the prototyping engine consists of two or more RFPDs, and the design verification if the prototyping engine consists of one RFPD. The entire target circuit is allocated to the RFPD (S254). Subsequently, when the server computer 20 determines that the signal on the coveter is present, the server computer 20 executes the prototyping system software in step 260 to perform the action of the IOP-probe supplementary circuit for each RFPD in the prototyping engine. After generating the HDL code representing the IOP-probe HDL supplementary code to the corresponding RFPD in the prototyping engine (S260), in step 262, the server computer 20 performs the prototyping system software for each RFPD. The HDL sub-code assigned to the RFPD and the HDL sub-code for the IOP-probe are combined together to generate the extended design verification target HDL sub-code (S262). However, if it is determined in step 258 that there is no signal on the coveted bed, the flow proceeds to step 264, in which the server computer 20 executes a prototyping system software to assign the verification target HDL code to each RFPD. To generate (S264). Subsequently, in step 266, the server computer 20 generates a programming pattern for implementing the extended design verification target HDL code for each RFPD in the prototyping engine by executing the prototyping system software (S266). The server computer 20 executes the prototyping system software, downloads a programming pattern to each RFPD through the relay module 30 and the system interface port 26, and functionally equivalents to the design verification target HDL code on the prototyping engine. To implement the circuit (S268). Thereafter, in step 270, the rapid prototyping apparatus performs a circuit verification process on the circuit implemented on the prototyping engine in the normal mode (S270). In step 272, it is determined whether the probe needs to be performed (S272). If it is determined that the probe needs to be performed, the process proceeds to step 274, and if not necessary, the process proceeds to step 282. In step 274, it is checked whether the required probe is an input probe or an output probe (S274). If the input probe is an input probe, the flow proceeds to step 276, and in the case of an output probe, the flow goes to step 280. In step 280, the server computer 20 executes the prototyping system software when the output probe is required, switches to the output probe mode, and applies the probe clock using the IOP probe additional circuit implemented in the RFPD. After transmitting the signal values appearing at one or more output probes in a certain time period to the server computer 20 through the system interface port 26 and the relay module 30, the output probed signals using the prototyping system software. The values are analyzed (S280). In operation 276, the server computer 20 generates input probe data at the point in time when the input probe is required (S276). Thereafter, in step 278, the server computer 20 switches to the input probe mode by executing the prototyping system software, and inputs the input probe data to the input probe through the relay module 30 and the system interface port 26. In step S278, the input probe is applied accordingly. On the other hand, if the above-described probe is completed (S278, S280), or if it is determined that the probe is not necessary, in step 282 the server computer 20 checks whether the design verification is completed (S282), if complete, the whole process End (S284), not complete and proceeds to step 270.

The present invention also refers to the mixed verification device incorporating the rapid prototyping device having the input / output probe function mentioned above and the simulator and the mixed verification method using the same. While the existing design verification device and method through logic emulation was only capable of fast functional verification of the design verification target circuit, the advantage of such a mixed verification device and the mixed verification method using the same is that whenever necessary on the verification time base It is possible to alternate between functional and timing verification. As a result, designers can perform fast functional verification during the verification process of the circuits they design to the point where accurate timing verification is required, and also reduce the verification time when accurate timing verification is required. It is possible to do that. Using a rapid prototyping device and a simulator capable of input and output probes of the present invention, such a high-speed functional verification and accurate timing verification can be performed several times in the verification process. That is, for example, from the beginning of verification to a specific time point A, the extended design verification target circuit in which the IOP-detection additional circuit is added to the design verification target circuit is placed on the prototyping engine of the rapid prototyping device capable of input / output probe of the present invention. The current state information of the design verification target circuit implemented on the prototyping engine using the output probe at the time point A and performing the fast functional verification by using the same. Simulation using a simulator on the server computer after reading the logical values of the flip-flops or latches) into the server computer and then using the current state information of the design verification target circuit at this point A as the initial state vector of the simulation. The timing verification proceeds from the time point A to another specific time point B. After timing verification is performed from time A to time B, the state information of the design verification target circuit at time B is transmitted from the simulator to the prototyping software of the server computer, and then transmitted to the prototyping engine through the input probe. An IOP-probe add-on circuit on the typing engine can be added to update the state information of the extended design-verification circuit, allowing fast functional verification with the rapid prototyping device from another point in time. The high speed functional verification using the prototyping engine and the accurate timing verification using the logic simulator can be repeatedly performed, which makes it possible to implement the rapid prototyping device and the input / output probe of the present invention. I / O probe method. In order to perform mixed verification as described above, performance switching between logic emulation and simulation is performed. Such operation is called execution mode switching. Such performance mode switching is performed when a specific condition is satisfied (for example, When a specific value is written twice in a specific register), such a condition is called a execution mode switching condition. The execution mode switching condition may be two or more times temporally related to the entire verification process. In such a case, logic emulation is performed at the point when the condition is satisfied in the order of the condition set first from the time set later. Run-to-simulation switching occurs from the simulation to the simulation or from the simulation to the logic emulation. To this end, it is necessary to store the execution mode switching conditions in a queue, which is called the execution mode switching condition queue.

11 is a prototyping engine having at least one output probe line connected to an input / output terminal of an RFPD and at least one RFPD having at least one input probe line, a server computer, a prototyping system software, and a relay module. A schematic illustration of a complex verification device with a rapid prototyping device and a simulator as possible.

FIG. 12 is a flowchart for explaining step by step a method of timing and functional temporal mixing verification according to an embodiment of the present invention, which is performed by the server computer 20 shown in FIG.

In step 100, after inputting the design verification target circuit and the ASIC vendor library name used in the design using the server computer, the IOP probe is used on the prototyping engine of the rapid prototyping apparatus capable of input / output probe according to the present invention. A computer program for generating a programming pattern for implementing an extended design verification target circuit to which the additional design circuit is added and downloading it to the RFPD on the prototyping engine to implement the extended design verification target circuit on the prototyping engine. In step S100, a type simulation of a design verification target circuit using a timing simulator is prepared. Initial state information for a design verification target circuit which is a timing and functional mixed verification target using the server computer 20 in step 102 (values for all memory elements (flip-flops or latches) in the circuit) By inputting the current state information of the timing simulation circuit for the timing simulator and the logic emulation circuit for the rapid prototyping device capable of the I / O probe of the present invention as the initial state information and determining the verification stop time or stop condition This is the current verification stop time or stop condition (S102). In step 104, it is determined whether to perform timing verification or functional verification with the current state information (S104). When the functional verification is performed, the flow proceeds to step 106 and the functional verification is performed until the current verification stop time or the stop condition is satisfied using the rapid prototyping apparatus capable of the input / output probe of the present invention (S106). In step 108, the execution of the verification is stopped when the current verification stop time or the stop condition is satisfied, and then it is examined whether additional verification is required. If no additional verification is required, the entire verification process is ended, and if further verification is required, the flow proceeds to step 110 (S108). In step 109, a new current verification stop time or stop condition is determined (S109). In operation 110, it is examined whether switching of the verification method is necessary (S110). If it is not necessary to switch the verification method, the flow proceeds to step 112 and it is checked whether the current verification method is a functional verification or a timing verification (S112). If the current verification method is functional verification, the flow proceeds to step 106 and if the timing verification proceeds to step 120. When timing verification is performed in step 104, the flow proceeds to step 120, and the timing verification is performed until the current verification stop time or stop condition is satisfied using a timing simulator on the server computer (S120). ). If it is necessary to switch the verification method in operation 110, the process proceeds to operation 130 to determine whether the verification conversion is a transition from a timing verification to a functional verification or a transition from a functional verification to a timing verification (S130). If the verification transition is a transition from timing verification to functional verification, the flow proceeds to step 132 in which the current state information of the design verification target circuit at the current verification stop point obtained through timing simulation on the server computer is implemented on the prototyping engine. In step S132, the input probe is performed on the RFPDs on the prototyping engine of the rapid prototyping apparatus capable of the input / output probe of the present invention so that the extended design verification target circuit may have the same (S132). If the verification transition is a transition from functional verification to timing verification, the flow proceeds to step 134 where the output probe for the extended design verification target circuit implemented on the prototyping engine of the rapid prototyping apparatus capable of input / output probe of the present invention is obtained. The prototype of the rapid prototyping device capable of input / output probes according to the present invention so that the current state information of the design verification target circuit obtained by the current verification stop can be equally possessed by the design verification target circuit performed by the timing simulator on the server computer. The output probe is performed on the RFPDs on the typing engine and the process proceeds to step 120 (S134). FIG. 13 is a flowchart for explaining step by step a simulation and emulation mixing verification method according to another embodiment of the present invention, which is performed by the server computer 20 shown in FIG.

After inputting the design verification target HDL code and RFPD vendor library name using the server computer in step 300, the IOP probe additional circuit on the prototyping engine of the rapid prototyping apparatus capable of input / output probe of the present invention using the same. An extended design by generating a programming pattern for implementing the extended design-verified HDL code with the added HDL code (called the HDL supplementary code for IOP-probe) representing the behavior of the code and downloading it to the RFPD on the prototyping engine. While the verification target HDL code is implemented on the prototyping engine, the server computer prepares to perform simulation of the design verification target HDL code using a simulator (S300). In step 302, using the server computer 20, input the initial state information of the design-verification target HDL code to be the simulation and emulation mixed verification target, the simulation HDL code for the simulator and the rapid prototyping of the input-output probe of the present invention The current state information of the HDL code for logic emulation for the typing device is made equal to the initial state information, and the verification intermediate stop time or stop condition is determined to be the current verification stop time or stop condition (S302). In step 304, it is determined whether to perform simulation or emulation with the current state information (S304). When the emulation is performed, the process proceeds to step 306 and the verification is performed until the current verification stop time or the stop condition is satisfied using the rapid prototyping apparatus capable of the input / output probe of the present invention (S306). In step 308, the execution of the verification is stopped when the current verification stop time or the stop condition is satisfied, and then it is examined whether additional verification is required. If no additional verification is required, the entire verification process is ended, and if further verification is required, the process proceeds to step 310 (S308). In step 309, a new current verification stop time or stop condition is determined (S309). In operation 310, it is examined whether switching of the verification method is necessary (S310). If it is not necessary to switch the verification method, the flow proceeds to step 312 to determine whether the current verification method is emulation or simulation (S312). If the current verification method is emulation, the method proceeds to step 306 and, if the simulation, proceeds to step 320. If the simulation is performed in step 304, the process proceeds to step 320, and the verification is performed until the current verification stop time or stop condition is satisfied using the simulator on the server computer (S320). If it is necessary to switch the verification method in operation 310, the flow proceeds to operation 330 to determine whether the verification conversion is a conversion from simulation to emulation or a conversion from emulation to simulation (S330). If the verification transition is a transition from simulation to emulation, the flow proceeds to step 332 in which the extended design implemented on the prototyping engine by presenting the current state information of the design target HDL code at the current verification stop point obtained through the simulation on the server computer. In order to have the same HDL code to be verified, input probes are performed on the RFPDs on the prototyping engine of the rapid prototyping apparatus capable of input / output probes of the present invention, and the flow proceeds to step 306 (S332). If the verification transition is a transition from emulation to simulation, the flow proceeds to step 334 and obtained through the output probe for the extended design verification target HDL code implemented on the prototyping engine of the rapid prototyping apparatus capable of input / output probe of the present invention. Prototyping of the rapid prototyping device capable of input / output probe of the present invention so that the current verification information of the design verification target HDL code at the time of the current verification stop has the same design verification target HDL code being performed by the simulator on the server computer. The output probe is performed on the RFPDs on the engine and the flow proceeds to step 320 (S334).

As described above, the rapid prototyping device and the probe method capable of input / output probes according to the present invention can quickly input / output all signal lines on a circuit or all signals on an HDL code for efficient and rapid design verification of a designed digital circuit. There is an advantage in providing a rapid prototyping device that can be probed and an automated verification method using the same. In addition, by using a rapid prototyping device that enables such an input / output probe as a simulator, it provides a timing and functional mixed verification device that enables high-speed functional verification and accurate timing verification together with an automated verification method using the same. There is an advantage.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (22)

In the rapid prototyping device having a prototyping engine, a server computer, and a relay module, The prototyping engine comprises one or more RFPDs, The at least one RFPD has at least one output probe line and at least one input probe line connected to the input and output terminals of the RFPD, The server computer generates an HDL code representing the behavior of an IOP-probe supplementary circuit or an IOP-probe supplementary circuit for one or more RFPDs in the engine, and adds an IOP-probe supplementary circuit to a design verification target circuit or an HDL code. Or generating a programming pattern for one or more RFPDs in the engine by adding an HDL code representing the behavior of an IOP-probe supplementary circuit, downloading the programming pattern to the corresponding RFPD, and then designing the target circuit or HDL code for prototyping. To be implemented on the engine, And the relay module is responsible for an interface between the server computer and the prototyping engine. The method of claim 1, The rapid prototyping device further comprises an ASIC vendor library, A rapid prototyping device, characterized in that the HDL code representing the behavior of the IOP-probe supplementary circuit or the IOP-probe supplementary circuit is automatically generated by executing prototyping system software by the server computer. The method of claim 2, Rapid prototyping device, characterized in that the prototyping system software includes an IOP-probe add-on circuit / HDL code generator for automatic generation of HDL code representing the behavior of the IOP-probe add-on circuit or the IOP-probe add-on circuit. . The method of claim 3, wherein The extended design verification circuit completed by adding the IOP-probe supplementary circuit to the design verification circuit is a shift register structure that can be loaded in parallel in the output probe mode by adding the additional circuit. Synchronous shifting operation is performed by parallel loading just before this shifting operation, so that the logic value of this shift register has the logic value of the signal lines to be output probe, and at the same time, all the flip-flops in the design verification circuit after the shifting operation is completed. These logic values are maintained to be the same as the logic values immediately before the shifting operation. In the input probe mode, the circuit portion formed by adding an additional circuit has a shift register structure that can be loaded in a serial manner to perform the shifting operation. To use the input coveter Synchronous or asynchronous set-up and reset operations on the flip-flops make the logic values of the flip-flops to be input probes as input probes, and at the same time, the design verification target circuits not included in the input probes after the shifting operation is completed. The logic values of the remaining flip-flops in the circuit are maintained to be the same as the logic values immediately before the shifting operation, and in the normal mode, the functional logic properties of the circuit to be verified are not modified even if an additional circuit for IOP probe is added. Rapid prototyping device, characterized in that. The method of claim 3, wherein When the design verification target is dictated by the HDL code, the extended HDL code that is completed by adding the HDL additional code representing the behavior of the IOP-probe supplementary circuit to the design verification HDL code is additional HDL code in the output probe mode. The HDL portion formed by adding the code expresses the shift register behavior that can be loaded in parallel, so that the signal line of the register HDL code in the HDL code expressing the shift register behavior immediately before the shifting operation is performed. It has the signal values that are the output probe targets by parallel load and at the same time, after the shifting operation is completed, the signal values of the signals of the HDL code expressing the flip-flops in the HDL code to be verified are immediately before the shifting operation. It remains the same as the signal value of, but in the input probe mode The HDL code part formed by adding the HDL code has a shift register structure that can be loaded in a serial manner to perform a shifting operation synchronized with the probe clock. Flip-flops of the HDL code that are the input probe targets by using the shifting operation Synchronous or asynchronous set-up and reset of signals in HDL code that express behaviors cause the logic values of the signals that are the input probe targets to be input probe values, and at the same time they are not included in the input probe targets after the shifting operation is completed. While the signal values of the remaining HDL signals representing the flip-flop behavior of the HDL code to be verified are maintained to be the same as the signal values immediately before the shifting operation, in the normal mode, the design verification HDL is performed even if an additional circuit for IOP probe is added. To construct HDL code that does not alter the behavior of the code Is rapid prototyping apparatus. The method according to claim 4 or 5, An extended design verification circuit with an IOP-probe supplementary circuit is logically connected by the signal boards and double input flip-flops in the probe probe with the design verification circuit assigned to this RFPD in the probe probe. The shift register array structure having the same length as the parallel load capable of parallel loading or the length of the shift register array structure having the longest parallel load having the same length as the positive integer multiple of the remaining parallel loadable shift register array structures having different lengths. At the same time, one input of each of the dual input flip-flops is connected to the signal line on the tamper, so that each of the signal line on the tamper can be loaded into the dual input flip flop in parallel, and at least one shift register array structure at the time of output teaming. The output of one flip-flop present in each of these RFPDs is 1 One input of the flip-flop is logically connected to one or more input probes of the RFPD in each of the shift register array structures capable of one or more parallel loads. The output of each of the flip-flops of the shift register array capable of loading the at least one parallel load by inputting the probe value into the shift register in a serial manner by a shifting operation synchronized with the probe clock is provided. If the system clock is connected to the clock input of each flip-flop that drives each of them, it is connected to one input of each dual input flip-flop replacing each of the flip-flops, or each of the input probe target signal lines For each flip-flop you drive, click the corresponding flip-flop If no system clock is physically connected to the input, replace the flip-flop with a flip-flop with an asynchronous set and an asynchronous reset to control the flip-flop's asynchronous set input and asynchronous reset input to zero the output of this flip-flop. Or can be set to 1 to implement a rapid prototyping device. The method according to claim 4 to 5, It is possible to configure the shift register array of the IOP probe additional circuit by connecting the dual input flip flops in series or the HDL code of the shift register array of the HDL code representing the behavior of the IOP probe additional circuit. Rapid prototyping device, characterized in that consisting of HDL code representing the behavior of the serial connection. The method according to claim 4 or 5 or 6, In probe mode, the same probe clock is applied to all clock inputs of the dual input flip flops of the shift register array of the IOP probe, and the control of the probe clock and system clock is carried out to the server computer through the relay module. Rapid prototyping device, characterized in that. In a design verification target circuit that is an input probe target, one or more flip-flops in which a locally generated local clock or a gated clock is input without a system clock being integrated into the clock input of one or more flip-flops present in the design verification target circuit. Design and test circuit for input probe additional circuit having finite state and control circuit that generates and outputs serial load-enabled shift register array structure and asynchronous set / reset enable signal for a specific time of probe clock. In addition, in the probe input mode, an input probe value is sequentially loaded from the outside through the serial loading synchronized to the probe clock, and then the flip of the shift register array is performed. Loaded on each of the flops Among the input probe values, the input probe value for the flip-flop that is the input probe target, the asynchronous set / reset activation output value for the flip-flop that is the input probe target generated from the finite state machine, and the operation mode applied from the outside. The control value generates signal values for controlling the asynchronous set and asynchronous reset of the flip-flop through the control circuit so that the asynchronous set input and the asynchronous reset input of the flip-flop to be probed are controlled by the signal values in the input probe mode. Input probe, and in the normal operation mode, the extended design verification target circuit generated by adding the input probe additional circuit to the original design verification target circuit is functionally equivalent to the original design verification target circuit. Input probe method that enables the operation. The method of claim 6, A rapid prototyping device, characterized in that the output probe and the input probe exist as separate independent unidirectional probes. The method of claim 6, Rapid prototyping device, characterized in that the output probe and the input probe is a bidirectional probe combined with each other. The method according to any one of claims 1 to 2, Rapid prototyping device, characterized in that the component in the prototyping engine is a field programmable gate array. The method according to any one of claims 1 to 2, A rapid prototyping device, characterized in that the component in the prototyping engine is a complex programmable logic element. Inputting the design verification target circuit and the ASIC vendor library name into the server computer; Inputting the signal line on the coveter existing in the design verification target circuit to the server computer; If the input circuit is divided into two or more RFPDs when the RFPD on the prototyping engine is 2 or more, and the prototyping engine consists of one RFPD, the entire design verification circuit is allocated to the RFPD, and the specific RFPD on the prototyping engine is allocated. Determining whether each of the probe signal lines is an input probe signal line or an output probe signal line if the probe signal lines have been allocated to the RFPD for the circuit assigned to the RFPD; Verification assigned to this RFPD so that signal values at specific time zones on the signal probe on the output probe appear only for a certain time on the output probe and that signal lines on the input probe have signal values applied to the input probe at specific time zones. Generating an additional design verification target circuit by additionally adding an additional circuit for IOP-probe to the target circuit, and generating technology mapping, layout and wiring, and programming pattern for implementing the extended design verification target circuit in the corresponding RFPD. Steps, Downloading the generated programming patterns from the server computer to each RFPD in the prototyping engine through the relay module and the system interface port so that a circuit equivalent to the design verification target circuit and a functionally equivalent circuit in the normal mode can be implemented on the prototyping engine; , Apply the input waveform to the input of the design verification target circuit implemented on the prototyping engine and the functionally equivalent circuit in the normal mode, and observe the output waveform at the output.If necessary, the signal lines on the output probe for the output probe signal line One or more input / output signals in which signal values of the signal lines on the output probe serve as output probe lines of the corresponding RFPD by using the IOP probe additional circuit when the signal values on the output probe exist in the RFPD. Making the pins appear sequentially, And analyzing the transmitted value by transmitting the value of the output probe line to the server computer through the system interface port and the relay module. For the input probe signal line, the signal of the signal line on the input probe using the IOP probe additional circuit. And a value having an input probe value sequentially transmitted from a server computer to one or more input / output pins corresponding to the input probe line of the corresponding RFPD through a relay module and a system interface port. Inputting the design verification HDL code and RFPD vendor library name into the server computer; Inputting the coveted signals present in the HDL code for design verification to the server computer; If the inputted HDL code is divided into two or more RFPDs if the RFPD on the prototyping engine is 2 or more, and the prototyping engine consists of one RFPD, the entire HDL code to be verified is assigned to the RFPD. Determining whether each of the signals on the probe is an input probe signal or an output probe signal when the signals on the probe are allocated to the HDL code assigned to the specific RFPD; Verification assigned to this RFPD so that signal values at specific time zones in signals on the output probe will only appear on the output probe for a certain period of time and that signals on the input probe have signal values applied to the input probe at specific time zones. Generating an extended design verification target HDL code by additionally adding an HDL code to a probe part expressing the behavior of the IOP probe additional circuit to the target HDL code; Quick synthesis, technology mapping, layout and routing, and programming pattern generation steps for implementing this extended design-verified HDL code in the corresponding RFPD; The generated programming patterns are downloaded from the server computer through the relay module and the system interface port to each RFPD in the prototyping engine so that a circuit equivalent to the design-verified HDL code and the functionally equivalent circuit in the normal mode are implemented on the prototyping engine. Wow, The input waveform is applied to the input of the circuit which is functionally equivalent in the normal mode with the design verification target HDL code implemented on the prototyping engine, and the output waveform is observed at the output. One or more input / output signals whose signal values on the output probe correspond to the output probe lines of the corresponding RFPD by using the IOP probe additional circuit when the signal lines on the output probe exist in the RFPD. Making the pins appear sequentially, And analyzing the transmitted value by transmitting the value of the output probe line to the server computer through the system interface port and the relay module. For the input probe signal line, the signal of the signal line on the input probe using the IOP probe additional circuit. And having an input probe value sequentially transmitted from a server computer to one or more input / output pins corresponding to the input probe line of the corresponding RFPD through a relay module and a system interface port. A prototyping engine with at least one output probe connected to the input and output terminals of the RFPD and at least one RFPD with at least one input probe, a server computer, and a prototyping system software that can automatically generate additional circuits for the IOP probe. , A complex verification device having a relay module and a rapid prototyping device capable of input / output probe and simulator. Logic emulation method for verifying by using one or more RFPD which implements extended design verification target circuit with IOP probe additional circuit added to design verification target circuit and simulation method of verifying design verification target circuit using simulator Complex verification method that performs alternating one or more times as necessary by exchanging current status information between emulator and simulator. The method of claim 17, Complex verification method using IOP probe-based input / output probe method for exchanging current status information between logic emulator and simulator. Enter the design verification target circuit and the name of the ASIC vendor library used in the design using the server computer, and use it to expand the IOP-probe supplementary circuit on the prototyping engine of the rapid prototyping device. A programming pattern for implementing the designed design verification target circuit is generated and downloaded to the RFPD on the prototyping engine, so that the extended design verification target circuit is implemented on the prototyping engine, and the design verification target using the simulator on the server computer Preparing to perform a simulation of the circuit, By using the server computer, input the starting state information of the design verification target circuit to be mixed verification target, and the current state information of the circuit for the simulation for the simulator and the logic emulation circuit for the rapid prototyping device capable of input / output probe. It determines the current execution mode by deciding whether to perform the simulation or the emulation for the first time, and determine the execution mode switching conditions between simulation and logic emulation in the execution mode switching condition queue. Storing in chronological order, Verifying the design by logic emulation or simulation in a manner appropriate to the current execution mode; The execution of the current design verification method is stopped when the first condition in time in the execution mode switching conditions is satisfied, the current satisfied execution mode switching condition is removed from the execution mode switching queue, and the current execution mode is changed to another execution mode. Verification method that has been performed up to now and other design verification methods through the current state information exchange using the IOP-probe supplementary circuit implemented in the rapid prototyping device that performs logic emulation Successive design validations, and And performing the above-described design verification method alternately one or more times between the logic emulation and simulation until the execution mode switching queue becomes empty. Using the server computer, enter the HDL code and RFPD vendor library name for design verification, and use it to expand the IOP-probe HDL additional code on the prototyping engine of the rapid prototyping device. Generate a programming pattern for implementing the HDL code to be verified and download it to the RFPD on the prototyping engine to ensure that the extended design verification HDL code is implemented on the prototyping engine. Preparing to perform the simulation of the HDL code, HDL code for simulation and HDL code for logic emulation for a rapid prototyping device capable of input and output probes by inputting the initial state information of the design-proven target HDL code that is subject to mixed timing and functional verification using a server computer. Determine the current execution mode by determining whether the current state of the data is the same as the initial state information and whether the first execution is simulated or emulated, and the execution mode switching conditions between simulation and logic emulation in the execution process. Storing the chronological order in the execution mode switching condition queue; Verifying the design by logic emulation or simulation in a manner appropriate to the current execution mode; The execution of the current design verification method is stopped when the first condition in time in the execution mode switching conditions is satisfied, the current satisfied execution mode switching condition is removed from the execution mode switching queue, and the current execution mode is changed to another execution mode. Verification method that has been performed up to now and other design verification methods through the current state information exchange using the IOP-probe supplementary circuit implemented in the rapid prototyping device that performs logic emulation Successive design validations, and And performing the above-described design verification method alternately one or more times between the logic emulation and simulation until the execution mode switching queue becomes empty. Enter the design verification target circuit and the name of the ASIC vendor library used in the design using the server computer, and use it to expand the IOP-probe supplementary circuit on the prototyping engine of the rapid prototyping device. A programming pattern for implementing the designed design verification target circuit is generated and downloaded to the RFPD on the prototyping engine, so that the extended design verification target circuit is implemented on the prototyping engine, and the design verification target using the simulator on the server computer Preparing to perform timing simulation of the circuit, The current state of the circuit for timing simulation and the logic emulation circuit for a rapid prototyping device capable of input / output probes by inputting the initial state information of the design verification target circuit to be the timing and functional mixture verification using a computer for the server Making the status information equal to the initial status information, determining the verification stop time or stop condition and making it the current verification stop or stop condition; Determining whether to perform timing verification or functional verification with current state information, and using a rapid prototyping device capable of input / output probes, until the current verification stop or stop condition is satisfied. To proceed with the verification, Stopping the performance of the verification at the point where the current verification stop or stop condition is satisfied, and then examining whether additional verification is required, and determining a new current verification stop or stop condition; Examining whether the verification method needs to be switched, examining whether the current verification method is functional verification or timing verification; Performing timing verification using the simulator on the server computer until the current verification stop or the stop condition is satisfied; Examining whether the verification transition is a transition from a timing verification to a functional verification or a transition from a functional verification to a timing verification; Rapid prototyping device capable of input / output probes so that the extended design verification target circuit implemented on the prototyping engine has the same current status information of the design verification target circuit obtained by timing simulation on the server computer. Performing input probes on the RFPDs on the prototyping engine of The current state of the design verification target circuit at the time of the verification stop obtained by the output probe of the extended design verification target circuit implemented on the prototyping engine of the rapid prototyping device capable of input / output probes is obtained by a simulator on the server computer. And performing an output probe on the RFPDs on the prototyping engine of the rapid prototyping device capable of input / output probes to have the same design verification target circuit being performed. Using the server computer, enter the HDL code and RFPD vendor library name for design verification, and use it to expand the IOP-probe HDL additional code on the prototyping engine of the rapid prototyping device. Generate a programming pattern for implementing the HDL code to be verified and download it to the RFPD on the prototyping engine to ensure that the extended design verification HDL code is implemented on the prototyping engine. Preparing to perform the simulation of the HDL code, HDL code for simulation and HDL code for logic emulation for a rapid prototyping device capable of input and output probes by inputting the initial state information of the design-proven target HDL code that is subject to mixed timing and functional verification using a server computer. Making the current status information of the same as the initial status information and determining the verification stop time or stop condition and making it as the current verification stop time or stop condition, Determining whether to perform simulation or emulation with current state information, and emulating until the current verification stop or stop condition is met by using a rapid prototyping device capable of input / output probe. Wow, Stopping the performance of the verification at the point where the current verification stop or stop condition is satisfied, and then examining whether additional verification is required, and determining a new current verification stop or stop condition; Investigating whether the verification method needs to be switched, investigating whether the current verification method is emulation or simulation, Using the simulator on the server computer to perform the simulation until the current verification stop or stop condition is satisfied; Examining whether the verification transition is from simulation to emulation or from emulation to simulation, Rapid prototyping with I / O probing to ensure that the current state of the design verification target HDL code obtained by simulation on the server computer is identical to the extended design verification target HDL code implemented on the prototyping engine. Performing an input probe on the RFPDs on the prototyping engine of the device, On the server computer, the current state of the design verification target HDL code obtained at the time of stopping verification obtained through the output probe for the extended design verification target HDL code implemented on the prototyping engine of the rapid prototyping device capable of input / output probe And performing an output probe on the RFPDs on the prototyping engine of the rapid prototyping device capable of input / output probes so that the design-verification target HDL code being performed by the same can have the same.