KR20000057899A - Shallow trench isolation planarization using self aligned isotropic etch - Google Patents

Abstract

PURPOSE: An improved planarization method for a shallow trench isolation structure is provided for circuit with arbitrary density. CONSTITUTION: In a method for forming an isolation structure, a semiconductor substrate(100) with a plurality of trenches(101) downwardly formed thereon is provided. In addition, a non-etched surface(108) of the substrate(100) between the adjacent trenches(101) is covered with a nitride layer(102). Next, a conformal insulating filler(103) is deposited on the substrate(100) and a thinner conformal etching barrier(106) is then formed on the insulating filler(103). Subsequently, the etching barrier(106) above the non-etched surface(108) is removed so that the insulating filler(103) is partially exposed. Next, the exposed insulating filler(103) is isotropically etched, and then the remaining etching barrier(106) is selectively etched. Finally, a resultant surface is planarized by a chemical mechanical polishing technique. Preferably, the selective etch process for the etching barrier(106) may be performed with a higher etch rate of the etching barrier(106) to the insulating filler(103).

Description

Isolation structure formation method {SHALLOW TRENCH ISOLATION PLANARIZATION USING SELF ALIGNED ISOTROPIC ETCH}

TECHNICAL FIELD The present invention generally relates to the field of semiconductor device manufacturing, and more particularly, to a planarization method of an isolation structure in an integrated circuit.

Chemical-mechanical polishing (CMP) is used to planarize oxides or other materials used to fill shallow trenches formed for isolation. The most common method used for CMP in semiconductor device fabrication is to attach a semiconductor wafer to a carrier (which may or may not be rotated) through a mounting pad and then expose the exposed surface of the wafer to a polishing pad (rotating or non-rotating platen) And is polished by contact with the substrate). Thus, mechanical wear between the wafer surface and the polishing pad causes the wafer surface to be polished. Slurry may be introduced between the wafer surface and the polishing pad to facilitate polishing and remove any particles liberated in this process. The slurry can more easily polish the wafer by interacting with the wafer surface, and any material liberated from the wafer during this polishing step will be taken away by the excess slurry.

In order to achieve proper isolation between devices in an integrated circuit, a technique known as shallow trench isolation (STI) is used. In this technique, after forming a shallow trench in the silicon surface, the trench is filled with an insulating material, which is usually made of deposited oxide. This deposited oxide has conformal properties to follow the contours of the silicon surface so that an oxide film of the same thickness is formed on the silicon surface and in the trench in which the devices are to be manufactured.

To achieve the planar surface as a result of device fabrication, CMP is typically used to remove oxides formed on silicon surfaces that will contain devices while leaving oxide in the trench. These silicon surfaces are unevenly distributed throughout the integrated circuit, requiring a process that can control the range of integrated circuit density to form a uniform planar surface. Significant dishing in regions containing large trenches due to the non-uniform distribution of silicon surfaces throughout this integrated circuit and the typical low selectivity (of oxide to nitride) of most CMP silica slurries used in oxide polishing. Damage to separated small silicon surfaces and incomplete removal of oxides from large silicon regions or arrays can occur. Dummy silicon surfaces can be used to reduce this variation, but variations in the thickness of the oxides filled in the die across the wafer are still very high. Typically, to overcome this change, a patterned pattern is used to etch back oxide on the silicon surface to reduce the pattern density on the appearance, leaving only the excess oxide around the edge of the silicon surface easily removed using CMP during short term polishing. Etch back is used. This method adds significant cost to the fabrication of integrated circuits due to the addition of photolithographic patterning levels. Thus, there is a need for a method to overcome the limitations of CMP without increasing the cost for planarization of the STI and without increasing the complexity of the patterned etch back. The present invention does not require a patterning step and provides a method by which arbitrary circuit density can be adjusted.

The present invention includes a method of forming a planar isolation structure for use in an integrated circuit.

One embodiment of the present invention provides a method of forming an isolation structure in a semiconductor substrate, the steps of etching trenches in the substrate to form regions of the substrate that are substantially etched away between the trenches and substantially filling the trenches. Depositing a filler having a top surface, forming an etch barrier on the top surface of the filler, and removing portions of the etch barrier located on the substantially unetched substrate region; Exposing the mold, removing the exposed portions of the filler, and planarizing the filler. Preferably, removing the etch barrier uses a selective etch process, the selective etch process having an etch rate of the etch barrier higher than the filler etch rate.

An advantage of the present invention is the formation of planar isolation structures for arbitrary circuit densities with reduced man-hours.

The above and other advantages of the present invention will be readily appreciated by those skilled in the art by reference to the specification in conjunction with the accompanying drawings.

1 is a cross-sectional view of a silicon wafer showing shallow trenches and trench fill oxide structures.

2A-2E are cross-sectional views illustrating one embodiment of the present invention.

3 is a flow diagram illustrating a method of one embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: silicon substrate

101: trench

103: filling material

106: conformal etch barrier

The present invention will now be described with reference to FIGS. 1, 2A-2E and 3. Those skilled in the art will appreciate that the advantages of the present invention can be applied to other structures that require planarization of the film.

The silicon substrate 100 may be monocrystalline silicon and an epitaxial silicon layer formed on the single crystal substrate having a plurality of trenches 101 is shown in FIG. 1. The nitride film 102 is formed and patterned to etch silicon to form the trench 101. The well-deposited film also serves to protect the unetched silicon surface 108 from which the devices will be fabricated. A conformal insulating filler 103 is formed to fill the trenches and to provide insulation between any of the devices that will be fabricated later on the unetched silicon surface 108. This conformal insulating filler 103 may be chemical vapor deposited (CVD) silicon oxide, PECVD TEOS, HDP oxide, oxynitride or any insulating material having the same properties. The phase shown in FIG. 1 is formed due to the conformal properties of the filler 103. Filler 108 fills trenches 105 (typically about 0.3-0.6 μm deep), but will also form a film on the unetched silicon surface 108 that is the same thickness as the film thickness in trench 105. In areas where the non-etched silicon surfaces 104 are closely disposed, the filler will form a relatively flat surface throughout the silicon surfaces. In the region where the unetched silicon surfaces 107 are separated, the filler 103 will conform to the phase of the unetched silicon surface 108 and the trench 101. In one embodiment of the present invention, CVD oxide is used as the filler 103. For this embodiment, selective densification of the filler 103 is done by annealing the oxide within a temperature range of 500 ° C. to 1500 ° C. in an atmosphere containing oxygen, nitrogen, argon or any combination of these gases.

In step 302 of FIG. 3, a thin conformal etch barrier is formed on the surface of filler 103 that is resistant to the isotropic etchant of filler 103. This thin conformal etch barrier 106 is shown in FIG. 2A. In one embodiment of the present invention, for the filler 103 comprising silicon dioxide, the etch barrier 106 may be a silicon nitride, polycrystalline silicon, amorphous silicon, metal, polymer (e.g., paralene ^™ ) of 50-4000 microns film. Or any compound thereof. In step 304, the etch barrier 106 on the silicon surfaces 104, 107 is removed using CMP or other suitable technique. The resulting structure is shown in FIG. 2B. It is desirable that only the minimum amount of filler 103 below the etch barrier 106 be removed at this stage. Typical selectivity of CMP slurries is 1: 1 for nitrides and oxides respectively and 10: 1 for polysilicon and oxides respectively.

In step 306, the filler 103 is isotropically etched. In another embodiment of the present invention, the filler 103 may be isotropically removed by wet chemical etching, dry plasma-based etching, or any combination thereof. 2C shows the structure after anisotropic etching. In one embodiment of the present invention, dilute HF solution (buffered or unbuffered) may be used as an etchant for CVD silicon oxide filler 103 and silicon nitride or polycrystalline silicon etch barrier 106. The upper and lower limits of the HF concentration will be determined by the reaction rate in the low concentration range and the isotropy of the etchant to the filler in the high concentration range. The actual concentration range of the HF diluent is 0.25% to 15%, but the concentration is not limited to this range. In other embodiments, isotropic etching may be performed using plasma-based etching if CVD silicon oxide filler 103 and silicon nitride or polysilicon etch barrier 106 are used. In this case, the etching can be done with a plasma etchant using a fluorocarbon based chemical (eg, CHF ₂ / CF ₄ / Ar, C ₂ F ₆ , C ₃ F ₈ , or CHF ₃ ).

Step 308 includes removing the remaining etch barrier 106 using wet chemical etching or plasma-based etching as an optional step. If step 308 is not performed, the remaining portions of structure 106 will be removed in CMP step 310. However, this may cause scratching or contamination. In another embodiment, hot phosphoric acid will be a suitable wet chemical etchant for CVD silicon oxide fillers and polysilicon etch barriers. In both cases, the etching process must remove the etch barrier without removing a significant amount of filler. The resulting structure is shown in FIG. 2D as a result of this step.

In step 310, the remaining filler surface covering silicon surface 108 is removed by planarizing the remaining wafer surface using CMP. The resulting structure is shown in FIG. 2E. This allows the use of standard processing techniques to complete the integrated circuit.

Although the present invention has been described and illustrated only with respect to the above embodiments, the present invention is not limited to these embodiments. Those skilled in the art will recognize that various modifications and variations of the present invention may be made by reference to the present specification. Therefore, the appended claims should be construed broadly as including all such modifications.

Claims (34)

In the method of forming an isolation structure on a semiconductor substrate, Etching trenches in the substrate to form an area of the substrate that is not actually etched between the trenches; Depositing a conformal filler having a top surface substantially filling the trenches; Forming a conformal etch barrier on the top surface of the conformal filler; Removing portions of the conformal etch barrier located on the substrate region that are not actually etched to expose portions of the conformal filler; Removing the exposed portions of the conformal filler using isotropic etching; Polishing the conformal filler using chemical mechanical polishing Isolation structure forming method comprising a. The method of claim 1, further comprising removing the conformal etch barrier using a selective etch process, wherein the selective etch process forms an isolation structure having an etch rate of the conformal etch barrier higher than the conformal filler etch rate. Way. The method of claim 1, wherein the conformal filler comprises a material selected from the group consisting of silicon oxide and silicon oxynitride. The method of claim 1, wherein the conformal etch barrier comprises a material selected from the group consisting of silicon nitride, polycrystalline silicon, and amorphous silicon. The method of claim 1, wherein the conformal etch barrier comprises a metal. The method of claim 1, wherein the conformal etch barrier comprises a polymer. 2. The method of claim 1, wherein removing the portions of the conformal etch barrier located on the substantially unetched region of the substrate comprises chemical mechanical polishing. The method of claim 1, wherein removing the portions of the conformal etch barrier located on the substantially unetched region of the substrate comprises dry plasma etching. The method of claim 1, wherein removing the portions of the conformal etch barrier located on the substantially unetched region of the substrate comprises a wet chemical etch. The method of claim 1, wherein removing the exposed portions of the conformal filler comprises a wet chemical isotropic etch. The method of claim 1, wherein removing the exposed portions of the conformal filler comprises a dry plasma isotropic etch. In the method of forming an isolation structure on a semiconductor substrate, Etching trenches in the substrate to form an area of the substrate that is not actually etched between the trenches; Depositing a filler having a top surface substantially filling the trenches; Forming an etch barrier on the top surface of the filler; Exposing portions of the filler material by removing portions of the etch barrier positioned on the substrate region that are not actually etched; Removing the exposed portions of the filler; Planarizing the filler Isolation structure forming method comprising a. 13. The method of claim 12, further comprising removing the etch barrier using a selective etch process, wherein the selective etch process has an etch rate of the etch barrier higher than a filler etch rate. The method of claim 12, wherein the filler comprises a material selected from the group consisting of silicon oxide and silicon oxynitride. 13. The method of claim 12 wherein the etch barrier comprises a material selected from the group consisting of silicon nitride, polycrystalline silicon and amorphous silicon. 13. The method of claim 12 wherein the etch barrier comprises a metal. 13. The method of claim 12 wherein the etch barrier comprises a polymer. 13. The method of claim 12 wherein the step of removing portions of the etch barrier located on the substantially unetched region of the substrate comprises chemical mechanical polishing. 13. The method of claim 12 wherein the step of removing portions of the etch barrier located on the substantially unetched region of the substrate comprises dry plasma etching. 13. The method of claim 12, wherein removing portions of the etch barrier that are located on the substantially unetched region of the substrate include wet chemical etching. 13. The method of claim 12 wherein the step of removing the exposed portions of the filler comprises a wet chemical isotropic etch. The method of claim 12, wherein removing the exposed portions of the filler comprises a dry plasma isotropic etch. 13. The method of claim 12, wherein said planarizing of said filler comprises chemical mechanical polishing. In the method of forming an isolation structure on a semiconductor substrate, Etching trenches in the substrate to form an area of the substrate that is not actually etched between the trenches; Depositing a conformal filler that substantially fills the trenches, the conformal filler having a top surface, a raised area, and a settling area; Forming a conformal etch barrier on the top surface of the conformal filler; Exposing portions of the conformal filler by removing portions of the conformal etch barrier in the raised region while leaving portions of the conformal etch barrier in the settlement region; Removing the exposed portions of the conformal filler using isotropic etching; Polishing the conformal filler using chemical mechanical polishing Isolation structure forming method comprising a. 25. The method of claim 24, further comprising removing the conformal etch barrier using a selective etch process, wherein the selective etch process forms an isolation structure having an etch rate of the conformal etch barrier higher than the conformal filler etch rate. Way. 25. The method of claim 24, wherein the conformal filler comprises a material selected from the group consisting of silicon oxide and silicon oxynitride. 25. The method of claim 24, wherein the conformal etch barrier comprises a material selected from the group consisting of silicon nitride, polycrystalline silicon, and amorphous silicon. 25. The method of claim 24, wherein the conformal etch barrier comprises a metal. 25. The method of claim 24, wherein the conformal etch barrier comprises a polymer. 25. The method of claim 24, wherein removing the portions of the conformal etch barrier of the raised region comprises chemical mechanical polishing. 25. The method of claim 24, wherein removing the portions of the conformal etch barrier of the raised region comprises dry plasma etching. 25. The method of claim 24, wherein removing portions of the conformal etch barrier in the raised region comprises wet chemical etching. 25. The method of claim 24, wherein removing the exposed portions of the conformal filler comprises a wet chemical isotropic etch. 25. The method of claim 24, wherein removing the exposed portions of the conformal filler comprises a dry plasma isotropic etch.