KR20000050284A - Semiconductor memory device - Google Patents

Abstract

The semiconductor memory device disclosed herein may include a first memory bank in which data of a first group is output, a second memory bank in which a second group of data is sensed when data of the first memory bank is output, and data of the memory banks. A sense amplifier, a latch circuit for storing data sensed by the sense amplifier, and a plurality of I / Os for conveying the sensed data, wherein the sense amplifier includes a discharge circuit for discharging a bit line and the bit line. A precharge circuit for precharging the bit line to a predetermined level after discharge, a bias circuit for controlling the voltage level of the bit line after the bit line precharge, and a response of the bias circuit in response to a sense signal. Plot the output of the bias circuit so that the output remains at a constant level. Includes a bias control circuit.

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

TECHNICAL FIELD The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a burst read cycle.

1 and 2 are circuit diagrams showing an array configuration of a NOR flash memory device.

The memory cell array 100 includes a plurality of array blocks, and only one array block will be described below. The array block includes a plurality of bit lines (GBL0, GBL1, GBL2 ..., SBL0, SBL1, SBL2, ...) which are arranged in parallel in the column direction. The memory cells correspond to the word lines WL0 to WLn, respectively, and are connected in parallel between the sub bit lines. NMOS transistors having gates connected to corresponding word lines WL0 to WLn, and source-drain channels, that is, current paths, formed in regions where word lines WL0 to WLn and sub bit lines cross. It contains them. One SBL and a GBL are selected to read the memory cell, and at the same time, a word line, an SSL, and a GSL are selected. In addition to the selected SBL, SBL and GBL adjacent to the selected SBL are further selected to be used as bias bit lines.

In order to read whether the selected memory cell is on-cell or off-cell, the sense amplifier senses the voltage level of the selected main bit line and outputs data to the outside. When the sense amplifier of the NOR flash memory device is in the burst read mode, the voltage level of the bit lines may change due to noise, thereby incorrectly detecting data.

Accordingly, an object of the present invention is to solve the above-mentioned problems, and to provide a semiconductor memory device capable of preventing a read error due to noise.

1 is a block diagram schematically showing a configuration of a semiconductor memory device;

2 shows a configuration of a memory block;

3 is a timing diagram of a read operation of FIG. 1.

4 shows a configuration of a sense amplifier;

5 is an operation timing diagram of FIG. 4;

6 is a circuit diagram showing a configuration of a bias circuit;

7 is a timing diagram showing the problem of FIG. 4 due to noise;

8 is a circuit diagram showing a configuration of a bias circuit according to the present invention; And

9 is an operation timing diagram of the sense amplifier according to FIG. 8.

* Description of the symbols for the main parts of the drawings *

30: memory block 40, 60: sense amplifier

50, 70: latch circuit

According to a feature of the present invention for achieving the object of the present invention as described above, in the semiconductor memory device that senses the data while the data is sequentially output in synchronization with the read activation signal, the cell in synchronization with the read activation signal A first memory bank to which data of the same is output; A second memory bank in which data of cells is sensed when outputting data of the first memory bank; A sense amplifier configured to sense data by receiving current of a selected bit line corresponding to the eight bit lines; A latch circuit for storing data sensed by the sense amplifier and a plurality of I / Os for transferring data of the latch circuit to the outside, the sense amplifier comprising: a discharge circuit for discharging a bit line; A precharge circuit for precharging the bit line to a predetermined level after the bit line discharge; A bias circuit for controlling the voltage level of the bit line after the bit line precharge; And a bias control circuit for plotting the output of the bias circuit so that the output of the bias circuit maintains a constant level in response to a sense signal.

In a preferred embodiment, the bias control circuit comprises a voltage supply circuit for supplying a power supply voltage in response to a comparison signal, a distribution circuit for accepting and distributing the power supply voltage, and the distribution circuit in response to the detection signal .phi.STG. It includes a blocking circuit to block the output of the.

In a preferred embodiment, the blocking circuit comprises a switch connected between the distribution circuit and the bias control circuit output.

(Action)

According to the present invention as described above, in the burst read mode semiconductor memory device, it is possible to prevent a read error that incorrectly detects the off-cell on-cell due to I / O transition noise.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 9.

In the following description, specific details are set forth by way of example and in detail in order to provide a more thorough understanding of the present invention. However, for those skilled in the art, the present invention may be practiced only by the above description without these details.

1 illustrates a memory block configuration of a semiconductor memory device.

Referring to FIG. 1, in a semiconductor memory device having two memory banks, eight data are output when a burst is read in one bank. Eight sense amplifiers S / A # 0 to S / A # 7 correspond to one I / O. Each sense amplifier includes latch circuits LATCH # 0 to LATCH # 7 to store sensed data of a selected memory cell. The semiconductor memory device having the above structure reads 8 × 16 pieces of data during the latency period. A gapless read method is used to read the data, and the gapless read method is a semiconductor memory device having two banks, wherein eight data are output in a burst mode in a first memory bank (second memory bank). Another second memory bank (first memory bank) refers to a method of detecting new data (eight data).

Referring back to FIG. 2, a description of a hierarchical bit line system of an array with NOR-structured memory cells is described in Digest of Technical Paper, in Symposium on VLSI Circuit held in Tokyo, Japan, August 1988. on pp. 85-88, entitled "16Mb ROM Design Using Bank Select Architecture." A hierarchical bit line system of NOR type mask roms is described in detail in this document. The data read operation is classified into three sections, that is, a bit line precharge section, a data sensing section, and a data output section. In the precharge section for the read operation, it is a section for precharging the main bit lines to a predetermined voltage level in order to read the data stored in the selected cell.In the data sensing section, the selected cell is on-cell or off-cell. The voltage level of the corresponding main bit line is sensed to read whether it is off-cell. Finally, the detected data is output to the outside in the data output section.

The data read operation is described in detail as follows.

A power supply voltage is applied to a pair of bank selection signals, which are power supply voltage levels, and a selected word line WL0 to sense data of cells in the memory block. The pair of bank select signals select a main bit line, whereby data of cells associated with the selected main bit line and the selected word line are sensed through a sense amplifier. That is, when the selected cell is on cell, the voltage level of the selected main bit line is lower than the precharge level through the current path. In contrast, when the selected cell is off cell, the voltage level of the main bit line is precharge level. Will be maintained. The sense amplifier therefore outputs the data of the cell by sensing the voltage level of the main bit line.

3 is an operation timing diagram in a burst read mode.

Referring to FIG. 3, the burst read mode semiconductor memory device may divide an operation into an address input period, a latency period, and a data read period. If the address latch enable (ALEH) is 'H' and the ALEL is 'H', the first address is input. If the ALEH is 'L' and the ALEL is 'H', the second address signal is input. When ALEH is 'L' and ALEL is 'L', a latency period is provided so that the sense amplifier 40 senses data of the cell and stores the data in the latch circuit 50. After the time tRL has passed, data is sequentially output when the read enable signal (RE) is toggled.

FIG. 4 shows the sense amplifier configuration of FIG. 1.

Referring to FIG. 4, the sense amplifier 40 is connected to eight bit lines B / L0 to B / L7, which are connected to the latch circuit 50 through Y-pass gates. The latch circuit 50 receives the current supplied from the selected bit line and stores data sensed as '0' or '1'. Since the configuration of the transistors corresponding to one bit line is the same, only the first bit line will be described.

First, an NMOS transistor N1 for discharging the bit line B / L0 is connected to a bit line B / L0 in response to a discharge signal .phi.dis <0>. After the discharge of the bit line B / L0, a PMOS transistor P1 for precharging the bit line B / L0 to a predetermined level in response to a precharge signal Φpre is applied to the bit line B / L0. Connected with A load transistor P2 serving as a load to the bit line B / L0 and pass gates P3 and P4 connecting the bit line B / L0 and the latch circuit 50 are connected in series. do. A bias transistor N9 is connected to keep the voltage level of the bit line B / L0 constant during a read operation. The bias transistor N9 is present for each of the bit lines B / L0 to B / L7, respectively, N9 to N16, which are controlled by the same signal Vbias <0>.

The bit lines B / L0 to B / L7 must be discharged to the ground level for the data read operation, which is necessary when the discharge signal .phi.dis shifts from 'L' to 'H'. By turning on. Then, the precharge signal .phi.pre is shifted from 'H' to 'L' and the bit line B / L0 is precharged to a predetermined level (for example, 1v) through the PMOS transistor P1. In order to keep the voltage level of the bit line B / L0 constant, a transistor N9 which receives the bias signal Vbias is used. When the voltage level of the bias signal Vbias is greater than the voltage level of the bit line by Vtn and applied to the transistor N9, the transistor N9 is turned off by reaching the voltage level of the bit line B / L0. The bit line B / L0 is precharged to a certain level. After the bias signal Vbias is set to a voltage level for controlling the voltage level of the bit line, the transistor P1 is turned on by the precharge signal phi pre to receive the bias signal Vbias. And the precharge transistor P1 are supplied to the bit line B / L0. As described above, after the bit line B / L0 is precharged to a predetermined level, the transistor N9 is turned off to maintain BSO <0> at the VCC level.

When the precharge operation of the bit line is completed, the data stored in the memory cell is read. If the selected memory cell is an on cell (cell with current path: data '1'), current flows to the ground, whereby the voltage level of the bit line B / L0 and BSO <0> is lowered. . Conversely, if the selected memory cell is an off cell (a cell with no current path: data '0'), no current flows through the cell to ground, so the bit line and BSO maintain the voltage level. do. However, in order to shorten the precharge time of the bit line, data of the selected memory cell is first read before the precharge operation of the bit line connected to the off-cell is completed. Therefore, the precharge current must be compensated for the off-cell bit line so that the bit line and BSO <0> can maintain the voltage level. The current compensated for the bit line is called load current.

The load current flows when the signal Φ load is set to a specific level (for example, 1.8v) and then applied to the gate of the PMOS transistor P3. As the load current flows through the PMOS transistor P2, the bit lines B / L0 to B / L7 precharged to a predetermined level may change in accordance with the state of the connected memory cell. For example, in the on-cell case, the voltage level of the bit line and BSO <0> is lowered because the amount of current flowing from the cell to ground is greater than the load current. On the other hand, in the case of off-cell, since the bit line precharge current of the selected cell is smaller than the load current, the bit line and BSO <0> maintain the voltage level. When the BSO voltage level is transferred to the latch circuit 50 through the pass gates P3, P4, and P33, data of the cell is read.

5 is a gapless read operation timing diagram.

Referring to FIG. 5, as in FIG. 3, addresses are sequentially input according to transition levels of ALEH and ALEL, and data is sensed by a sense amplifier for a predetermined period and stored in the latch circuit 50. Then, as the read activation signal RE is toggled, eight data D7 to D15 stored in the latch circuit are sequentially output. Eight data D0 to D7 are sequentially output through the sensing period as described above (burst read mode).

6 is a circuit diagram showing the configuration of a bias circuit for maintaining the precharge level of a bit line.

Referring to FIG. 6, a bias circuit for controlling transistors N9 to N16 for keeping the precharge level of the bit line constant includes PMOS transistor 1, resistors 2, 3 and comparator 4. It is composed of The PMOS transistor 1 has a gate connected to the output terminal of the comparator 3 and a current path is formed between the power supply voltage VCC and the node Node1. The resistors 2, 3 are connected in series between the current path of the PMOS transistor 1 and the ground VSS and their connection node Node2 is connected to the non-inverting terminal of the comparator 4. The comparator 4 accepts the reference voltage Vref as the inverting terminal, accepts the bias voltage Vbias distributed through the resistors 2 and 3 as the non-inverting terminal and outputs the gate of the PMOS transistor 1. Is connected to. The reference voltage Vref maintained constant even when the external power source changes, and the voltage distributed through the resistors 2 and 3 ) Is compared through the comparator 3 and the operation of the PMOS transistor 1 is controlled according to the comparison result of the voltages. By the bias circuit, the bias voltage is Is kept constant.

7 is a timing diagram illustrating a read error occurring in a gapless read operation.

Referring to FIG. 7, the data Di is output from the I / O during the data sensing operation, and the noise A is generated whenever the I / O transitions for the next data output Di + 1. The I / O transition noise also affects VSS. The VSS also affects the bias circuit so that noise is amplified by the ratio of the resistors R1 and R2, which is loaded at the bias voltage level. As a result, the NMOS transistor N9 whose operation is controlled by the bias voltage Vbias is turned on so that the BSO, which must maintain VCC in the case of the off-cell, is lowered to the bit line level, so that the data of the memory cell is incorrectly detected. And C occur.

8 is a circuit diagram showing the configuration of a bias circuit according to the present invention.

Referring to FIG. 8, the bias circuit consists of a PMOS transistor 5, resistors 6, 7 comparator 8 and a switch circuit 9. The PMOS transistor 5 has a gate connected to the output of the comparator 8 and a current path connected between the supply voltage and node Node1. Resistors 6 and 7 are connected in series between the node Node1 and ground. The comparator 8 has an inverting terminal which receives a reference voltage vref and a non-inverting terminal which is connected to a node Node2 to which the resistors 6 and 7 are interconnected. The switch circuit 8 comprises a switch sw1 connected between the node Node1 and the bias voltage output terminal 10 and turned on and off by a sense signal .phi.STG. The switch sw1 may be configured as a MOS transistor.

The bias circuit causes the switch sw1 to be turned off while the data sensing signal .phi.STG is 'H' to float the bias voltage output terminal 10. Therefore, even if noise is applied to the bias circuit due to I / O transition noise, the switch sw1 disconnects from the bias voltage output terminal 10 so that the bias voltage output terminal 10 maintains its previous state as a floating state. By using the bias circuit according to the present invention, the BSO corresponding to the bit line of the off-cell is sensed as off-cell as VCC is maintained as it is.

9 is a timing diagram of a gapless read operation according to the present invention.

9, the bit lines are discharged to the ground level when the signal indicating the data sensing interval is activated and the discharge signal .phi.dis transitions from 'L' to 'H'. After the discharge of the bit line is completed, the bit lines are precharged to a predetermined level by a precharge signal phi pre. As the read enable signal RE toggles, the sense amplifier senses and outputs data of the memory cells. Whenever the sensed data is output to the I / O (every transition), the generated noise is carried on the VSS as shown in FIG. This is also transmitted to the bias circuit, but while the sensing signal ΦSTG is 'H', the bias voltage Vbias, which is the output of the bias circuit, becomes floating due to the switch sw1 off to maintain the previous voltage level. . Therefore, the voltage level of the BSO is maintained in the sensing period for the off-cell to prevent the case of being misread on-cell.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely described, for example, and various changes and modifications are possible without departing from the spirit of the present invention. .

According to the present invention as described above, it is possible to prevent the sense amplifier from incorrectly detecting the data of the cell due to the I / O transition noise.

Claims (3)

A semiconductor memory device which senses data while simultaneously outputting data sequentially in synchronization with a read activation signal. A first memory bank in which data of cells are output in synchronization with the read activation signal; A second memory bank in which data of cells is sensed when outputting data of the first memory bank; A sense amplifier configured to sense data by receiving current of a selected bit line corresponding to the eight bit lines; A latch circuit for storing data sensed by the sense amplifier; Including a plurality of I / O for transmitting the data of the latch circuit to the outside, The sense amplifier, A discharge circuit for discharge of the bit line; A precharge circuit for precharging the bit line to a predetermined level after the bit line discharge; A bias circuit for controlling the voltage level of the bit line after the bit line precharge; And a bias control circuit that floats the output of the bias circuit in response to a sense signal (ΦSTG) so that the output of the bias circuit maintains a constant level. The method of claim 1, The bias control circuit includes a voltage supply circuit for supplying a power supply voltage in response to a comparison signal; A distribution circuit that accepts and distributes the power supply voltage; And a blocking circuit to block an output of the distribution circuit in response to the sensing signal. The method of claim 2, And the blocking circuit comprises a switch connected between the distribution circuit and a bias control circuit output.