KR20000043921A - Fabrication method of flash memory device - Google Patents
Fabrication method of flash memory device Download PDFInfo
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- KR20000043921A KR20000043921A KR1019980060359A KR19980060359A KR20000043921A KR 20000043921 A KR20000043921 A KR 20000043921A KR 1019980060359 A KR1019980060359 A KR 1019980060359A KR 19980060359 A KR19980060359 A KR 19980060359A KR 20000043921 A KR20000043921 A KR 20000043921A
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 230000004888 barrier function Effects 0.000 claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 11
- 229920005591 polysilicon Polymers 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims abstract description 11
- -1 silicon oxy nitride Chemical class 0.000 claims abstract description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 7
- 125000006850 spacer group Chemical group 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 238000010791 quenching Methods 0.000 claims 2
- 230000000171 quenching effect Effects 0.000 claims 2
- 238000009751 slip forming Methods 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 6
- 239000002184 metal Substances 0.000 abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 9
- 230000000694 effects Effects 0.000 description 6
- 238000005247 gettering Methods 0.000 description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 5
- 239000011575 calcium Substances 0.000 description 4
- 239000012528 membrane Substances 0.000 description 4
- 230000014759 maintenance of location Effects 0.000 description 3
- 239000011734 sodium Substances 0.000 description 3
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 description 2
- 210000003323 beak Anatomy 0.000 description 2
- 229910052791 calcium Inorganic materials 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 플래쉬 메모리 장치 제조 방법에 관한 것으로, 플로팅 게이트의 차지 손실을 억제시켜 소자의 신뢰성을 향상시키기 위한 플래쉬 메모리 장치 제조 방법에 관한 것이다.The present invention relates to a flash memory device manufacturing method, and to a flash memory device manufacturing method for suppressing the charge loss of the floating gate to improve the reliability of the device.
소자 특성상 플래쉬 메모리는 플로팅 게이트에 전자가 일정량 이상 차 있는 것과 그렇지 못한 경우에 따라서 프로그램 상태와 소거 상태를 구분한다. 소자의 신뢰성을 향상시키기 위해서는 플로팅 게이트에 전자를 주입해 준 프로그램 상태에서 외부 환경의 변화에 따라 차지 량이 감소하여 소거 상태로 바뀌어서는 안되는 특성이 요구된다.The flash memory distinguishes the program state from the erased state according to the device characteristics depending on whether the electrons in the floating gate are over a certain amount or not. In order to improve the reliability of the device, in the program state in which electrons are injected into the floating gate, the charge amount is reduced according to the change of the external environment, and therefore, the characteristic should not be changed to the erase state.
도 1(a) 및 1(b)는 종래 플래쉬 메모리 장치 제조 방법을 설명하기 위해 도시한 소자의 단면도이다.1 (a) and 1 (b) are cross-sectional views of a device for explaining a conventional flash memory device manufacturing method.
도 1(a)에 도시된 바와 같이, 기판(11) 상부에 터널 산화막(12), 플로팅 게이트용 제 1 폴리실리콘층(13), ONO 구조의 유전체막(14), 콘트롤 게이트용 제 2 폴리실리콘층(15) 및 반사 방지막(16)을 순차적으로 형성한 후 패터닝하여 플래쉬 메모리 셀을 형성한다. 이후, 전체 구조 상부에 산화막을 형성하고 식각하여 플래쉬 메모리 셀 측벽에 스페이서 산화막(17)을 형성한다. 다음에, PMD 공정을 실시하여 전체 구조 상부에 열산화막(18)을 형성하고, 평탄화를 위하여 BPSG막(19)을 형성한다. 그리고 IMD 공정을 실시하여, 실리콘 옥시 나이트라이드층(20), 유기 SOG막(21) 및 플라즈마 산화막(22)을 순차적으로 형성한다. 절연막 형성이 완료되면 금속층을 형성하고 패터닝하여 금속배선(23)을 형성한다.As shown in Fig. 1A, the tunnel oxide film 12, the first polysilicon layer 13 for the floating gate, the dielectric film 14 of the ONO structure, and the second poly for the control gate are formed on the substrate 11. The silicon layer 15 and the anti-reflection film 16 are sequentially formed and then patterned to form a flash memory cell. Thereafter, an oxide film is formed on the entire structure and etched to form a spacer oxide film 17 on the sidewall of the flash memory cell. Next, a PMD process is performed to form a thermal oxide film 18 over the entire structure, and a BPSG film 19 is formed for planarization. Then, an IMD process is performed to sequentially form the silicon oxy nitride layer 20, the organic SOG film 21, and the plasma oxide film 22. When the insulating film is formed, the metal layer is formed and patterned to form the metal wiring 23.
이와 같은 방법을 플래쉬 메모리 장치를 제조하는 경우, 막 내부에 함유되어 있던 수분이 BPSG막에 침투하면서 BPSG막에 게터링(gettering)되어 있던 나트륨(Na+) 또는 칼슘(Ca+)과 치환반응 하면서 이동 이온을 방출하여 플로팅 게이트 내의 전자를 중화시키므로써 플로팅 게이트 내의 전자를 감소시켜 셀을 프로그램 상태에서 소거 상태로 바뀌게 하여 소자의 오동작을 유발하게 된다.In the case of manufacturing a flash memory device, the moisture contained in the membrane penetrates the BPSG membrane and transfers to the ion (Na +) or calcium (Ca +), which has been gettered on the BPSG membrane, and reacts with the mobile ions. By emitting the electrons to neutralize the electrons in the floating gate, the electrons in the floating gate are reduced to change the cell from the program state to the erase state, thereby causing the device to malfunction.
이러한 문제점을 해결하기 위하여, 도 1(b)에 도시된 바와 같이, BPSG막 형성전에 이동 이온에 대한 게터링 효과가 높은 PSG막(24)을 형성한다. [표 1]은 PSG막의 증착 여부에 따른 배이크(bake) 테스트시의 차지 리텐션 특성을 나타낸다.In order to solve this problem, as shown in Fig. 1 (b), the PSG film 24 having a high gettering effect on mobile ions is formed before the BPSG film is formed. Table 1 shows charge retention characteristics during a bake test depending on whether or not a PSG film is deposited.
배이크 테스트는 300℃의 온도에서 실시하였으며, 배이크 테스트 결과는 8M 플래쉬 메모리 셀 중 차지 손실로 인하여 패일된 비트 수를 나타낸다.The beak test was conducted at a temperature of 300 ° C., and the beak test results show the number of bits failed due to charge loss in 8M flash memory cells.
[표 1]에서 알 수 있는 바와 같이, BPSG막(19) 형성 전 PSG막(24)을 형성하게 되면, 배이크 테스트 공정에서 차지 리텐션 특성이 상당히 향상되어 있음을 아 수 있다. 그러나 차지 손실을 완전히 억제하지는 목하고, 8M 비트당 3 내지 4비트씩 진행성 차지 손실을 보이고 있다. 이는 어느 층에선가 수분이 BPSG막과 PSG막에 침투되어 오면서 BPSG막, PSG막에 함유되어 있던 나트륨(Na+), 칼슘(Ca+) 등과 치환반응 되면서 이동 이온을 방출하여 플로팅 게이트 내의 전자를 중화시키므로써 플로팅 게이트 내의 전자를 감소시켜 프로그램 상태에서 소거 상태로 바뀌게 하여 소자의 오동작을 일으키게 한다. 이때, BPSG막과 PSG막으로 침투하는 수분은 SOG막(21) 내의 수분 및 BPSG막(19) 내의 수분이 소오스가 될 수 있다.As can be seen from Table 1, when the PSG film 24 is formed before the BPSG film 19 is formed, it can be seen that the charge retention characteristic is significantly improved in the batch test process. However, it does not completely suppress the charge loss, and shows progressive charge loss of 3 to 4 bits per 8M bits. As water penetrates the BPSG film and the PSG film in some layers, it reacts with the sodium (Na +) and calcium (Ca +) contained in the BPSG film and the PSG film and releases mobile ions to neutralize electrons in the floating gate. The electrons in the surplus floating gate are reduced and changed from the program state to the erase state, causing the device to malfunction. At this time, the moisture penetrating into the BPSG film and the PSG film may be a source of water in the SOG film 21 and water in the BPSG film 19.
따라서, 본 발명은 PMD 공정 및 IMD 공정시 수분에 대한 배리어 특성이 우수한 실리콘 옥시 나이트라이드막과 이동 이온에 대한 게터링 효과가 우수한 PSG막을 이용하므로써 플로팅 게이트에 주입되어 있는 전자가 중화되는 것을 방지하여 차지 손실을 막을 수 있는 플래쉬 메모리 장치 제조 방법을 제공하는 데 그 목적이 있다.Accordingly, the present invention prevents the electrons injected into the floating gate from being neutralized by using a silicon oxy nitride film having excellent barrier properties against moisture during the PMD process and an IMD process and a PSG film having a good gettering effect on mobile ions. It is an object of the present invention to provide a method of manufacturing a flash memory device that can prevent charge loss.
상술한 목적을 달성하기 위한 본 발명에 따른 플래쉬 메모리 장치 제조 방법은 기판 상에 터널 산화막, 플로팅 게이트용 제 1 폴리실리콘층, 유전체막, 콘트롤 게이트용 제 2 폴리실리콘층 및 반사 방지막을 순차적으로 형성한 후 패터닝하여 플래쉬 메모리 셀을 형성하고, 전체 구조 상부에 산화막을 형성한 다음 식각하여 상기 플래쉬 메모리 셀 측벽에 스페이서 산화막을 형성하는 단계와, 전체 구조 상부에 열산화막, 제 1 PSG막, 제 1 수분 배리어막 및 제 1 평탄화막을 순차적으로 형성하는 단계와, 상기 제 1 평탄화막 상부에 제 2 PSG막, 제 2 수분 배리어막, 제 2 평탄화막 및 플라즈막 산화막을 순차적으로 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In the flash memory device manufacturing method according to the present invention for achieving the above object is sequentially formed a tunnel oxide film, a first polysilicon layer for floating gate, a dielectric film, a second polysilicon layer for a control gate and an anti-reflection film on a substrate And then patterning to form a flash memory cell, and then forming an oxide film on the entire structure, followed by etching to form a spacer oxide film on the sidewall of the flash memory cell, a thermal oxide film, a first PSG film, and a first structure on the entire structure. Sequentially forming a moisture barrier film and a first planarization film, and sequentially forming a second PSG film, a second moisture barrier film, a second planarization film, and a plasma film oxide film on the first planarization film. Characterized in that made.
도 1(a) 및 1(b)는 종래 플래쉬 메모리 장치 제조 방법을 설명하기 위해 도시한 소자의 단면도.1 (a) and 1 (b) are cross-sectional views of elements shown for explaining a conventional flash memory device manufacturing method.
도 2는 본 발명에 따른 플래쉬 메모리 장치 제조 방법을 설명하기 위해 도시한 소자의 단면도.Figure 2 is a cross-sectional view of the device shown for explaining the method of manufacturing a flash memory device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
201 : 기판 202 : 터널 산화막201: substrate 202: tunnel oxide film
203 : 플로팅 게이트 204 : 유전체막203: floating gate 204: dielectric film
205 : 콘트롤 게이트 206 : 반사 방지막205: control gate 206: antireflection film
207 : 스페이서 산화막 208 : 열산화막207 spacer oxide film 208 thermal oxide film
209 : 제 1 PSG막 210 : 제 1 수분 배리어막209: first PSG film 210: first moisture barrier film
211 : 제 1 평탄화막 212 : 제 2 PSG막211: first planarization film 212: second PSG film
213 : 제 2 수분 배리어막 214 : 제 2 평탄화막213: second moisture barrier film 214: second planarization film
215 : 플라즈마 산화막 216 : 금속 배선215: plasma oxide film 216: metal wiring
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2는 본 발명에 따른 플래쉬 메모리 장치 제조 방법을 설명하기 위해 도시한 소자의 단면도이다.2 is a cross-sectional view of a device illustrated to explain a method of manufacturing a flash memory device according to the present invention.
도시된 바와 같이, 기판(201) 상부에 터널 산화막(202), 플로팅 게이트용 제 1 폴리실리콘층(203), ONO 구조의 유전체막(204), 콘트롤 게이트용 제 2 폴리실리콘층(205) 및 반사 방지막(206)을 순차적으로 형성한 후 패터닝하여 플래쉬 메모리 셀을 형성한다. 이후, 전체 구조 상부에 산화막을 형성한 후 식각하여 플래쉬 메모리 셀 측벽에 스페이서 산화막(207)을 형성하고, PMD 공정을 실시하여 전체 구조 상부에 열산화막(18)을 형성한다. 다음에, 플로팅 게이트에 주입된 전하는 외부의 이동 이온으로부터 보호하기 위하여 이동 이온에 대한 게터링 효과가 우수한 제 1 PSG막(209)을 형성하고 제 1 수분 배리어막(210)을 형성한다. 제 1 수분 배리어막(210)으로는 수분에 대한 배리어 특성이 우수한 실리콘 옥시 나이트라이드(SiON)막 또는 실리콘 나이트라이드(SiN)막을 이용한다. 이후, 전체 구조 상부에 제 1 평탄화막(예를 들어, BPSG막; 211)을 형성한다.As shown, the tunnel oxide film 202, the first polysilicon layer 203 for the floating gate, the dielectric film 204 of the ONO structure, the second polysilicon layer 205 for the control gate, and the like on the substrate 201, and The antireflection film 206 is sequentially formed and then patterned to form a flash memory cell. Thereafter, an oxide film is formed on the entire structure, and then etched to form a spacer oxide film 207 on the sidewall of the flash memory cell, and a PMD process is performed to form a thermal oxide film 18 on the entire structure. Next, the charge injected into the floating gate is formed to form the first PSG film 209 having excellent gettering effect on the mobile ions and the first moisture barrier film 210 in order to protect against external mobile ions. As the first moisture barrier layer 210, a silicon oxynitride (SiON) film or a silicon nitride (SiN) film having excellent barrier property against moisture is used. Thereafter, a first planarization film (eg, a BPSG film) 211 is formed on the entire structure.
IMD층은 실리콘 옥시 나이트라이드막(213) 형성 전 먼저, 게터링 효과가 우수한 제 2 PSG막(212)을 먼저 형성하고, 제 2 수분 배리어막(예를 들어, 실리콘 옥시 나이트라이드막; 213), 제 2 평탄화막(예를 들어; SOG막; 214) 및 플라즈마 산화막(215)을 순차적으로 형성한다. 다음에, 금속층을 형성하고 패터닝하여 금속배선(216)을 형성한다.Before forming the silicon oxy nitride film 213, the IMD layer first forms a second PSG film 212 having excellent gettering effect, and then a second moisture barrier film (for example, silicon oxy nitride film; 213). A second planarization film (eg, an SOG film) 214 and a plasma oxide film 215 are sequentially formed. Next, a metal layer is formed and patterned to form a metal wiring 216.
여기에서 제 1 및 제 2 PSG막(209,212)의 인 농도는 3∼6%로 한다. 그리고 제 1 및 제 2 PSG막(209,212)은 TEOS와 TMP를 소오스로 한 APCVD 방법으로 증착하거나 플라즈마 CVD 방식으로 증착한다. 만약, 제 1 및 제 2 PSG막(209,212)을 플라즈마 CVD 방식으로 증착하는 경우에는 SiH4, O2(또는, N2O), PH3를 소오스 가스로 사용하며, 후속 공정으로 형성되는 제 1 수분 배리어막(210)을 동일한 챔버 내에서 연속적으로 형성한다. 또한, 제 1 및 제 2 수분 배리어막(210, 213)은 SiON 또는 SiN을 이용하여 1000Å 이상의 두께로 형성한다. 그리고, 평탄화 및 갭-필링 특성을 향상시키기 위해 사용하는 제 2 평탄화막(214)으로는 유기 SOG막 및 무기 SOG막 중 어느 하나를 사용하는데, 무기 SOG막을 사용하는 경우에는 500℃ 이상에서 큐링 공정을 실시하여 무기 SOG막의 수분을 제거하는 과정이 필요하다. 또한, 제 1 평탄화막(211)으로 무기 SOG막을 사용할 수도 있으며, 이 경우에도 500℃ 이상에서 큐링 공정을 실시하여 무기 SOG막의 수분을 제거하는 공정을 실시한다. 제 2 PSG막(212) 대신 SiON막을 3000Å 이상의 두께로 형성한 다음 무기 SOG막(214)을 형성할 수도 있다.The phosphorus concentrations of the first and second PSG films 209 and 212 are set to 3 to 6%. The first and second PSG films 209 and 212 are deposited by APCVD using TEOS and TMP as a source or by plasma CVD. When the first and second PSG films 209 and 212 are deposited by plasma CVD, SiH 4 , O 2 (or N 2 O), and PH 3 are used as source gases, and the first process is formed in a subsequent process. The moisture barrier film 210 is formed continuously in the same chamber. In addition, the first and second moisture barrier films 210 and 213 are formed to have a thickness of 1000 GPa or more using SiON or SiN. As the second planarization film 214 used to improve the planarization and gap-filling characteristics, any one of an organic SOG film and an inorganic SOG film may be used. The process of removing water from an inorganic SOG film | membrane is needed. In addition, an inorganic SOG film may be used as the first planarization film 211. In this case, a curing process may be performed at 500 ° C or higher to remove moisture from the inorganic SOG film. Instead of the second PSG film 212, a SiON film may be formed to a thickness of 3000 GPa or more, and then an inorganic SOG film 214 may be formed.
이와 같이, PMD층을 제 1 PSG/제 1 SiON/BPSG의 적층 구조(209/210/211)로 형성하고, IMD층을 제 1 PSG/제 1 SiON/SOG/플라즈마 산화막의 적층 구조(212/213/214/215)로 형성하므로써, SOG막(214) 내의 수소이온의 움직임을 IMD층에서부터 효과적으로 블럭킹할 수 있다. 또한, BPSG막 자체의 수분 확산에 의해 PSG막에 게터링되어 있던 이동 이온과 BPSG막이 치환반응하여 플로팅 게이트에 주입되어 있는 전자를 중화시키는 것을 방지할 수 있어 차지 리텐션 특성을 개선할 수 있다.In this manner, the PMD layer is formed of the laminated structure (209/210/211) of the first PSG / first SiON / BPSG, and the IMD layer is formed of the laminated structure of the first PSG / first SiON / SOG / plasma oxide film (212 / 213/214/215, the movement of hydrogen ions in the SOG film 214 can be effectively blocked from the IMD layer. In addition, due to the water diffusion of the BPSG film itself, it is possible to prevent neutralization of electrons injected into the floating gate due to substitution reaction between the mobile ions gettered on the PSG film and the BPSG film, thereby improving charge retention characteristics.
상술한 바와 같이, 본 발명에 따르면 이동 이온에 대한 게터링 효과를 갖는 PSG막과 수분에 대한 배리어 특성이 우수한 실리콘 옥시 나이트라이드(또는 실리콘 나이트라이드)막을 PMD 공정과 IMD 공정에 적용하므로써, 플래쉬 메모리 장치에서의 차지 손실을 억제하여 소자의 신뢰성 및 수율을 향상시킬 수 있는 효과가 있다.As described above, according to the present invention, a PSG film having a gettering effect on mobile ions and a silicon oxynitride (or silicon nitride) film having excellent barrier properties against moisture are applied to a PMD process and an IMD process, thereby providing a flash memory. There is an effect of suppressing the charge loss in the device to improve the reliability and yield of the device.
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| KR20030019088A (en) * | 2001-08-27 | 2003-03-06 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device |
| KR100753401B1 (en) * | 2001-06-15 | 2007-08-30 | 주식회사 하이닉스반도체 | Method for manufacturing flash memory device |
| EP2641732A4 (en) * | 2010-11-19 | 2014-04-30 | Konica Minolta Inc | BARRIER FILM AGAINST GAS AND METHOD FOR PRODUCING SAME, AND ELECTRONIC DEVICE |
| EP2650121A4 (en) * | 2010-12-06 | 2014-05-07 | Konica Minolta Inc | Gas-barrier film, method for producing gas-barrier film, and electronic device |
| EP2660041A4 (en) * | 2010-12-27 | 2014-06-25 | Konica Minolta Inc | Gas-barrier film and electronic device |
| CN114188397A (en) * | 2021-11-18 | 2022-03-15 | 上海华虹宏力半导体制造有限公司 | MTP device and manufacturing method thereof |
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| JPS6482653A (en) * | 1987-09-25 | 1989-03-28 | Nec Corp | Semiconductor integrated circuit |
| JPH03270256A (en) * | 1990-03-20 | 1991-12-02 | Nippon Precision Circuits Kk | Semiconductor device |
| JPH04102329A (en) * | 1990-08-22 | 1992-04-03 | Nec Corp | Manufacture of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100753401B1 (en) * | 2001-06-15 | 2007-08-30 | 주식회사 하이닉스반도체 | Method for manufacturing flash memory device |
| KR20030019088A (en) * | 2001-08-27 | 2003-03-06 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device |
| EP2641732A4 (en) * | 2010-11-19 | 2014-04-30 | Konica Minolta Inc | BARRIER FILM AGAINST GAS AND METHOD FOR PRODUCING SAME, AND ELECTRONIC DEVICE |
| US9603268B2 (en) | 2010-11-19 | 2017-03-21 | Konica Minolta, Inc. | Gas barrier film, method of producing a gas barrier film, and electronic device |
| EP2650121A4 (en) * | 2010-12-06 | 2014-05-07 | Konica Minolta Inc | Gas-barrier film, method for producing gas-barrier film, and electronic device |
| EP2660041A4 (en) * | 2010-12-27 | 2014-06-25 | Konica Minolta Inc | Gas-barrier film and electronic device |
| US9646940B2 (en) | 2010-12-27 | 2017-05-09 | Konica Minolta, Inc. | Gas barrier film and electronic device |
| CN114188397A (en) * | 2021-11-18 | 2022-03-15 | 上海华虹宏力半导体制造有限公司 | MTP device and manufacturing method thereof |
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