KR20000027273A - Method for manufacturing flash memory - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a method of manufacturing a flash memory having one cell and two bits.

2. Technical problem to be solved by the invention

The present invention seeks to improve the decrease in the production efficiency per wafer due to the increase in the chip size generated in the manufacture of the conventional one-cell one-bit device.

3. Summary of the Solution of the Invention

In the method of manufacturing a flash memory according to the present invention, a field oxide film is formed on a semiconductor substrate to define an active region, a tunnel oxide film is formed, and a plurality of rectangular polysilicon patterns for floating gates are formed on selected portions of the tunnel oxide film. A dielectric film, a polyside layer, and an anti-reflection layer are sequentially formed on the entire structure in which the floating silicon polysilicon pattern is formed, and formed in a direction crossing the field oxide film, so that a part of each of the neighboring floating silicon polysilicon patterns is included. A mask layer is formed on the antireflection layer, and the antireflection layer, the polyside layer, the dielectric film, the polysilicon pattern for the floating gate, and the tunnel oxide film are sequentially etched through an etching process using the mask layer, and the first and second 2 floating gate is formed, source and drain It is made in the order of forming.

Description

Manufacturing Method of Flash Memory

The present invention relates to a method of manufacturing a flash memory, and more particularly, to a method of manufacturing a flash memory capable of storing two bits of data in one cell.

Conventional flash memory cells store one bit of data in one cell. This type of flash memory cell is illustrated in FIG.

FIG. 1 (a) is a layout view of a conventional flash memory cell, and FIG. 1 (b) is a cross-sectional view showing a state in which part XX of FIG. 1 (a) is cut away. The method is as follows.

After the field oxide film 10 is formed on the semiconductor substrate 1 to define an active region, the tunnel oxide film 15 and the floating silicon polysilicon layer 20 are sequentially formed on the entire structure. A portion of the neighboring field oxide layer 10 overlaps each other, and a first mask layer 80 having a linear shape is formed on the floating gate polysilicon layer 20 so as to be parallel to the field oxide layer 10. The floating gate polysilicon layer 20 and the tunnel oxide layer 15 are sequentially etched through an etching process using the first mask layer 80. As a result, a linear floating polysilicon pattern 20 is formed to partially overlap with the field oxide film 10. The dielectric layer 25, the control gate polysilicon layer 30, the tungsten silicide layer 35, and the anti-reflection layer 40 are sequentially formed on the entire structure of the floating gate polysilicon pattern 20. Here, the polysilicon layer 30 and the tungsten silicide layer 35 for the control gate form a polyside layer 37 through heat treatment. A linear second mask layer 90 is formed on the polyside layer 37 in a direction intersecting with the floating gate polysilicon pattern 20 and the field oxide layer 10. The anti-reflection layer 40, the polyside layer 37, the dielectric layer 25, the polysilicon pattern 20 for the floating gate and the tunnel oxide layer 15 may be magnetized through an etching process using the second mask layer 90. Align etching. As a result, the control gate 37 and the floating gate 20 used as the word lines are formed. After the source and drain regions 50 and 60 are formed in the exposed portion of the semiconductor substrate 1 through the impurity ion implantation process, the drain contact 70 connected to the drain region 60 is formed.

The conventional flash memory cell formed by the above method is inadequate at the time of manufacturing a large capacity memory cell because only one bit of data is stored in one cell, resulting in a burden of increasing chip size.

Accordingly, the present invention forms two floating gates for one gate to store two bits of data, thereby increasing more memory capacity and reducing chip size compared to the same chip size. It is an object of the present invention to provide a method of manufacturing a flash memory that can improve production efficiency per wafer.

In order to achieve the above object, the present invention forms a field oxide film on a semiconductor substrate to define an active region, and then forms a tunnel oxide film, and forms a plurality of rectangular polysilicon patterns for floating gates in selected portions on the tunnel oxide film. step; Sequentially forming a dielectric film, a polyside layer, and an antireflection layer on the entire structure on which the polysilicon pattern for floating gate is formed; Forming a mask layer on the anti-reflection layer, the mask layer being formed in a direction intersecting with the field oxide layer and including a portion of each of the neighboring floating silicon polysilicon patterns; Through the etching process using the mask layer, the anti-reflection layer, the polyside layer, the dielectric layer, the floating silicon polysilicon pattern, and the tunnel oxide layer are sequentially self-aligned and etched to the control gate and the first and second floating layers. Forming a gate; And forming a source and a drain.

1A is a layout diagram of a conventional flash memory cell.

(B) is sectional drawing which shows the state which cut | disconnected the X-X part of FIG.

2 (a) and 2 (b), and FIGS. 3 (a) and 3 (b) are layout diagrams and cross-sectional views for sequentially explaining a method of manufacturing a flash memory according to the present invention.

<Description of Signs of Major Parts of Drawings>

1 and 100: semiconductor substrate 10 and 110: field oxide film

15 and 115: tunnel oxide film 20, 120B and 120C: floating gate

120A: Polysilicon Pattern for Floating Gate

25 and 125: dielectric film 123: polysilicon spacer

30 and 130: polysilicon layer for control gate

35 and 135: tungsten silicide layer 37 and 137: polyside layer

40 and 140: antireflection layers 50 and 150: source region

60 and 160: drain region 70 and 170: drain contact

80 and 180: Masks for Floating Gates

90 and 190: Mask for Control Gate

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 (a) and 2 (b), and FIGS. 3 (a) and 3 (b) are layout diagrams and cross-sectional views for sequentially explaining a method of manufacturing a flash memory according to the present invention. ) Is a cross-sectional view showing a state where the YY portion of each drawing (a) is cut out.

Referring to FIGS. 2A and 2B, after forming a field oxide film 110 on a semiconductor substrate 100 on which a general well or a triple well including a general well is formed, an active region is defined. The tunnel oxide film 115 and the polysilicon layer for floating gate are formed in this order. A portion of the neighboring field oxide film 110 overlaps each other, and a plurality of rectangular first mask layers 80 are formed on the floating gate polysilicon layer in a direction parallel to the field oxide film 110. The floating gate polysilicon layer is etched through an etching process using the first mask layer 180 to form a rectangular floating gate polysilicon pattern 120A. After forming a polysilicon layer for spacers on the entire structure on which the floating gate polysilicon pattern 120A is formed, the polysilicon spacers 123 are formed on both sidewalls of the polysilicon pattern 120A for the floating gate through a front surface etching process. Form.

In the above, the semiconductor substrate 100 contains a first conductive impurity, the triple well is formed by injecting a second conductive impurity of the type (Type) opposite to the first conductive impurity, the general well is opposite to the second conductive impurity It is formed by injecting a third conductive impurity of the type. In addition, the polysilicon spacer 123 is used as a part of the floating gate, and is formed to be spaced apart from the neighboring spacer 123 by a predetermined distance. The tunnel oxide film 115 is formed to a thickness of 60 to 150 GPa, and the polysilicon layer for the floating gate and the polysilicon layer for the spacer are formed to a thickness of 300 to 2000 GPa.

Generally, the conductive polysilicon layer is implanted with a conductive impurity, where instead of skipping the conductive impurity implantation of the floating silicon polysilicon layer, the conductive impurity is injected and deglaze into the polysilicon layer for the spacer. To perform the process.

2 (a) and 2 (b), the semiconductor substrate 100 and the semiconductor substrate 100 between the polysilicon spacers 123 are formed to form an off-set region. Conductive impurities having opposite polarities are injected. Subsequently, the dielectric film 125, the polysilicon layer 130 for the control gate, the tungsten silicide layer 135, and the anti-reflection layer 140 are sequentially formed on the entire structure. Here, the polysilicon layer 130 and the tungsten silicide layer 135 for the control gate form a polyside layer 137 through heat treatment.

A second mask layer 190 having a straight shape is formed in a direction crossing the field oxide layer 110 and includes a portion of each of the neighboring floating silicon polysilicon patterns 120A on the anti-reflection layer 140. To form. The anti-reflection layer 140, the polyside layer 137, the dielectric film 125, the polysilicon spacer 123, the polysilicon pattern 120 for the floating gate and the tunnel through an etching process using the second mask layer 190. The oxide film 115 is sequentially self-etched. As a result, the control gate 137 and the first and second floating gates 120B and 120C, which are used as word lines, are formed. The source and drain regions 150 and 160 are formed in the exposed portion of the semiconductor substrate 100 through the impurity ion implantation process, and then the drain contact 170 connected to the drain region 160 is formed.

In the above, about 1E14 to 7E15 ions / cm 2 are implanted into the conductive impurity for forming the off-set region. The dielectric film 125 may be formed to a thickness of 100 to 300 kPa, and may be formed by growing an oxide film to a thickness of 100 to 500 kPa after forming the polysilicon spacer 123 and etching the grown oxide film. The first and second floating gates 120B and 120C are each formed with a ratio of 1: 0.5 to 1 for measuring the current level of the floating gate.

As described above, the present invention has a chip size reduction effect by forming two floating gates in one cell to enable one cell and two bits of data memory, thereby increasing production efficiency per wafer. There is an economic advantage.

Claims (7)

Forming a field oxide film on the semiconductor substrate to define an active region, and then forming a tunnel oxide film, and forming a plurality of rectangular polysilicon patterns for floating gates in selected portions on the tunnel oxide film; Sequentially forming a dielectric film, a polyside layer, and an antireflection layer on the entire structure on which the polysilicon pattern for floating gate is formed; Forming a mask layer on the anti-reflection layer, the mask layer being formed in a direction intersecting with the field oxide layer and including a portion of each of the neighboring floating silicon polysilicon patterns; The anti-reflection layer, the polyside layer, the dielectric layer, the floating silicon polysilicon pattern, and the tunnel oxide layer may be sequentially etched through an etching process using the mask layer to form a control gate and a first and second floating gate. Forming; And A method of manufacturing a flash memory comprising the step of forming a source and a drain. The method of claim 1, And forming a polysilicon layer for spacers on the entire structure of the floating gate polysilicon pattern, and then forming polysilicon spacers on both sidewalls of the floating gate polysilicon pattern through an etching process. A method of manufacturing a flash memory. The method of claim 1, Injecting conductive impurities into the semiconductor substrate between the floating gate polysilicon patterns to form an off-set region. The method according to claim 1 or 2, And the polysilicon layer for the floating gate and the polysilicon layer for the spacer are formed to a thickness of 300 to 2000 microseconds. The method of claim 3, wherein The conductive impurity for forming the off-set region is a manufacturing method of a flash memory, characterized in that about 1E14 to 7E15 ions / cm 2 implanted. The method of claim 1, And the tunnel oxide film is formed to a thickness of 60 to 150 microseconds, and the dielectric film is formed to a thickness of 100 to 300 microseconds. The method of claim 1, And the first and the second floating gates have a size ratio of 1: 0.5 to 1.