KR20000009311A - Thin film transistor liquid crystal display and its fabricating method - Google Patents

Abstract

The gate electrode is formed on the transparent insulating substrate, and the gate insulating film covers the gate electrode. Source and drain electrodes are formed on both sides of the gate electrode, respectively, on the gate insulating layer above the gate electrode, and a doped amorphous silicon layer is formed on the source and drain electrode surfaces, and an amorphous silicon layer is formed on the doped amorphous silicon layer. It is covered with the form which overlaps this source and drain electrode. A protective film covers the gate insulating film in which the amorphous silicon layer is formed, and the contact hole which exposes a drain electrode is drilled in the protective film. An ITO pixel electrode is formed on the passivation layer to contact the drain electrode through the contact hole.

Description

Thin film transistor liquid crystal display device and manufacturing method thereof

The present invention relates to a thin film transistor liquid crystal display device and a manufacturing method thereof.

In general, a thin film transistor liquid crystal display includes a pixel region defined by a plurality of gate lines through which scan signals are transmitted, a plurality of data lines through which image signals are transmitted, and intersecting the gate lines, and portions where the gate lines and data lines intersect. And a thin film transistor. Such thin film transistor liquid crystal display devices are formed by stacking thin films one by one.

Next, a conventional thin film transistor liquid crystal display and a manufacturing method thereof will be described with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a thin film transistor liquid crystal display device according to a related art.

As shown in FIG. 1, the gate electrode 20 is formed on the transparent insulating substrate 10, and the gate insulating film 30 covers the gate electrode 20. An amorphous silicon layer 40, which is a semiconductor layer, is formed on the gate insulating layer 30 on the gate electrode 20, and the source and drain electrodes 61 and 62 are overlapped with both edges of the gate electrode 20. Formed. In this case, an ohmic contact layer, ie, a doped amorphous silicon layer, may be formed on the surface where the source and drain electrodes 61 and 62 contact the amorphous silicon layer 40 to improve electrical characteristics between the metal and the semiconductor layer. 51 and 52 are formed.

The protective insulating film 70 covers the source and drain electrodes 61 and 62, and the contact hole C1 exposing the drain electrode 62 is drilled.

The pixel electrode 80 is formed of a transparent conductive material such as indium-tin-oxide (ITO) on the protective insulating layer 70, and the drain electrode 62 is connected through the contact hole C1.

Such a conventional liquid crystal display device is manufactured by the following method.

The gate electrode 20 is formed by depositing and patterning a gate metal, and a silicon pattern (SiNx), an amorphous silicon film, and a doped amorphous silicon film are continuously deposited and then patterned to form a semiconductor pattern. Metals are deposited and patterned thereon to form source and drain electrodes 61 and 62, and a protective insulating film 70 and a pixel electrode 80 having contact holes C1 are formed.

In this manufacturing method, after the source and drain electrodes 61 and 62 are formed, the amorphous silicon layer 40 having a predetermined thickness in the process of etching the doped amorphous silicon layers 51 and 52 exposed outside the electrodes 61 and 62. In consideration of being etched and removed at the same time, the thickness of the amorphous silicon film should be kept thick, in which case the leakage current in the channel portion of the semiconductor layer increases. In addition, since it is difficult to manage the remaining thickness of the amorphous silicon layer 40 uniformly, it is difficult to maintain the characteristics of the thin film transistor uniformly. In addition, in such a structure, leakage current may occur when the protective insulating layer 70 covering the source and drain electrodes 61 and 62 is an organic insulating layer.

An object of the present invention is to maintain the thickness of the amorphous silicon layer uniformly and thinly to maintain the thin film transistor characteristics uniformly.

Another object of the present invention is to reduce the leakage current and improve the aperture ratio.

1 is a cross-sectional view of a thin film transistor liquid crystal display device according to the related art.

2 is a cross-sectional view of a thin film transistor liquid crystal display device according to an embodiment of the present invention;

3A to 3E are cross-sectional views illustrating a method of manufacturing a thin film transistor liquid crystal display according to an exemplary embodiment of the present invention in a process sequence.

In the thin film transistor liquid crystal display according to the present invention for solving this problem, the source and drain electrodes are formed under the doped amorphous silicon layer and the amorphous silicon layer.

In addition, in the method of manufacturing the thin film transistor liquid crystal display device, a metal film for forming the source and drain electrodes and a doped amorphous silicon film are continuously deposited and simultaneously etched to form the source and drain electrodes and the doped amorphous silicon layer. An amorphous silicon layer is formed thereon which overlaps the source and drain electrodes. A protective film is formed covering the amorphous silicon layer, and a pixel electrode is formed on the protective film.

The protective film covering the amorphous silicon layer may be formed of an organic insulating film of 2 μm or more.

As such, since the doped amorphous silicon layer is formed under the amorphous silicon layer, the thickness of the amorphous silicon layer can be formed thinly. Since most of the source and drain electrodes are covered under the doped amorphous silicon layer and the amorphous silicon layer, leakage current An organic insulating film can be used without concern.

Then, the thin film transistor liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the same.

2 is a cross-sectional view of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the gate electrode 20 is formed on the transparent insulating substrate 10, and the gate insulating film 30, such as a silicon nitride (SiNx) film, covers the gate electrode 20. The source and drain electrodes 63 and 64 are formed on the gate insulating layer 30 on the gate electrode 20 so as to overlap the edges of the gate electrode 20, respectively, and on the surfaces of the source and drain electrodes 63 and 64. The doped amorphous silicon layers 53 and 54 are formed, and the amorphous silicon layer 41 is covered with the source and drain electrodes 63 and 64 on the doped amorphous silicon layers 53 and 54. Here, the doped amorphous silicon layers 53 and 54 serve to improve contact characteristics between the amorphous silicon layer 41 and the source and drain electrodes 63 and 64. In addition, a region located between the source and drain electrodes 63 and 64 in the amorphous silicon layer 41 becomes a channel region for channeling current from the source electrode 63 to the drain electrode 64.

The protective film 70 covers the gate insulating film 30 on which the amorphous silicon layer 41 is formed, and the contact hole C1 exposing the drain electrode 64 is drilled through the protective film 70. An ITO pixel electrode 80 is formed on the passivation layer 70 to contact the drain electrode 64 through the contact hole C1.

A method of manufacturing a thin film transistor liquid crystal display device having such a structure will be described below with reference to FIGS. 3A to 3E.

3A to 3E are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to an exemplary embodiment of the present invention, in order of process.

As shown in FIG. 3A, the gate wiring metal is deposited and patterned on the substrate 10 to form the gate electrode 20.

Subsequently, a gate insulating film 30 is deposited on the entire surface of the gate electrode 20, and subsequently, a metal for data wiring and a doped amorphous silicon film are deposited. As described above, the doped amorphous silicon layers 53 and 54 are formed with the source and drain electrodes 63 and 64.

Next, as shown in FIG. 3C, an amorphous silicon film is deposited and patterned to form an amorphous silicon layer 41 covering the source and drain electrodes 63 and 64. In this step, the portions of the doped amorphous silicon layers 53 and 54 that are exposed out of the amorphous silicon layer 41 are removed.

As shown in FIG. 3D, an organic insulating film is applied and patterned to a thickness of 2 μm or more to form a contact hole C1 exposing the drain electrode 64.

As shown in FIG. 3E, an indium-tin-oxide (ITO) material is deposited and patterned to form a pixel electrode 80 on the protective layer 70 that contacts the drain electrode 64 through the contact hole C1.

As described above, the doped amorphous silicon layer is formed under the amorphous silicon layer to reduce the thickness of the amorphous silicon layer, thereby making it possible to uniformize the characteristics and the screen characteristics of the thin film transistor.

Further, by forming source and drain electrodes under the doped amorphous silicon layer and the amorphous silicon layer, an organic insulating film can be used as a protective film without fear of leakage current. The organic insulating layer can be maintained at a thickness of 2 μm or more, so that the coupling between the source and drain electrodes and the pixel electrode can be prevented to the maximum, and the high aperture ratio of the pixel can be realized.

Claims (7)

Transparent insulation substrate, A gate electrode formed on the substrate, A gate insulating film covering the gate electrode, A source and a drain electrode formed on the gate insulating layer on the gate electrode and overlapping both edges of the gate electrode; A doped amorphous silicon layer formed on the source and drain electrode surfaces, An amorphous silicon layer covering the doped amorphous silicon layer and overlapping the source and drain electrodes A thin film transistor liquid crystal display comprising a. In claim 1, A protective film covering the gate insulating film on which the amorphous silicon layer is formed and having a contact hole for exposing the drain electrode; And a pixel electrode formed on the passivation layer to contact the drain electrode through the contact hole. In claim 2, The protective film is a thin film transistor liquid crystal display device which is an organic insulating film. In claim 3, The protective film is a thin film transistor liquid crystal display device having a thickness of 2μm or more. Forming a gate electrode on the insulating substrate, Forming a gate insulating film covering the gate electrode; Continuously depositing a metal film and a doped amorphous silicon film on the gate insulating film, Simultaneously etching the doped amorphous silicon film and the metal film to form an ohmic contact layer, a source and a drain electrode, Depositing an amorphous silicon film, Patterning the amorphous silicon film to form an amorphous silicon layer, Forming a protective film covering the amorphous silicon layer, Forming a pixel electrode on the passivation layer, the pixel electrode being in electrical contact with the drain electrode Method of manufacturing a thin film transistor liquid crystal display device comprising a. In claim 5, The protective film is a method of manufacturing a thin film transistor liquid crystal display device formed by applying an organic insulating film. In claim 6, And the organic insulating layer is formed to a thickness of 2 μm or more.