KR20000001936A - Method for forming metal film of semiconductor element and semiconductor element manufactured by the method - Google Patents
Method for forming metal film of semiconductor element and semiconductor element manufactured by the method Download PDFInfo
- Publication number
- KR20000001936A KR20000001936A KR1019980022423A KR19980022423A KR20000001936A KR 20000001936 A KR20000001936 A KR 20000001936A KR 1019980022423 A KR1019980022423 A KR 1019980022423A KR 19980022423 A KR19980022423 A KR 19980022423A KR 20000001936 A KR20000001936 A KR 20000001936A
- Authority
- KR
- South Korea
- Prior art keywords
- metal film
- film
- insulating film
- contact hole
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자의 금속막 형성방법 및 이에 따라 제조되는 반도체소자에 관한 것이다.The present invention relates to a method for forming a metal film of a semiconductor device and a semiconductor device manufactured accordingly.
본 발명의 금속막 형성방법은, 하부구조물이 기 형성된 반도체기판 상에 절연막을 형성시킨 후, 콘택홀이 형성되도록 상기 절연막을 제거시키는 단계; 상기 콘택홀을 포함하는 반도체기판의 절연막 상에 제1금속막을 형성시킨 후, 상기 콘택홀 내부에만 제1금속막이 존재하도록 상기 제1금속막을 에치백시키는 단계; 상기 절연막의 표면 위로 상기 제1금속막의 상단부분이 드러나도록 상기 절연막을 에치백시키는 단계; 및 상기 상단부분이 드러난 제1금속막을 포함하는 반도체기판의 절연막 상에 제2금속막을 형성시키는 단계를 구비하여 이루어짐을 특징으로 한다.The metal film forming method of the present invention includes forming an insulating film on a semiconductor substrate on which a lower structure is formed, and then removing the insulating film to form a contact hole; Forming a first metal film on the insulating film of the semiconductor substrate including the contact hole, and then etching back the first metal film so that the first metal film exists only inside the contact hole; Etching back the insulating film so that an upper portion of the first metal film is exposed on the surface of the insulating film; And forming a second metal film on the insulating film of the semiconductor substrate including the first metal film on which the upper end portion is exposed.
본 발명의 반도체소자는, 반도체기판 상에 금속배선으로 형성되는 금속막 중에서 콘택홀이 형성된 영역에서의 금속막은 그 상단부가 콘택홀의 입구 위로 드러나도록 형성시켜 이루어진 것을 특징으로 한다.The semiconductor device of the present invention is characterized in that the metal film in the region where the contact hole is formed in the metal film formed of the metal wiring on the semiconductor substrate is formed so that the upper end thereof is exposed over the entrance of the contact hole.
따라서, 절연막의 단차를 최소화시켜 금속막의 형성시 발생되는 불량을 방지함으로써 반도체소자의 신뢰도가 향상되는 효과가 있다.Accordingly, the reliability of the semiconductor device is improved by minimizing the step difference of the insulating film to prevent defects generated during the formation of the metal film.
Description
본 발명은 반도체소자의 금속막 형성방법 및 이에 따라 제조되는 반도체소자에 관한 것으로서, 보다 상세하게는 절연막을 에치백(Etch Back)시켜 그 단차를 최소화시킬 수 있는 반도체소자의 금속막 형성방법 및 이에 따라 제조되는 반도체소자에 관한 것이다.The present invention relates to a method of forming a metal film of a semiconductor device and a semiconductor device manufactured according to the above, and more particularly, to a method of forming a metal film of a semiconductor device that can minimize the step by etching back the insulating film (Etch Back) It relates to a semiconductor device manufactured according to.
최근의 반도체소자는 고집적화에 따른 디자인룰(Design Rule)의 미세화로 상기 반도체소자로 제조할 수 있는 웨이퍼(Wafer) 즉, 반도체기판 상에 형성시키는 막(Film)들의 단차가 커져가고 있는 추세이다.BACKGROUND ART In recent years, semiconductor devices have a growing trend in manufacturing wafers, that is, films formed on semiconductor substrates, due to miniaturization of design rules due to high integration.
이에 따라 아이엘디막(Inter Layer Dielectric Film) 또는 아이엠디막(Inter Metal Dielectric Film) 등과 같은 절연막의 단차 또한 커져가고 있기 때문에 상기 절연막을 이용하여 형성시킬 수 있는 콘택홀(Contact Hole)의 선폭(CD : Critical Dimension)은 상대적으로 미세해지는 추세로 진행되고 있다.Accordingly, the step height of an insulating film such as an inter-layer dielectric film or an inter-metal dielectric film is also increasing, so that the line width (CD) of a contact hole that can be formed using the insulating film is increased. : Critical Dimension is progressing toward a relatively fine trend.
따라서 상기 절연막의 단차로 인한 콘택홀의 미세화로 금속배선으로 이용되는 금속막인 알루미늄막(Al Film)으로는 상기 콘택홀의 매몰이 용이하게 이루어지지 않아 최근에는 텅스텐막(W Film)을 이용하여 상기 콘택홀을 매몰시키는 공정을 수행하고 있다.Therefore, since the contact hole is not easily buried with an aluminum film, which is a metal film used for metal wiring due to the miniaturization of the contact hole due to the step difference of the insulating film, recently, the contact is made using a tungsten film (W Film). The process of burying the hole is performed.
그러나 상기 텅스텐막은 그 매몰특성은 우수하지만, 벌크(Bulk)저항이 알루미늄막보다 4배 내지 5배 정도 높은 결함을 노출하였다.However, the tungsten film is excellent in its investment characteristics, but exposed a defect of about 4 to 5 times higher bulk resistance than the aluminum film.
이에 따라 상기 콘택홀 내부에는 텅스텐막을 형성시키고, 그 상부에 알루미늄막을 형성시켜 그 매몰특성 및 벌크저항에 따른 결함을 해소하였다.As a result, a tungsten film was formed inside the contact hole, and an aluminum film was formed on the upper portion of the contact hole, thereby eliminating defects due to its investment characteristics and bulk resistance.
여기서 상기의 텅스텐막 및 알루미늄막으로 이루어지는 금속막의 형성공정은 먼저, 콘택홀을 포함하는 반도체기판의 절연막 상에 텅스텐막을 형성시킨 후, 상기 콘택홀 내부에만 텅스텐막이 존재하도록 상기 텅스텐막을 전면으로 제거시킨다.Here, in the forming process of the metal film made of the tungsten film and the aluminum film, first, a tungsten film is formed on the insulating film of the semiconductor substrate including the contact hole, and then the tungsten film is removed to the front so that the tungsten film exists only inside the contact hole. .
이러한 텅스텐막의 제거는 도1에 도시된 바와 같이 반도체기판(10) 상에 형성시킨 절연막(12)이 패턴(Pattern)에 따라서 그 단차(A)가 차이가 있었기 때문에 텅스텐막(14)의 제거가 우수함에도 불구하고 씨엠피(CMP)공정을 수행하지 못하였다.The removal of the tungsten film 14 is performed by removing the tungsten film 14 because the step A of the insulating film 12 formed on the semiconductor substrate 10 is different according to the pattern as shown in FIG. 1. Although excellent, the CMP process could not be performed.
즉, 상기 씨엠피공정은 주로 수평면에 대하여 이루어지는 공정이기 때문인 것이다.That is, the CMP process is mainly because the process is made for the horizontal plane.
따라서 상기 텅스텐막의 제거에는 주로 에치백을 이용하였으나, 상기 에치백은 언에치성 레지듀(Residue)를 제거하기 위하여 상기 텅스텐막을 오버에치(Over Etch)시키는데 이러한 텅스텐막의 오버에치는 도2에 도시된 바와 같이 오버에치시킨 텅스텐막(18)을 포함하는 반도체기판(20)의 절연막(22) 상에 형성시키는 알루미늄막(26)의 프로파일(Profile)에 영향을 끼쳤고, 후속되는 공정의 수행시 불량의 소스(Source)로 작용하였다.Therefore, the etch back is mainly used to remove the tungsten film, but the etch back overetches the tungsten film in order to remove the unetchable residue, and the overetch of the tungsten film is shown in FIG. As described above, the profile of the aluminum film 26 formed on the insulating film 22 of the semiconductor substrate 20 including the overetched tungsten film 18 was influenced and the subsequent process was performed. It acted as a source of failure.
따라서 종래의 반도체소자의 제조에서는 콘택홀을 형성시킬 수 있는 절연막의 단차로 인하여 금속막의 형성시 불량의 소스를 제공함에 따라 반도체소자의 신뢰도가 저하되는 문제점이 있었다.Therefore, in the manufacture of a conventional semiconductor device, there is a problem that the reliability of the semiconductor device is lowered by providing a source of defects when forming a metal film due to the step of the insulating film that can form the contact hole.
본 발명의 목적은, 콘택홀을 형성시킬 수 있는 절연막의 단차를 최소화시켜 금속막의 형성시 발생되는 불량을 방지하여 반도체소자의 신뢰도를 향상시키기 위한 반도체소자의 금속막 형성방법 및 이에 따라 제조되는 반도체소자를 제공하는 데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming a metal film of a semiconductor device for improving reliability of a semiconductor device by minimizing a step difference between an insulating film capable of forming a contact hole and preventing a defect occurring during formation of the metal film, and a semiconductor manufactured accordingly It is to provide a device.
도1 및 도2는 종래의 반도체소자에 형성시킨 금속막의 상태를 설명하기 위한 단면도이다.1 and 2 are cross-sectional views for explaining the state of a metal film formed in a conventional semiconductor element.
도3 및 도4는 본 발명에 따른 반도체소자의 금속막 형성방법의 일 실시예를 나타내는 단면도이다.3 and 4 are cross-sectional views showing an embodiment of a method for forming a metal film of a semiconductor device according to the present invention.
도5는 본 발명의 반도체소자에 형성시킨 금속막의 상태를 설명하기 위한 단면도이다.5 is a cross-sectional view for explaining the state of the metal film formed in the semiconductor device of the present invention.
※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing
10, 20, 30 : 반도체기판 12, 22, 32, 38 : 절연막10, 20, 30: semiconductor substrate 12, 22, 32, 38: insulating film
14, 18 : 텅스텐막 26 : 알루미늄막14, 18: tungsten film 26: aluminum film
34 : 제1금속막 36 : 제2금속막34: first metal film 36: second metal film
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 금속막 형성방법은, 하부구조물이 기 형성된 반도체기판 상에 절연막을 형성시킨 후, 콘택홀이 형성되도록 상기 절연막을 제거시키는 단계; 상기 콘택홀을 포함하는 반도체기판의 절연막 상에 제1금속막을 형성시킨 후, 상기 콘택홀 내부에만 제1금속막이 존재하도록 상기 제1금속막을 에치백시키는 단계; 상기 절연막의 표면 위로 상기 제1금속막의 상단부분이 드러나도록 상기 절연막을 에치백시키는 단계; 및 상기 상단부분이 드러난 제1금속막을 포함하는 반도체기판의 절연막 상에 제2금속막을 형성시키는 단계를 구비하여 이루어짐을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a metal film of a semiconductor device, the method including: forming an insulating film on a semiconductor substrate on which a lower structure is formed, and then removing the insulating film to form a contact hole; Forming a first metal film on the insulating film of the semiconductor substrate including the contact hole, and then etching back the first metal film so that the first metal film exists only inside the contact hole; Etching back the insulating film so that an upper portion of the first metal film is exposed on the surface of the insulating film; And forming a second metal film on the insulating film of the semiconductor substrate including the first metal film on which the upper end portion is exposed.
상기 절연막은 일반적인 아이엘디막 또는 아이엠디막 등으로 이용할 수 있는 산화막인 것이 바람직하다.It is preferable that the insulating film is an oxide film which can be used as a general ILD film or an IMD film.
상기 제1금속막은 콘택홀의 매몰특성이 우수한 텅스텐막인 것이 바람직하고, 상기 제2금속막은 콘택저항 및 벌크저항 등이 낮은 알루미늄막이 바람직하다.Preferably, the first metal film is a tungsten film having excellent buried characteristics of the contact hole, and the second metal film is preferably an aluminum film having low contact resistance, bulk resistance, and the like.
본 발명에 따른 반도체소자는, 반도체기판 상에 금속배선으로 형성되는 금속막 중에서 콘택홀이 형성된 영역에서의 금속막은 그 상단부가 콘택홀의 입구 위로 드러나도록 형성시켜 이루어진 것을 특징으로 한다.The semiconductor device according to the present invention is characterized in that the metal film in the region where the contact hole is formed in the metal film formed of the metal wiring on the semiconductor substrate is formed so that the upper end thereof is exposed over the entrance of the contact hole.
이하, 본 발명의 구체적인 실시예를 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도3 및 도4는 본 발명에 따른 반도체소자의 금속막 형성방법의 일 실시예를 나타내는 단면도이고, 도5는 본 발명의 반도체소자에 형성시킨 금속막의 상태를 설명하기 위한 단면도이다.3 and 4 are cross-sectional views showing one embodiment of a method for forming a metal film of a semiconductor device according to the present invention, and FIG. 5 is a cross-sectional view for explaining a state of a metal film formed in the semiconductor device of the present invention.
먼저, 도3은 하부구조물이 기 형성된 반도체기판(30) 상에 절연막(32)이 형성되어 있고, 상기 절연막(32)을 이용하여 패턴으로 형성시킨 콘택홀 내부에 제1금속막(34)이 매몰되어 있는 상태를 나타내고 있다.First, in FIG. 3, an insulating film 32 is formed on a semiconductor substrate 30 on which a lower structure is formed, and a first metal film 34 is formed in a contact hole formed in a pattern using the insulating film 32. The state of being buried is shown.
그리고 도4는 상기 제1금속막(34)을 포함하는 반도체기판(30)의 절연막(32) 상에 제2금속막(36)이 형성되어 있는 상태를 나타내고 있다.4 shows a state in which the second metal film 36 is formed on the insulating film 32 of the semiconductor substrate 30 including the first metal film 34.
여기서 본 발명의 상기 절연막(32)은 일반적인 아이엘디막 또는 아이엠디막 등으로 이용하는 산화막을 형성시킬 수 있다.Here, the insulating film 32 of the present invention can form an oxide film used as a general ILD film or an IMD film.
또한 본 발명의 상기 제1금속막(34)은 콘택홀의 매몰특성이 우수한 텅스텐막을 상기 제2금속막(36)은 콘택저항 및 벌크저항 등이 낮은 알루미늄막을 형성시킬 수 있다.In addition, the first metal layer 34 of the present invention may form a tungsten film having excellent buried characteristics of a contact hole, and the second metal layer 36 may form an aluminum film having low contact resistance and bulk resistance.
이러한 구성으로 이루어지는 본 발명은 먼저, 하부구조물이 기 형성된 반도체기판(30) 상에 산화막 등으로 이루어지는 절연막(32)을 형성시킨 후, 콘택홀이 형성되도록 상기 절연막(32)을 제거시킨다.According to the present invention having such a structure, first, an insulating film 32 made of an oxide film or the like is formed on a semiconductor substrate 30 on which a lower structure is formed, and then the insulating film 32 is removed to form a contact hole.
이어서, 상기 콘택홀을 포함하는 반도체기판(30)의 절연막(32) 상에 텅스텐막으로 이루어지는 제1금속막(34)을 형성시킨 후, 상기 콘택홀 내부에만 제1금속막(34)이 존재하도록 상기 제1금속막(34)을 상기 절연막(32)의 표면까지로 에치백시킨다.Subsequently, after the first metal film 34 made of a tungsten film is formed on the insulating film 32 of the semiconductor substrate 30 including the contact hole, the first metal film 34 exists only inside the contact hole. The first metal film 34 is etched back to the surface of the insulating film 32 so as to be covered.
여기서 상기 제1금속막(34)의 에치백은 언에치성 레지듀를 제거하기 위하여 오버에치시키는 것이 일반적인 것으로써, 상기 콘택홀의 입구보다 조금 하부에 상기 제1금속막(34)이 존재하도록 에치백시킬 수 있다.In this case, the etch back of the first metal layer 34 is generally over-etched to remove the unetchable residue, so that the first metal layer 34 exists slightly below the inlet of the contact hole. Can be etched back.
그리고 도3에 도시된 바와 같이 상기 콘택홀 내부에 존재하는 제1금속막(34)의 상단부분이 절연막(32)의 표면 위로 드러나도록 상기 절연막(32)을 표면으로부터 소정의 깊이까지로만 에치백시킨다.As shown in FIG. 3, the insulation layer 32 is etched back from the surface to a predetermined depth so that an upper end portion of the first metal layer 34 inside the contact hole is exposed on the surface of the insulation layer 32. Let's do it.
여기서 상기 절연막(32)은 두께 등은 작업자가 상기 에치백의 수행 등을 고려함으로써 용이하게 결정할 수 있다.In this case, the thickness of the insulating layer 32 can be easily determined by the operator considering the performance of the etch back.
계속해서 상기 상단부분이 드러난 제1금속막(34)을 포함하는 반도체기판(30)의 절연막(32) 상에 알루미늄막으로 이루어지는 제2금속막(36)을 형성시킨다.Subsequently, a second metal film 36 made of an aluminum film is formed on the insulating film 32 of the semiconductor substrate 30 including the first metal film 34 on which the upper portion is exposed.
이렇게 이루어진 본 발명은 상기 제1금속막(34) 및 제2금속막(36)으로 이루어지는 금속막의 형성시 상기 절연막(32)의 단차로 인한 불량을 최소화시킬 수 있다.According to the present invention, the defect caused by the step of the insulating film 32 can be minimized when the metal film formed of the first metal film 34 and the second metal film 36 is formed.
즉, 본 발명은 상기와 같은 금속막의 형성시 상기 절연막(32)의 단차 및 콘택홀의 미세화로 인하여 그 프로파일 등에 영향을 끼치는 등의 불량을 최소화시킬 수 있다.That is, the present invention can minimize defects such as affecting the profile due to the step difference of the insulating film 32 and the miniaturization of the contact hole when forming the metal film as described above.
또한 도5에 도시된 바와 같이 후속되는 공정의 수행으로 상기 제2금속막(36) 상에 형성시키는 절연막(38)의 패턴인 비아콘택홀(Via Contact Hole)에서 발생할 수 있는 금속막(도시되지 않음)의 찌그러짐 현상 등과 같은 불량을 최소화시킬 수 있다.In addition, as shown in FIG. 5, a metal film that may occur in a via contact hole, which is a pattern of an insulating film 38 formed on the second metal film 36 by performing a subsequent process (not shown). Defects such as distortion) can be minimized.
그리고 상기와 같이 단차를 최소화시키기 위하여 금속막의 형성공정에 상감기법을 활용한 최근의 반도체소자 제조방법인 다마신공정(Damascene Process) 등에 적극적으로 활용할 수 있다.In order to minimize the step as described above, it can be actively used in the damascene process (Damascene Process), which is a recent method of manufacturing a semiconductor device using the damascene method in the metal film forming process.
따라서, 본 발명에 의하면 콘택홀을 형성시킬 수 있는 절연막의 단차를 최소화시켜 금속막의 형성시 발생되는 불량을 방지함으로써 반도체소자의 신뢰도가 향상되는 효과가 있다.Therefore, according to the present invention, the reliability of the semiconductor device is improved by minimizing the step difference of the insulating film capable of forming the contact hole, thereby preventing defects generated during the formation of the metal film.
이상에서 본 발명은 기재된 구체예에 대해서만 상세히 설명되었지만 본 발명의 기술사상 범위 내에서 다양한 변형 및 수정이 가능함은 당업자에게 있어서 명백한 것이며, 이러한 변형 및 수정이 첨부된 특허청구범위에 속함은 당연한 것이다.Although the present invention has been described in detail only with respect to the described embodiments, it will be apparent to those skilled in the art that various modifications and variations are possible within the technical scope of the present invention, and such modifications and modifications are within the scope of the appended claims.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980022423A KR20000001936A (en) | 1998-06-15 | 1998-06-15 | Method for forming metal film of semiconductor element and semiconductor element manufactured by the method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980022423A KR20000001936A (en) | 1998-06-15 | 1998-06-15 | Method for forming metal film of semiconductor element and semiconductor element manufactured by the method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000001936A true KR20000001936A (en) | 2000-01-15 |
Family
ID=19539565
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980022423A Withdrawn KR20000001936A (en) | 1998-06-15 | 1998-06-15 | Method for forming metal film of semiconductor element and semiconductor element manufactured by the method |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20000001936A (en) |
-
1998
- 1998-06-15 KR KR1019980022423A patent/KR20000001936A/en not_active Withdrawn
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8629560B2 (en) | Self aligned air-gap in interconnect structures | |
| KR100416596B1 (en) | Method of manufacturing interconnection wire in semiconductor device | |
| JPH0645457A (en) | Method for manufacture of contact via in integrated circuit | |
| KR100641502B1 (en) | Contact formation method using dual damascene process in semiconductor device manufacturing | |
| US20080299718A1 (en) | Damascene process having retained capping layer through metallization for protecting low-k dielectrics | |
| US7569481B2 (en) | Method for forming via-hole in semiconductor device | |
| JP3312604B2 (en) | Method for manufacturing semiconductor device | |
| JPH10284600A (en) | Semiconductor device and fabrication thereof | |
| US6554002B2 (en) | Method for removing etching residues | |
| US20020106885A1 (en) | Method of fabricating a slot dual damascene structure without middle stop layer | |
| KR20000001936A (en) | Method for forming metal film of semiconductor element and semiconductor element manufactured by the method | |
| US6413856B1 (en) | Method of fabricating dual damascene structure | |
| KR20030001356A (en) | Dual damascene circuit with upper wiring and interconnect line positioned in regions formed as two layers including organic polymer layer and low-permittivity layer | |
| US6468897B1 (en) | Method of forming damascene structure | |
| KR100493850B1 (en) | Metal film formation method of semiconductor device | |
| US6444573B1 (en) | Method of making a slot via filled dual damascene structure with a middle stop layer | |
| KR20010058209A (en) | Method of forming metal line with dual damascene process | |
| US20050142856A1 (en) | Method of fabricating interconnection structure of semiconductor device | |
| US6391766B1 (en) | Method of making a slot via filled dual damascene structure with middle stop layer | |
| KR0154190B1 (en) | Tungsten-Plug Formation Method of Semiconductor Device | |
| KR20050064668A (en) | Method of forming a dual damascene pattern | |
| KR20010025972A (en) | Method of forming interconnection layer in semiconductor device | |
| KR100701779B1 (en) | Contact formation method of semiconductor device | |
| KR20030002942A (en) | Method for forming metal interconnection in semiconductor device | |
| KR20030058846A (en) | Method for manufacturing via hole of semiconductor device and semiconductor device thereby |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19980615 |
|
| PG1501 | Laying open of application | ||
| PC1203 | Withdrawal of no request for examination | ||
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |