KR20000001189A - Program method of nonvolatile memory device - Google Patents

Abstract

PURPOSE: A program method of a non volatile memory device is provided to reduce leakage current flowing to an unselected cell. CONSTITUTION: In cell programming, a program method according to the present invention loads either the same voltages or the different voltages having same polarity to a selected bit line and a common source line, thereby a leakage current flowing to an unselected cell as well as a current consumed in programming can be reduced.

Description

How to Program a Nonvolatile Memory Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to nonvolatile semiconductor memory devices, and more particularly, to a method of programming an EEPROM cell.

The semiconductor memory device may be classified into a volatile memory device in which data is lost when power is removed from a chip, and a nonvolatile memory device in which data stored once is preserved even when power is removed. Among these non-volatile memory devices, EPyrom (Electrically Programmable Read Only Memory) can electrically program data, but in order to erase the programmed data, the chip needs to be separated from the board to scan ultraviolet rays. Accordingly, the flash Y pyrom which can compensate for the disadvantage of the above pyramid and electrically program and erase the data was introduced in IEDM P.464 in 1984. The flash Y pyrom cell is a device that can be electrically programmed and erased without being separated from the circuit board. The structure of the flash Y pyrom cell is simple, and the manufacturing cost per unit memory is low, and the refresh operation for long-term data retention is unnecessary. Due to the advantage, the demand is gradually increasing in this field.

The flash Y pyrom may be divided into a nand type and a noah type according to a form in which a cell is connected to a bit line. In the NAND flash Y pyrom, a plurality of cells are connected in series to form a unit string. In the NOR flash Y pyrom, each cell is connected in parallel between a bit line and a ground line. Such a quinoa flash ypyrom cell is disclosed in US Pat. No. 4,203,158, the structure of which is shown in FIG. Referring to FIG. 1, a stacked gate in which a gate oxide layer 12, a floating gate 14, an interlayer insulating layer 16, and a control gate 18 are sequentially formed on a semiconductor substrate 10 doped with trivalent impurities such as boron (B) is illustrated. . Diffusion regions having a conductivity type opposite to the semiconductor substrate 10, that is, a source region 20 and a drain region 21, are formed under both sides of the stacked gate.

A structure of a quinoa flash ypyrom cell having another type of stacked gate structure is disclosed in US Pat. No. 4,698,787, the structure of which is shown in FIG. Reference numeral 30 denotes a semiconductor substrate doped with a P-type impurity, 32 a gate oxide film, 34 a floating gate, 36 an interlayer insulating film, 38 a control gate, 40 and 42 respectively a source and a drain region, and 41 It is a lightly doped region for further relaxing the electric field of the source region 40 at the reverse bias.

During operation of the cells, the program is performed by forming hot-electrons in the drain region and injecting them into the floating gate 34 through the gate oxide layer. The erasing operation of the cells is performed using Fowler-Nordheim (FN) tunneling. To discharge the electrons injected into the floating gate into the source region. As described above, the noah type flash Y pyrom has an advantage of being electrically programmable and erased, but a high voltage is required to generate heat-electrons for programming data, and the current consumption is also very high. . Since the program speed is proportional to the flux of electrons injected into the floating gate, a large amount of electrons must be injected into the gate electrode for a fast program speed. This requires high longitudinal and low transverse electric fields. Therefore, in order to satisfy these conditions, it is inevitable to apply high voltages of about 6V and 12V to the drain and control gate regions, respectively. In general, since the voltage of the power source applied to the chip is about 3.3V to 5V, a booster circuit for converting the voltage into a high voltage of about 6V to 12V should be separately provided. However, if the boost circuit is formed in the chip, the complexity of the circuit configuration as well as the chip density may be undesirable.

FIG. 3 is an equivalent circuit diagram of a cell array including unit cells shown in FIG. 2, and FIG. 4 is an equivalent circuit diagram of unit cells shown in FIG. First, referring to FIG. 3, a plurality of bit lines B / L1, B / L2... B / Ln and word lines W / L1, W / L2, and W / L3 formed at regular intervals. Unit cell transistors having a structure in which the floating gate 34 and the control gate 38 are sequentially stacked are formed in regions where W / Ln is orthogonal. The bias conditions applied for programming, erasing, and reading the quinoa flash Y pyrom are shown in Table 1 below.

program elimination Reading Select bitline 5 V Floating 1 V Unselected bitlines Floating Floating Floating Select wordline 10 V -12V Vcc Unselected wordlines 0 V Floating 0 V Common sourceline 0 V 5 V 0 V Board (Bulk) 0v 0 V 0 V

At this time, when a voltage of 5 V is applied to the selected bit line B / L1 and a voltage of 12 V is applied to the selected word line W / L1, the bit lines B / L1 and W / L2 to n where no voltage is applied cross. The floating gate of the cell B present in the region is induced with a capacitive coupling voltage as shown in FIG. That is, as shown in FIG. 4, the drain voltage is capacitively coupled to the floating gate, so that a potential is maintained at the floating gate. In this case, if the voltage appearing at the floating gate is Vfg as shown in Fig. 4, Vfg is expressed by the following equation (1).

vfg = Υcg * Vcg + Υd + Υs * Vs + Υb * Vb

Here, Vcg is the voltage of the control gate, Vd is the drain voltage, Vs is the source voltage. In addition, Vb is the substrate voltage, kcg is the ratio of the total capacitance Ctotal to the capacitance Cono of the interlayer insulating film, Υd is the ratio of Ctotal to the drain capacitance Cd, and Υs is the ratio of Ctotal to the source capacitance Cs. Is the ratio of Ctotal to the bulk capacitance Cb. Here, Ctotal is expressed as Equation 2 below.

Ctotal = Cono + Cd + Cb + Cs

Since the non-selected cell becomes Vcg = Vb = Vs = 0 during programming, Equation 1 is briefly expressed by Equation 3 below. In other words,

Vfg = Υd * Vd

Is given by The floating gate voltage induced by the capacitive coupling described above causes weak inversion or strong inversion below the channel of the unselected cells. When the voltage level of the induced floating gate is greater than or equal to the threshold voltage Vth viewed from the floating gate, the channel is completely inverted, so that a so-called drain leakage current phenomenon occurs in which the drain current of the non-selected cell is rapidly increased. This lowers the voltage applied to the bit line to program the selected cell. In order for the cell to be programmed, a voltage above a predetermined voltage must be applied to the bit line, but if the applied voltage decreases due to the drain leakage current, a failure occurs in which the selected cell is not programmed. 5 is a graph showing a drain turn-on phenomenon indicating such a drain leakage current. That is, the leakage current flowing through the drain is measured while sweeping from 0V for the condition where the cell B is placed under the program condition, the word line, the source and the substrate, and the drain voltage from 0V. As shown in the graph, the leakage current increases as the drain voltage increases. Since the leakage current flowing through the drain at a voltage of 5 V, which is a normal program condition, is about 100 μA, when the number of cells connected to one bit line is 1 Kb, the leakage current is generated in all non-selected cells that share the selected bit line. The total leakage current reaches 1023 x 100μA. This is about 300 times larger than 300μA for programming the selected cell. However, if the voltage applied to the bit line is reduced in order to reduce the leakage current, the program speed of the selected cell is decreased or a defect that is not programmed is generated.

Therefore, there is an urgent need in the art for an improved programming method that can reduce leakage current and prevent defective programming of cells.

Accordingly, an object of the present invention is to provide a program method of a nonvolatile memory device that can solve the above-described conventional problems.

Another object of the present invention is to provide a program method capable of reducing the drain leakage current flowing in an unselected cell.

In order to achieve the above object, in the present invention, a unit cell having a stacked gate structure in which a floating gate and a control gate are stacked is present in each region where a bit line and a word line cross each other to form a cell array. A program method; And applying a voltage having the same magnitude or the same polarity to the drain terminal and the source terminal of the selected cell of the unit cells.

In addition, in order to achieve the above object, in the present invention, in the method of programming a non-volatile memory device in which the unit memory cells having a floating gate for data storage surrounded by an insulating film in the form of a matrix to form a cell array: the unit memory cell Selecting one of the word lines connected to the control gates of the plurality of control lines, and selecting one of the unit memory cells by selecting one of bit lines to which unit memory cells connected to different word lines are commonly connected; Applying a voltage set to a word line and a bit line connected to the selected cell to activate the selected cell; And applying a voltage having the same level or a voltage of the same polarity as the voltage applied to the bit line to the common source line of the selected cell.

1 is a cross-sectional structural view of a stacked flash Y pyrom cell applied to the present invention

2 is a cross-sectional structural view of still another stacked flash Y pyrom cell applied to the present invention

FIG. 3 is an equivalent circuit diagram of a cell array constructed using the cells shown in FIGS. 1 and 2.

FIG. 4 is an equivalent circuit diagram illustrating the capacitive coupling of FIG. 3. FIG.

5 is a graph showing the drain turn-on phenomenon of the cell due to leakage current

Figure 6 is an equivalent circuit diagram of a cell array showing the voltage applied to each line of the cell transistor during programming according to the present invention.

7 is a graph showing a program result of a cell

8 is a structure of a test cell for explaining the phenomenon shown in FIG.

9 is a graph illustrating a comparison of gate current values measured after turning on the test cell according to a conventional bias application condition and a bias application condition of the present invention.

10 is a graph illustrating a ratio of gate current and drain current values measured after turning on the test cell according to a conventional bias application condition and a bias application condition of the present invention.

11 is a graph illustrating program characteristics of a cell in which a substrate is grounded or a negative voltage is applied thereto.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The bias conditions applied for programming, erasing and reading quinoa flash ypyrom according to the present invention are shown in Table 2 below.

program elimination Reading Select bitline 5 V Floating 1 V Unselected bitlines Floating Floating Floating Select wordline 10 V -12V Vcc Unselected wordlines 0 V Floating 0 V Common sourceline 5 V 5 V 0 V Board (Bulk) 0 V 0 V 0 V

Conventionally, 0 V is applied to the common source line during cell programming, but the present invention applies the same voltage to the selection bit line and the common source line as shown in Table 2 above. Alternatively, the leakage current in the non-selected cell is prevented by applying a voltage having the same polarity to the selection bit line and the common source line even though the voltage level is not the same as the drain.

FIG. 6 is an equivalent circuit diagram of a cell array showing a voltage applied to each line of a cell transistor during programming according to the present invention, based on Table 2 above. Referring to the drawings, 5V is applied to the selected bit line B / L1 and 10V is applied to the selected word line W / L1 during programming, and the unselected bit line B / L2 is floating and the unselected word lines W / L2 to n are grounded. It is a state. As the core of the present invention, a voltage of 5V is applied to the common source line of the cell array in the same manner as the selection bit line B / L1. That is, 5V is applied to the drain terminal D of the cell A which shares the selection bit line and the selection word line, and 10V is applied to the gate terminal G. The voltage of 5V is applied to the source terminal S of the cell B which shares the bit line with the selected cell A but does not share the word line by applying 5V to the common source line CSL, so that the drain and the source potential of the selected cell A are equal. do. Therefore, it can be seen that no current flows between two terminals having the same potential of the selected cell A. As described above, in the present invention, the same voltage is applied to the selection bit line and the common source line to prevent the drain leakage current phenomenon in which the current leaks through the cell B when programming the cell A. In addition, even when voltages of different voltages are applied to the selection bit line and the common common source line, leakage current may be reduced by a body effect even when a voltage having the same polarity is applied.

FIG. 7 is a graph showing a comparison of the results of programming a cell under the conventional program conditions shown in Table 1 and the program conditions of the present invention shown in Table 2. FIG. Lines L1 and L2 represent cell program rates according to the conventional method, and lines L3 and L4 represent cell program rates according to the present invention. As shown in the graph, it can be seen that the program rate is almost the same as the conventional program result of applying VD only to the drain of the cell A and the program result of applying the same voltage to the drain and the source.

FIG. 8 illustrates the structure of a test cell used to measure the gate current under program conditions to illustrate the effect of the present invention having the same program speed as shown in FIG. 7 and significantly reducing current consumption during programming. Indicates. The control gate and the floating gate may verify the result of FIG. 7 of the cell by comparing the gate current values measured under the conventional program condition and the program condition of the present invention in the test cell electrically connected to each other.

9 is a graph illustrating a comparison of gate current values measured in the test cell of FIG. 8 according to a conventional program bias application condition and a bias application condition of the present invention. In more detail, the measurement condition of the line L5 is a gate current measured under a conventional bias application condition, which is a result of applying 4V to the drain, 0V to the source and the substrate, and sweeping the gate voltage from 0V to 8V. The line L6 is a gate current measured under the application conditions of the present invention, and a voltage of 4V is simultaneously applied to the drain and the source, and the gate voltage is sweeped from 0V to 8V. It can be seen that the gate current Ig representing the program rate of the cell is almost the same level as the bias condition of the present invention and the conventional bias condition as shown in the graph.

FIG. 10 is a graph illustrating the ratio Ig / Id of the gate current to the drain current measured at the drain terminal during the gate current measurement by driving the test cell of FIG. 8 under the same bias condition as in FIG. 9. Line L7 is the result according to the conventional bias application condition and line L8 is the result according to the application condition of the present invention. In order to obtain the gate current Ig used directly in the program, it is necessary to consume the current Id, and the ratio Ig / Id of these two currents is an important value to quantify the program efficiency. It can be seen that it is about 10 ⁷ times or more than the typical value of about 1.OE-9. This means that when the cell is programmed with the bias application condition according to the present invention, the current consumption in the drain-source is reduced to about 10 ⁷ times or more.

Under the program conditions of the present invention described above, program characteristics can be further improved by applying a negative voltage to the substrate, which is shown in the graph of FIG. Lines L9 and L10 show results when a voltage of 0 V is applied to the bulk, and lines L11 and L12 show results when a negative voltage of -2 V is applied. As such, the program speed is remarkably improved as the absolute value of the substrate voltage increases, and the threshold voltage Vth of the cell remains constant even when the program time increases. Therefore, it can be seen that the threshold voltage Vth level of the cell programmed during cell programming can be easily adjusted, which can be applied to multi-level cells.

As described above, in the cell program method, the problem of leakage current of an unselected cell is solved by applying a voltage having the same polarity or a voltage having the same polarity to the selected bit line and the common source line even though the voltages of the same magnitude are different. can do.

Although described with reference to the preferred embodiment of the present invention as described above, those skilled in the art will be variously modified and modified within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. It will be appreciated that this can be changed.

Claims (6)

A method of programming a nonvolatile memory device in which a unit cell having a stacked gate structure in which a floating gate and a control gate are stacked is present in a region where a bit line and a word line cross each other to form a cell array. And applying a voltage having the same magnitude or a voltage having the same polarity to the drain terminal and the source terminal of the selected cell among the unit cells. The method of claim 1, further comprising applying a voltage having the same polarity as the voltage applied to the drain terminal and the source terminal to the floating gate terminal of the selection cell. The program method of claim 2, further comprising applying a voltage having a polarity opposite to that applied to the drain terminal and the source terminal to the substrate of the selection cell. The first conductive semiconductor substrate has a drain and source region of a conductive type opposite to the semiconductor substrate, and has a first conductive layer formed between the semiconductor substrate and a first insulating film, and the first conductive layer is formed between the first conductive layer and the first conductive layer. A plurality of bit lines in which unit cells having a second conductive layer formed through a second insulating layer are arranged in parallel at regular intervals and a plurality of word lines arranged at regular intervals in a direction perpendicular to the bit lines cross each other. In the method of programming a nonvolatile memory device located in an area and forming a cell array: And applying a voltage having the same magnitude or a voltage having the same polarity to the drain and the source region of the selected cell among the unit cells. The method of claim 4, wherein a voltage having the same polarity as the voltage applied to the drain and the source is applied to the second conductive layer of the selected unit cell, and a voltage applied to the drain terminal and the source terminal is applied to the substrate of the unit cell. And applying a voltage of opposite polarity. A method of programming a nonvolatile memory device in which unit memory cells having a floating gate for data storage surrounded by an insulating layer exist in a matrix to form a cell array: Selecting one of the word lines connected to the control gates of the unit memory cells, and selecting one of the bit lines to which the unit memory cells connected to different word lines are commonly connected; Steps; Applying a voltage set to a word line and a bit line connected to the selected cell to activate the selected cell; And applying a voltage having the same level or a voltage of the same polarity as the voltage applied to the bit line to the common source line of the selected cell.