KR19990079930A - Voltage-Controlled Oscillators in Phase-Locked Loop Circuits - Google Patents

Abstract

The voltage controlled oscillator according to the invention accepts an external voltage and differs in response to first and second reference voltages having a voltage level complementary to the first, second and third switch signals supplied from the outside. A switch circuit for selectively outputting first, second and third currents having a magnitude; Receives the first, second and third currents, and in response to a control signal supplied from the outside and the second reference voltage, to the magnitude of the first, second and third currents selectively supplied from the switch circuit. An oscillation circuit for outputting an oscillation signal whose frequency range is determined; An output buffer for receiving the oscillation signal and outputting the oscillation signal. The switch circuit may selectively supply currents required when the voltage controlled oscillator operates at a low voltage, thereby reducing the influence of the voltage output from the circuit of the previous step of supplying the input signal.

Description

VOLTAGE CONTROLLED OSCILLATOR OF PHASE LOCKED LOOP CIRCUIT

The present invention relates to a phase locked loop circuit, and more particularly, to a voltage controlled oscillator capable of operating even at a low voltage.

Charge Pump Phase Locked Loop (CPPLL) is a system that synchronizes the input and output frequencies. Among the circuits provided in the phase locked loop circuit, a voltage controlled oscillator generally refers to an oscillation circuit that changes an oscillation frequency by an externally applied control voltage. In recent years, the oscillation frequency is directly proportional to the control DC voltage. Therefore, the voltage controlled oscillator converting the control voltage into frequency, that is, the V-F conversion circuit, plays an important role as an interface with the digital circuit.

Referring to FIG. 1, a commonly used phase locked loop circuit includes a phase frequency comparator 100, a charge pump circuit 200, a loop filter 300, a voltage controlled oscillator 400, and a feedback driver 500. It is. The phase frequency comparator 100 compares a reference frequency (Fref) input from the outside with a feedback frequency (Ffeed) output from the feedback driver (500) to generate an UP signal and a down (DN) signal. Supply to the charge pump circuit 200. The charge pump circuit 200 receives the up signal and the down signal from the phase frequency comparator 100 and supplies a pumping current Ip to the loop filter 300. The loop filter 300 receives the pumping current Ip from the charge pump 200 to filter the current. The voltage controlled oscillator 400 outputs a frequency Fout corresponding to the current supplied from the loop filter 300. The feedback amplifier 500 supplies the frequency Fout output from the voltage controlled oscillator 400 to the phase frequency comparator 100.

Referring to FIG. 2, the voltage controlled oscillator according to the related art includes a current mirror 410, a ring oscillator 420, and an output buffer 430. The current mirror 410 replaces the voltage PW output from the loop filter 300 with a current by controlling the first control signal. The ring oscillator 420 converts the current output from the current mirror 410 into a frequency Fout by controlling the second control signal and outputs the frequency. The output buffer 430 outputs the frequency Fout output from the ring oscillator 430 to an internal circuit.

Referring to Figure 3, the frequency of the voltage controlled oscillator according to the prior art shows a frequency of 20MHz ~ 170MHz. Here, the magnitude or linearity of the gain of the voltage controlled oscillator is an important problem in the noise characteristics of the entire phase locked loop circuit (PLL). The smaller the gain of the voltage controlled oscillator, that is, the lower the sensitivity of the voltage output from the loop filter, the better the noise characteristic. In addition, as the voltage goes down to a lower voltage, the range of voltages that can be output from the loop filter is limited, making it difficult to obtain a desired frequency in the voltage controlled oscillator. In order to solve this problem, the conventional phase locked loop circuit employs a method of dividing a divider by connecting a divider to an output terminal of a voltage controlled oscillator. However, in the use of the frequency divider, noise due to frequency division occurs, which causes limitations due to the characteristics of the noise.

Therefore, the conventional voltage controlled oscillator fails to output a desired frequency when using a low voltage.

It is therefore an object of the present invention to provide a voltage controlled oscillator capable of operating at low voltages.

1 is a block diagram showing the configuration of a general phase locked loop circuit;

2 is a circuit diagram showing a circuit configuration of a voltage controlled oscillator according to the prior art;

3 is a waveform diagram showing frequency characteristics of a voltage controlled oscillator according to the prior art;

4 is a circuit diagram showing a circuit configuration of the voltage controlled oscillator of the present invention;

5 is a waveform diagram showing the frequency characteristics of the voltage controlled oscillator according to the present invention.

* Explanation of symbols on the main parts of the drawings

100: phase frequency comparator 200: charge pump circuit

300 loop filter 400 voltage controlled oscillator

410: current mirror 420: ring oscillator

430 output buffer 440 switch circuit

500: feedback driver

(Configuration)

According to one aspect of the present invention for achieving the object as described above, the first and second receiving the external voltage, and having a voltage level complementary to the first, second and third switch signals supplied from the outside A switch circuit for selectively outputting first, second and third currents having different magnitudes in response to the reference voltages; Receives the first, second and third currents, and in response to a control signal supplied from the outside and the second reference voltage, to the magnitude of the first, second and third currents selectively supplied from the switch circuit. An oscillation circuit for outputting an oscillation signal whose frequency range is determined; An output buffer for receiving the oscillation signal and outputting the oscillation signal.

In this embodiment, the switch circuit comprises: a first switch circuit for selectively outputting the first current in response to the first switch signal and the second reference voltage; A second switch circuit for selectively outputting the second current different in magnitude from the first current in response to the first and second switch signals and the first reference voltage; And a third switch circuit for selectively outputting the third current having a magnitude different from the first and second currents in response to the first and third switch signals.

(Action)

With such a device, it is possible to obtain the output of the desired frequency at low voltage by adjusting the magnitude of the current supplied through the switch circuit.

(Example)

Hereinafter, reference will be made in detail with reference to FIGS. 4 to 5 according to an embodiment of the present invention.

4 is a circuit diagram showing the circuit configuration of the voltage controlled oscillator of the present invention.

Referring to FIG. 4, the voltage controlled oscillator according to the present invention includes a switch circuit 440, a ring oscillator 420, and an output buffer 430. The switch circuit 440 includes a first switch circuit 441, a second switch circuit 442, a third switch circuit 443, and a capacitor 444. The first switch circuit 441 includes two PMOS transistors PM1 and PM4. The PMOS transistor PM1 is connected between a voltage power supply and the PMOS transistor PM4. The PMOS transistor PM4 is connected between the PMOS transistor PM1 and the ground power supply VSS.

The second switch circuit 442 includes PMOS transistors PM2, PM5, PM6, and PM7 and NMOS transistors NM1 and NM2. The PMOS transistor PM2 is connected between the voltage power supply VDD and the PMOS transistor PM7. The PMOS transistor PM5 is connected between the voltage power supply VDD and the NMOS transistor NM1. The PMOS transistor PM6 is connected between the voltage power supply VDD and the NMOS transistor NM2. The PMOS transistor PM7 is connected between the PMOS transistor PM2 and the input terminal of the ring oscillator 420. The NMOS transistor NM1 is connected between the PMOS transistor PM5 and the ground power supply VSS. The NMOS transistor NM2 is connected between the PMOS transistor PM6 and the ground power supply VSS.

The third switch circuit 443 includes PMOS transistors PM3, PM8, and PM9 and an NMOS transistor NM3. The PMOS transistor PM3 is connected between the voltage power supply VDD and the PMOS transistor PM9. The PMOS transistor PM8 is connected between the voltage power supply VDD and the NMOS transistor NM3. The PMOS transistor PM9 is connected between the PMOS transistor PM3 and the input terminal of the ring oscillator 420. The capacitor 444 is connected between the input terminal of the ring oscillator 420 and the ground power source VSS.

The ring oscillator 420 includes nine inverters 421, 422,..., 428, 429. The inverters 421, 422,..., 428, 429 have one terminal connected to an output terminal of the switch circuit 440 and the other terminal connected to the ground power supply VSS. The inverters 421, 422,..., 428, 429 are connected in parallel between the switch circuit 440 and the output buffer 430. The output buffer 430 includes two inverters 431 and 432. One terminals of the inverters 431 and 432 are connected to the voltage power supply VDD and the other terminals are connected to the ground power supply VSS. The inverters 431 and 432 are connected in parallel between the ring oscillator 420 and the output terminal.

Hereinafter, the operation of the voltage controlled oscillator of the present invention will be described with reference to FIG.

Referring back to FIG. 4, the switch circuit 440 of the voltage controlled oscillator of the present invention receives the external voltage VDD and receives first, second, and third switch signals S1, S2, S3, and first. And supply the first, second and third currents to the ring oscillator 420 by controlling the second reference voltages VR1 and VR2. The first switch circuit 441 converts the external voltage VDD into a first current under the control of a first switch signal S1 and a second reference voltage VR2 to input the input of the ring oscillator 420. Supply to the terminal. The second switch circuit 442 converts the external voltage VDD into a second current by controlling the first switch signal S2 and the first reference voltage VR1 to convert the external oscillator 420 of the ring oscillator 420. Supply to the input terminal. The third switch circuit 443 converts the external voltage VDD into a third current under the control of a third switch signal S3 and supplies it to the input terminal of the ring oscillator 420.

The capacitor 444 is configured to receive the first, second and third currents output from the first, second and third switch circuits 441, 442, and 443 to the input terminal of the ring oscillator 420. To supply. The ring oscillator 420 converts the first, second and third currents supplied from the switch circuit 440 into a frequency by controlling a control signal con supplied from an external source. The output buffer 430 buffers and outputs the frequency output from the ring oscillator 420.

5 is a waveform diagram showing the frequency characteristics of the voltage controlled oscillator according to the present invention.

Referring to FIG. 5, the frequency characteristic of the voltage controlled oscillator of the present invention may be configured to output the first, second and third currents output through the first, second and third switch circuits 441, 442, and 443. It occurs by adjusting to 200uA, 200uA and 140uA, respectively. The first frequency F1 is a characteristic which appears when all of the first, second and third currents are supplied to the ring oscillator 420. The second frequency F2 is a characteristic that appears when the third current is interrupted and the first and second currents are supplied to the ring oscillator 420. The third frequency F3 is a characteristic that appears when the second current is blocked and the first and third currents are supplied to the ring oscillator 420. The fourth frequency F4 is a characteristic that appears when the first and second currents are blocked and the first current is supplied to the ring oscillator 420.

When the first and second currents are cut off and the first current is supplied to the ring oscillator 420 as in the fourth frequency F4, the characteristics of 20 to 40 MHz appear. It can be seen that the frequency characteristic of the voltage controlled oscillator of the present invention is more insensitive to the voltage change of the loop filter 300 than the frequency characteristic of the voltage controlled oscillator according to the prior art 20 to 170 MHz. In addition, since the gain of the voltage controlled generator is proportional to the range of the frequency and inversely proportional to the change of the voltage of the loop filter, the range of the frequency can be reduced to secure a wider voltage range. This reduces the gain of the voltage controlled oscillator even when operating at low voltages, thereby obtaining a desired output frequency. And, noise generated at the output frequency can be reduced.

As described above, by switching the characteristics of the frequency using a switch circuit, a desired frequency can be obtained when operating at a low voltage.

Claims (2)

In a voltage controlled oscillator of a phase locked loop circuit for generating a frequency according to the magnitude of the input currents: A first and a second having a different magnitude in response to the first and second reference voltages that accept an external voltage and have a voltage level complementary to the first, second and third switch signals supplied from the outside; And a switch circuit for selectively outputting third currents; Receives the first, second and third currents, and in response to a control signal supplied from the outside and the second reference voltage, to the magnitude of the first, second and third currents selectively supplied from the switch circuit. An oscillation circuit for outputting an oscillation signal whose frequency range is determined; And an output buffer for receiving the oscillation signal and outputting the oscillation signal. The method of claim 1, The switch circuit, A first switch circuit for selectively outputting the first current in response to the first switch signal and the second reference voltage; A second switch circuit for selectively outputting the second current different in magnitude from the first current in response to the first and second switch signals and the first reference voltage; And a third switch circuit for selectively outputting the third current having a magnitude different from the first and second currents in response to the first and third switch signals.