KR19990076163A - Flash memory device and program method - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a flash memory device and a program method.

2. Technical problem to be solved by the invention

When programming a flash memory cell in word units, a large drain current is required, and accordingly, a large drain pumping circuit is required.

3. Summary of the Solution of the Invention

When programming the flash memory cell, the primary program divided by byte unit increases the threshold voltage of the cell, and then second program by word unit, thereby reducing the consumption of program current and the size of the drain pumping circuit. And shorten the program time.

Description

Flash memory device and program method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device and a program method. Particularly, the program current is increased by increasing the threshold voltage of the cell with a primary program divided by a byte unit during programming of the flash memory cell and then performing a secondary program in a word unit. The present invention relates to a flash memory device and a program method which can reduce consumption, reduce the size of a drain pumping circuit, and shorten a program time.

A program of a general flash memory cell is composed of units of words. This method is described below with reference to FIG. 1.

1 is a circuit diagram illustrating a conventional method of programming a flash memory cell.

In general word-based programming, one of a plurality of word lines WL0 to WLn is selected by a row decoder according to an input address, and stored in a memory cell of one word (16 bits) connected to the selected word line. At the same time, a method of programming data was used. When programming one flash memory cell, about 500 mA of current is consumed. Thus, when programming in word units, a drain current of 8 mA is required. This drain current is supplied through the drain pumping circuit. When programming in a word unit according to the conventional method, a quite large drain pumping circuit is required to satisfy the drain current of 8 s and a programming time of 5 s is required. . As such, in the related art, a large amount of current is consumed when programming a flash memory cell to increase the size of the drain pumping circuit, thereby degrading the integration degree of the device and requiring a large program time, resulting in a decrease in program efficiency.

Accordingly, the present invention utilizes the characteristic that the threshold voltage is increased during programming of a flash memory cell. First, the first program is executed in byte units to increase the threshold voltage of the memory cell to some extent, and then the two bytes are simultaneously programmed. It is an object of the present invention to provide a flash memory device and a program method capable of executing a program in a short time with low current consumption and increasing an integration degree of a device.

The flash memory device according to the present invention for achieving the above object is a memory cell array connected between a plurality of word lines and a plurality of bit lines, and a drain pumping circuit for supplying a drain current to the memory cells constituting the memory cell array A flash memory device comprising: first driving means connected between a bit line and a drain pumping circuit of an upper one byte of the memory cell array to drive the upper one byte memory cell, and a lower one byte of the memory cell array A second driving means connected between the bit line and the drain pumping circuit to drive the lower one byte memory cell, and sequentially programming the upper and lower one byte memory cells and then storing the upper and lower one byte memory. That the cell is configured to be reprogrammed simultaneously It features.

In addition, the program method of the flash memory according to the present invention for achieving the above object is to turn on the first driving means during the first threshold voltage rise time of the memory cell to program the memory cell of the upper byte and the first driving means A first program step of programming a lower one byte memory cell by turning on a second driving means during a second threshold voltage rise time of the memory cell after the first threshold voltage rise time has elapsed after turning off; A second program step of simultaneously programming the upper one byte and the lower one byte of memory cells with the first driving means and the second driving means turned on at the same time after the second threshold voltage rise time has elapsed from the first programming step; It is characterized by comprising.

1 is a circuit diagram showing a conventional method for programming a flash memory cell.

2 (a) and 2 (b) are circuit diagrams and timing diagrams for explaining the programming method of a flash memory cell according to the present invention;

3 (a) and 3 (b) are graphs illustrating the relationship between program time and memory cell threshold voltage.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 (a) and 2 (b) are circuit diagrams for explaining a program method of a flash memory cell according to the present invention.

In general, the threshold voltage of an erased flash memory cell is 1.6 V. When programming the erased cell, the drain current initially decreases gradually after a strong peak current flows, and the cell cuts off. There is a characteristic to be in a state.

As shown in FIG. 2A, the first and second transistors T1, which are driving means for driving the memory cell by connecting the output of the drain pumping circuit 21 and the upper 8 bits and the lower 8 bits of the memory cell, T2) is driven by the D_PumpA and D_PumpB signals, each driven by a different pulse. At this time, the D_PumpA signal has a high state for a first threshold voltage rise time (first 500 mA) of the memory cell and a low state for a second threshold voltage rise time (next 500 mA) of the memory cell, and the second time. After elapses, the state becomes high again. Also, the D_PumpB signal has a low state during the first threshold voltage rise time of the memory cell and goes low after the second threshold voltage rise time of the memory cell.

The first transistor T1 is turned on for the first 500 ns (first threshold voltage rise time) as the D_PumpA signal becomes high, and receives a current from the drain pumping circuit, thereby connecting a memory cell connected to the bit line of the upper byte. Then turn off. Thereafter, when the first transistor T1 is turned off, the second transistor T2 receives a current from the drain pumping circuit for the next 500 kV (second threshold voltage rise time) as the D_PumpB signal becomes high. Causes the lower one byte of memory cell to be programmed. In this primary program, the threshold voltage of the memory cell is increased to some extent, and the drain current decreases. After this first program, the D_PumpA signal is set high to turn on the first transistor T1 again, and the second transistor is still high. 2nd program for ~ 4ms.

In such a flash memory device, when the data of a cell is read, the data stored in the cell is read through the sense amplifiers SA0 to SA15 with the READ_EN signal high and the DARA_IN signal low. Can be. On the other hand, the flash memory cells are set to '1' in advance when the program is executed. The READ_EN signal goes low during programming, and the data input signals DATA0_IN to DATA15_IN go low when storing '1' data, and high when storing '0' data. do.

The drain pumping circuit is designed in consideration of the drain current of the cell. When the drain pumping circuit fails to supply the drain peak current of the cell, the program efficiency decreases and the program is not sufficiently performed within a predetermined program time. As described in the present invention, if the program is executed in the unit of byte during the initial 500 mA of the drain current, the drain peak current can be reduced by half, which results in the pumping circuit also being reduced by about half. Since the drain current of the cell rapidly decreases after 1 ms of the first program, the second pump, which collects two bytes and programs one word at the same time, can be programmed with a drain pumping circuit reduced to one half. Done.

As described above, the two-step programming is performed by using the threshold voltage rising characteristic of the cell, thereby reducing the programming time and reducing the size of the drain pumping circuit, thereby improving program efficiency and improving device integration.

2 (b) shows a timing diagram of the D_PumpA signal and the D_PumpB signal when programming in this manner. After the D_PumpA signal is high for the first 500 ms, the first transistor T1 is turned on, and the first 8-bit memory cell is programmed, and then the first transistor T1 is turned off. After that, when the D_PumpB signal becomes high, the lower 8-bit memory cell is programmed for 500 ms. After this time, the total program time required for programming the flash memory cell is programmed by turning on the first transistor T1 again with the second transistor T2 turned on and programming two bytes at a time for about 3 ms. PGM_EN) takes about 4 ms.

3 (a) and 3 (b) are graphs illustrating the relationship between the program time and the memory cell threshold voltage.

As shown in FIG. 3A, the threshold voltage Vth of the memory cell rises rapidly during the initial stage of 1 kV, and gradually increases thereafter to a cut-off state. FIG. 3 (b) shows the result of log scale of the graph of 3 (a). It can be seen that the drain current of the cell is inversely proportional to the square of the cell threshold voltage.

As described above, according to the present invention, by using a threshold voltage rising characteristic of a flash memory cell, the program voltage is shortened by increasing the threshold voltage of the memory cell to a certain degree in a byte unit and then programming the two bytes at the same time. In addition, the size of the drain pumping circuit can be reduced, thereby improving the program efficiency while improving the device integration.

Claims (4)

A memory cell array connected between a plurality of word lines and a plurality of bit lines; A flash memory device comprising a drain pumping circuit for supplying a drain current to a memory cell constituting the memory cell array, First driving means connected between the upper one byte bit line and the drain pumping circuit of the memory cell array to drive the upper one byte memory cell; And second driving means connected between the lower one byte bit line and the drain pumping circuit of the memory cell array to drive the lower one byte memory cell, and sequentially programming the upper and lower one byte memory cells. And the upper and lower byte memory cells are reprogrammed at the same time. The method of claim 1, wherein the first driving means is turned on during the first threshold voltage rise time of the memory cell, and is turned off during the second threshold voltage rise time of the memory cell after the first threshold voltage rise time elapses. And a signal configured to be turned on again after the second threshold voltage rise time has elapsed. The method of claim 1, wherein the second driving means is turned on during the first threshold voltage rise time of the memory cell, and is turned off after the second threshold voltage rise time of the memory cell after the first threshold voltage rise time has elapsed. Flash memory device, characterized in that driven by a signal. The first driving means is turned on during the first threshold voltage rising time of the memory cell to program the memory cell of a higher byte, and the first driving means is turned off, after the first threshold voltage rising time has elapsed. A first program step of programming the lower one byte memory cell by turning on the second driving means during a second threshold voltage rise time of A second program for simultaneously programming the upper one byte and the lower one byte memory cells with the first driving means and the second driving means turned on at the same time after the second threshold voltage rise time elapses from the first program step Flash memory program method comprising the steps of.