KR19990075885A - Ferroelectric Random Access Memory Device - Google Patents

Abstract

The nonvolatile semiconductor memory device, ie, a ferroelectric random access memory device, disclosed herein includes at least one memory cell including a ferroelectric capacitor and a transfer transistor, and a bit line connected to the memory cell; And a sense amplifying circuit for sense amplifying a reference bit line charged with a reference voltage during a read operation and a potential difference between the bit lines. The nonvolatile semiconductor memory device further comprises: a reference ferroelectric capacitor having main electrodes; A first switching circuit for connecting a first one of said main electrodes and said reference bit line during a read operation, in response to a first switching control signal; A second switching circuit for connecting a second one of said main electrodes and said reference bit line in response to said second switching control signal; A reference plate line to which a pulse signal is applied in each section during a read operation comprising a sensing section and a rewriting section; A third switching circuit for electrically connecting the reference plate line and the first main electrode such that a positive voltage is generated between the reference plate line and the reference bit line by the pulse signal in response to the first switching control signal. Wow; A fourth switching circuit for electrically connecting the reference plate line and the second main electrode such that a positive voltage is generated between the reference plate line and the reference bit line by the pulse signal in response to the second switching control signal. Wow; And a control signal generation circuit for generating the first and second switching control signals in response to a signal informing the selection of the reference ferroelectric capacitor during the read operation. Here, the control signal generation circuit generates the first and second switching control signals as complementary signals while a read operation is performed on the memory cell so that the reference ferroelectric capacitor is in a non-switching region during a rewrite period during the read operation. To be switched on.

Description

FERROELECTRIC RANDOM ACCESS MEMORY DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a memory device having a ferroelectric capacitor as a storage means.

Recently, nonvolatile memory having the ability to retain data even at power off has been realized through the use of ferroelectric materials, such as PZT, which exhibit hysteresis characteristics. By using such ferroelectric materials in the memory cell, the nonvolatile memory can be implemented with a simple structure. Ferroelectric random access memory (FRAM) devices are non-volatile and have high-speed, low-voltage operation, which is drawing attention and competition from many memory chip makers. For example, the operating speed of the FRAM is determined by the polarization inversion time. The polarization inversion rate of the ferroelectric capacitor is determined according to the area of the capacitor, the thickness of the ferroelectric thin film, the applied voltage, and the like, but is usually in the unit of ns. This means that it can operate at much higher speeds compared to electrically erasable and programmable read only memory (EREPOM) or flash memory with read / write times in milliseconds.

FRAM with 2T / 2C structure as a non-volatile memory device has a disadvantage in that it is difficult to improve the density despite the advantages of high speed, so in order to overcome the limitation, 1T / 1C (1Tr / FRAM having a structure of 1 Cap) was developed. In this 1T / 1C structure, however, one reference cell is used for the sensing operation on the plurality of memory cells. As a result, the reliability of the chip itself depends on its characteristics.

Specifically, the fatigue characteristics of the ferroelectric material inserted between the main electrodes of the ferroelectric capacitor have a great influence on the reliability of the FRAM itself. In other words, the fatigue phenomenon of the reference cell reduces its residual polization (Pr), thereby reducing the sensing margin of the reference cell and causing a malfunction of the memory cell. The main reason for this fatigue phenomenon is that the polarization reversal of the ferroelectric material is performed twice during the sensing operation of the selected memory cell.

Accordingly, an object of the present invention is to provide a ferroelectric random access memory device having improved reliability.

1 is a block diagram showing the configuration of a ferroelectric RAM device according to a preferred embodiment of the present invention;

2 shows a hysteresis curve of a ferroelectric material;

3 shows an output waveform of the counter of FIG. 1; And

4 is a timing diagram illustrating a sensing operation of a ferroelectric RAM device according to a preferred embodiment of the present invention.

* Explanation of symbols on the main parts of the drawings

100: sense amplifier circuit 120: bit line precharge and equalization circuit

140: reference voltage supply circuit 160: counter

(Configuration)

According to an aspect of the present invention for achieving the above object, at least one memory cell consisting of a ferroelectric capacitor and a transfer transistor; A bit line connected to the memory cell; A nonvolatile semiconductor memory device comprising a reference bit line charged with a reference voltage during a read operation and a sense amplifier circuit for sense amplifying a potential difference between the bit lines, comprising: a reference ferroelectric capacitor having main electrodes; A first switching circuit for connecting a first one of said main electrodes and said reference bit line during a read operation, in response to a first switching control signal; A second switching circuit for connecting a second one of said main electrodes and said reference bit line in response to said second switching control signal; A reference plate line to which a pulse signal is applied in each section during a read operation comprising a sensing section and a rewriting section; A third switching circuit for electrically connecting the reference plate line and the first main electrode such that a positive voltage is generated between the reference plate line and the reference bit line by the pulse signal in response to the first switching control signal. Wow; A fourth switching circuit for electrically connecting the reference plate line and the second main electrode such that a positive voltage is generated between the reference plate line and the reference bit line by the pulse signal in response to the second switching control signal. Wow; Means for generating said first and second switching control signals in response to a signal informing the selection of said reference ferroelectric capacitor during said read operation; The control signal generating means generates the first and second switching control signals as complementary signals during a read operation to the memory cell so that the reference ferroelectric capacitor switches in the non-switching region during the rewrite period during the read operation. It is characterized by that.

In this embodiment, the control signal generating means comprises a counter.

In this embodiment, the first to fourth switching circuits are characterized by including NMOS transistors.

(Action)

With such a device, it is possible to improve the reliability of the ferroelectric ram device by allowing the ferroelectric material of the reference ferroelectric capacitor to be polarized once during the read operation.

(Example)

Hereinafter, reference will be made in detail with reference to FIGS. 1 to 4 according to an embodiment of the present invention.

1 is a block diagram illustrating a configuration of a ferroelectric random access memory device according to a preferred embodiment of the present invention.

In FIG. 1, the memory cell MC is composed of a transfer transistor Tr and a ferroelectric capacitor C _F. One of the main electrodes of the ferroelectric capacitor C _F is connected to a bit line BL through the transfer transistor Tr connected to a word line WL, and the other electrode includes a plate electrode line; PL).

A ferroelectric random access memory device according to the present invention includes a sense amplifier circuit 100, a bit line precharge and equalize circuit 120 and a reference voltage supply circuit 100. ). The sense amplifier circuit 100 senses and amplifies the difference between the reference voltage provided from the reference voltage supply circuit 140 and the voltage on the bit line BL corresponding to the stored data of the memory cell MC.

The bit line precharge and sensing circuit 120 precharges and equalizes the potentials of the bit lines BL and BLR in response to a precharge signal PRE and an equalization signal EQ. The circuit 120 is composed of three NMOS transistors MN1, MN2 and MN3.

The reference voltage supply circuit 140 generates a reference voltage Vref in response to a reference word line enable signal WLR during a read operation and generates a corresponding reference bit line BLR. Supply the reference voltage Vref.

The reference voltage supply circuit 140 includes a counter 160, three inverters IV1-IV3, four NMOS transistors MN4, MN5, MN6 and MN7, and It consists of one reference ferroelectric capacitor (RC _F ).

The counter 160 generates a high level switching control signal CNT when the reference word line activation signal WLR is activated, that is, when it is activated from a low level to a high level. The switching control signal CNT activated by the counter 160 generates the switching control signal CNT at a low level when the reference word line activation signal WLR is deactivated and then activated again. That is, based on one cycle of the signal WLR, the control signal CNT changes from a low level to a high level or from a high level to a low level. The waveform for this is well illustrated in FIG. 3.

The reference ferroelectric capacitor RCF has two main electrodes 142 and 144. One of the main electrodes 142 is connected to a reference bit line BLR through the transistor MN6 whose gate is controlled by the control signal CNT applied via an inverter IV3, and the other An electrode 144 is connected to the reference bit line BLR through the transistor MN7 whose gate is controlled by the control signal CNT. In addition, the main electrode 142 has a reference plate line PLR through a transistor MN5 whose gate is controlled by the control signal CNT applied through inverters IV1 and IV2. Is connected to. The main electrode 144 is connected to the reference plate line PLR through a transistor MN4 whose gate is controlled by the control signal CNT applied through the inverter IV1.

The operation of the reference voltage supply circuit 140 according to the preferred embodiment of the present invention is described below.

As shown in FIG. 3, when the reference word line activation signal WLR transitions from a low level to a high level, the output CNT of the counter 160 goes to a high level. By the high level of the control signal CNT, transistors MN5 and MN7 are turned on and transistors MN4 and MN6 are turned off. As a result, the main electrodes 142 and 144 of the ferroelectric capacitor RC _F are connected to the reference plate line PLR and the reference bit line BLR through the transistors MN5 and MN7, respectively.

Assume that the polarization Pr of the reference ferroelectric capacitor RC _F is at the point A of the hysteresis curve of FIG. 2. At this time, when a pulse is applied to the reference plate line (PLR), the dipoles of the capacitor (RC _F ) by the electric field applied from the plate line (PLR) to the reference bit line (BLR), the points (B) of the hysteresis curve of FIG. And to (D) along (C). As a result, the reference bit line BLR is charged to a potential corresponding to the polarization amount to be changed, that is, to the reference voltage Vref. Thereafter, a sensing operation on the memory cell is performed.

Then, the rewrite operation is performed after the sensing operation is performed. At this time, the output CNT of the counter 160 remains at a high level. As a result, the transistors MN4 and MN6 are turned off and the transistors MN5 and MN7 are turned on. At this time, when a pulse is applied to the reference plate line PLR, an electric field is formed from the reference plate line PLR to the reference bit line BLR, and the ferroelectric material is polarized to point C at point D of FIG. . That is, since it moves along the non-switching curve, no polarization reversal occurs. Since the reverse case is also performed according to this operation, the description thereof is omitted here.

4 is a timing diagram showing a sensing operation according to a preferred embodiment of the present invention.

First, the bit lines and the reference bit lines BL and BLR are precharged and equalized to the ground voltage by the signals PRE and EQ. Thereafter, the word line WL and the reference word line WLR are driven from the low level to the high level. As a result, the transfer transistor Tr of the memory cell and the transistors MN5 and MN7 of the reference voltage supply circuit 140 are turned on. Pulses are applied to the plate line and the reference plate lines PL and PLR so that the bit lines and reference bit lines BL and BLR corresponding to the ferroelectric capacitor C _F and the reference ferroelectric capacitor RC _F are respectively It is induced to the corresponding voltage level.

For example, when data "1" is stored in the ferroelectric capacitor C _F , the potential of the reference bit line BLR is lower than that of the bit line BL, as shown in FIG. 4. On the other hand, when data "0" is stored, the potential of the reference bit line BLR is higher than that of the bit line BL. At this time, the voltage difference between the lines BL and BLR is sufficiently amplified by the sense amplifier circuit 100.

Then, the rewrite operation is performed on the reference ferroelectric capacitor RC _F and the ferroelectric capacitor C _F of the memory cell. However, since the ferroelectric capacitor RC _{F in the} reference voltage supply circuit 140 is switched along the non-switching curve DC, the fatigue phenomenon of the reference ferroelectric capacitor RC _F may be prevented from deteriorating. At this time, the amount of charge derived from the reference ferroelectric capacitor RC _F should be maintained to be half that of the memory cell.

For that reason, when using the switching charge amount of the reference ferroelectric capacitor R _F , it should be smaller than that of the memory cell. In addition, when using capacitors of the same size, the amount of charge must be controlled by adjusting the voltage level of the pulse applied to the reference plate line PLR. In the subsequent operation, the above-described operation is repeatedly performed after the transistors MN4 and MN6 are turned on by a signal having a phase opposite to that of the counter generated in the previous operation.

As described above, the ferroelectric material of the reference ferroelectric capacitor is polarized only once by alternately applying pulses to the main electrodes of the reference ferroelectric capacitor during the read operation in order to prevent device malfunction due to the fatigue phenomenon. As a result, the reliability of the device can be improved.

Claims (3)

At least one memory cell consisting of a ferroelectric capacitor and a transfer transistor; A bit line connected to the memory cell; A nonvolatile semiconductor memory device comprising: a reference bit line charged with a reference voltage during a read operation and a sense amplifier circuit for sense amplifying a potential difference between the bit lines. A reference ferroelectric capacitor having main electrodes; A first switching circuit for connecting a first one of said main electrodes and said reference bit line during a read operation, in response to a first switching control signal; A second switching circuit for connecting a second one of said main electrodes and said reference bit line in response to said second switching control signal; A reference plate line to which a pulse signal is applied in each section during a read operation comprising a sensing section and a rewriting section; A third switching circuit for electrically connecting the reference plate line and the first main electrode such that a positive voltage is generated between the reference plate line and the reference bit line by the pulse signal in response to the first switching control signal. Wow; A fourth switching circuit for electrically connecting the reference plate line and the second main electrode such that a positive voltage is generated between the reference plate line and the reference bit line by the pulse signal in response to the second switching control signal. Wow; Means for generating said first and second switching control signals in response to a signal informing the selection of said reference ferroelectric capacitor during said read operation; The control signal generating means generates the first and second switching control signals as complementary signals during a read operation to the memory cell so that the reference ferroelectric capacitor switches in the non-switching region during the rewrite period during the read operation. Nonvolatile semiconductor memory device characterized in that. The method of claim 1, And said control signal generating means comprises a counter. The method of claim 1, And the first to fourth switching circuits comprise NMOS transistors.