KR19990072313A - Cache coherency protocol having a hovering (h) state for instructions and data - Google Patents

Abstract

A cache and method are disclosed for maintaining cache coherency in a data processing system. The data processing system includes a plurality of processors, each associated with one of the plurality of caches. According to the method, one data item is stored in a first one of the caches in association with one address tag specifying one address of the data item. The coherency indicator of the first cache is set to a first state indicating that the data item is valid. While the coherency indicator is set to the first state, if one of the caches intends to store at the address specified by the address tag, in response to the coherency of the first cache The indicator is updated to a second state indicating that the address tag is valid but the data item in the first cache is invalid. Then, according to one embodiment, the data transmission associated with the address specified by the address tag while detecting the coherency indicator is set to the second state, and in response, the first data item is detected as the second data item. Is stored in association with an address tag in the first cache. The coherency indicator is also updated to a third state indicating that the second data item is valid.

Description

CACHE COHERENCY PROTOCOL HAVING A HOVERING (H) STATE FOR INSTRUCTIONS AND DATA}

TECHNICAL FIELD The present invention relates to methods and systems for data processing, and more particularly, to methods and systems for maintaining cache coherency in multiprocessor data processing systems. More specifically, the present invention provides an Hovering (H) that allows the first cache to be updated with valid data in response to the second cache independently transmitting valid data on the interconnect combining the first and second caches. And an improved cache coherency protocol for a multiprocessor data processing system.

In a conventional symmetric multiprocessor (SMP) data processing system, all processors are generally identical to one another, that is, all processors use a common instruction set and communication protocol, have similar hardware structures, and have similar memory hierarchies. Generally supported. For example, a conventional SMP data processing system includes one system memory, a plurality of processing elements each having one processor and one or more levels of cache memory, and a system bus that couples the processing elements to each other and to system memory. system bus). In order to obtain valid execution results in one SMP data processing system, it is important to maintain a coherent memory hierarchy, that is, to support all processors with the same view of memory contents.

The coherent memory hierarchy is maintained by using one selected memory coherency protocol, such as the MESI protocol. In the MESI protocol, an indication of coherency status is stored in association with each coherent granule (eg, cache line or sector) of at least all of the upper level (cache) memories. Each coherency granule is one of two states, modified (M), exclusive (E), shared (S), or invalid (I) states, represented by two bits in the cache directory. It can have one state. The modified state indicates that one coherency granule is only valid in a cache that stores the modified coherency granule and that the value of the modified coherency granule has not been written to system memory. When a coherency granule exhibits an exclusive state, the coherency granule resides only in a cache that has an exclusive coherency granule among all caches in that level of the memory hierarchy. do. However, in the exclusion state, the data is consistent with the system memory. If one coherency granule is marked as shared in one cache directory, the coherency granule resides in at least one other cache of the same level of the associated cache and system hierarchy. All copies of the coherency granules above correspond to system memory. Finally, an invalid state indicates that both data and address tags associated with one coherent granule are invalid.

The state in which each coherency granule (e.g., cache line) is set depends on both the state of the cache line and the type of memory access achieved by the requesting processor. have. Thus, maintaining memory coherency in a multiprocessor data processing system requires processors to communicate messages over the system bus indicating the intention to read or write in storage locations. For example, when a processor wants to write data to one storage location, the processor first informs all other processing elements that it is writing data to that storage location, and gets permission from all other processing elements. You can record later. The permission messages received by the requesting processor indicate that all other stored copies of the storage contents have been invalidated, thereby ensuring that other processors will not have access to stale local data. The exchange of such messages is known as cross-invalidation (XI).

The present invention allows the cross-validation of cache entries to maintain memory coherency in an SMP data processing system, whereas the invalidation of cache entries by remote processors is a hit ratio in local caches. By reducing the number of elements), which may affect the performance of the data processing system. Thus, even with large local caches, one processing element may have a long access latency when retrieving data from a remote cache or system memory in another processing element that once resided in one local cache. may result in access latency. As noted above, it is desirable to support a SMP data processing system with a method and system for maintaining memory coherency that can reduce the performance shortcomings caused by cross-validation of cache entries.

One object of the present invention is to support an improved method and system for data processing.

It is yet another object of the present invention to support multiprocessor data processing systems with an improved method and system for maintaining cache coherency.

It is yet another object of the present invention to provide for a roaming request that, when the second cache independently transmits valid data on the interconnect combining the first and second caches, the first cache is updated with valid data in response thereto. It supports the cache coherency protocol for multiprocessor data processing systems that include.

The above objects are achieved as described below. Data processing systems are supported that include a plurality of processors, each associated with one of a plurality of caches. According to the method of the present invention, one data item is stored in a first of the caches in association with an address tag that addresses the data item. The coherency indicator in the first cache is set to a first state indicating that the data item is valid. While the coherency indicator is set to the first state, if another one of the caches intends to store at the address specified by the address tag, the coherency indicator of the first cache is The address tag is updated to a second state indicating that the address tag is valid but the data item in the first cache is invalid. Then, according to one embodiment, the data transmission associated with the address specified by the address tag while detecting the coherency indicator is set to the second state, and in response, the first data item is detected as the second data item. Is stored in the first cache in association with an address tag. The coherency indicator is also updated to a third state indicating that the second data item is valid.

Further objects, features, and effects as well as the above of the present invention will become apparent from the following detailed description.

1 illustrates one exemplary embodiment of a multiprocessor data processing system in accordance with the present invention.

2 is a block diagram illustrating an exemplary embodiment of one cache in accordance with the present invention.

3 is a state diagram illustrating one exemplary embodiment of the H-MESI memory coherency protocol of the present invention.

<Explanation of symbols for the main parts of the drawings>

10: processor

12: L1 cache

14: L2 Cache

16: Interconnect

18: system memory

The upper level block diagram of a multiprocessor data processing system according to the present invention will be described with reference to the drawings, in particular with reference to FIG. As shown, the data processing system 8 preferably includes a number of processors 10a-10n that each include a PowerPC ^tm line, one of the processors available from IBM. In addition to conventional registers, instruction flow logic, and execution units used for the execution of program instructions, each processor 10a-10n is on-board level L1 caches 12a-. 12n) of the relevant one. Each of the L1 caches 12a-12n temporarily stores instructions and data that are easily accessible by the associated processor. Although the L1 caches 12a-12n are described in FIG. 1 as unified caches that store both instructions and data (hereafter referred to only as data), those skilled in the art will appreciate that each L1 cache 12a-12n It can be appreciated that) may alternatively be implemented branched to an instruction cache and a data cache.

In order to minimize data access latency, the data processing system 8 may include one or more additional, such as second level (L2) caches 14a-14n used to load data into the L1 caches 12a-12n. It also includes the cache memory level. That is, the L2 caches 14a-14n serve as intermediate storage between the system memory 18 and the L1 caches 12a-12n, so much larger than the L1 caches 12a-12n. Can store data but has a longer access latency. For example, L2 caches 14a-14n may have 256 to 512 kilobytes of storage, whereas L1 caches 12a-12n have a storage capacity of 64 to 128 kilobytes. As noted above, although FIG. 1 only illustrates a two level cache, the memory hierarchy of the data processing system 8 may be concatenated sequentially or include additional levels of lookaside caches. Can be extended to

As described, the data processing system 8 further includes an input / output device 20, a system memory 18, and a non-volatile storage 22, each of which is coupled to an interconnect. Input / output device 20 includes conventional peripherals such as display devices, keyboards, and graphical pointers, each of which is connected to interconnect 16 via existing adapters. The nonvolatile storage device 22 stores the drive system and other software to be transferred to the volatile system memory 18 in response to the data processing system 8 being powered on. Of course, those skilled in the art will include many additional components, such as not shown in FIG. 1, such as a memory controller for coordinating access to the system memory 18 and serial / parallel ports for connecting the data processing system 8 to a network or ancillary systems. It should be understood that it can.

Interconnect 16, which may include one or more buses or cross-point switches, includes L2 caches 14a-14n, system memory 18, input / output device 20, and nonvolatile storage. It serves as a connection channel for communication transactions between the (22). A typical communication transaction on interconnect 16 includes a source tag that specifies the source of the transaction, a destination tag, address, and / or data that specifies the desired recipient of the transaction. Each device connected to the interconnect 16 preferably snoops all communication transactions on the interconnect 16.

Referring now to FIG. 2, a more detailed block diagram of an exemplary embodiment of an L2 cache 14 in accordance with the present invention is shown. In the exemplary embodiment above, the L2 cache 14 is a four-way set associate cache using a 32 bit address. Thus, the data array 34 of the L2 cache 14 includes a number of congruence classes, each of which contains four paths for storing cache lines. As in conventional set associative caches, the storage locations of system memory 18 are stored in data array 34 using index bits (eg, 20-26 bits in 32-bit addresses) within the storage location address. Mapped to specific homology classes.

Cache lines stored in data array 34 are written to cache directory 32 which contains one directory entry for each path in data array 34. Each directory entry has a tag field 40, a coherency status field 42, a least recently used field (LRU field) 44, and an inclusion field. 46). The tag field 40 stores the tag bits (eg, 0-19 bits) of the system memory address of the cache line, thereby specifying which cache line is stored in that path of the data array 34. Referring to FIG. 3 in more detail below, the coherency state field 42 indicates the data coherency state stored in the corresponding path of the data array 34 using predetermined bit combinations. LRU field 44 indicates how recently the corresponding path of data array 34 has been accessed relative to other paths of its homology class, whereby a cache line has a homology class in response to a cache miss. Indicates if it is cast out. Finally, the inclusion field 46 indicates whether the cache line stored in the corresponding path of the data array 34 is also stored in the associated L1 cache 12.

With continued reference to FIG. 2, the L2 cache 14 responds to signals received from the associated L1 cache 12 and to snooped transactions on the interconnect 16 to perform data storage and retrieval in the data array 34. It further includes a cache controller 36 for managing and updating the cache directory 32. As described above, cache controller 36 includes a read queue 50 and a write queue 52 that update cache directory 32 and allow access to data array 34. For example, if a read request is received from the associated L1 cache 12, in response the cache controller 36 places the read request on one entry in the read queue 50. Cache controller 36 supports the read request by supplying the requested data to the associated L1 cache 12 and then removes the read request from read queue 50. In another example, cache controller 36 is initiated by another L2 caches 14a-14n to indicate that the far processor 10 wishes to modify a local copy of one particular cache line. You can snoop. Snooping the transaction, and in response, cache controller 36 reads a request to read cache directory 32 to determine whether the particular cache line resides in data array 34. (50). If it resides, cache controller 36 places an appropriate response on interconnect 16 and, if necessary, requests a directory write to update the coherency status field associated with that particular cache line when supported. Is embedded in the recording queue 52. Although FIG. 2 describes an embodiment using only one read queue and one write queue, the number of queues supported by the cache controller 36 is a matter of design, and the cache controller 36 It should be understood that separate queues may also be supported for cache directory access and data array access.

Cache controller 36 further includes a mode register 60 that includes one or more bits that can be set to control its operation, as described in more detail below. Moreover, cache controller 36 includes a performance monitor 70. The performance monitor 70 has a number of performance monitor counters that increase in response to the occurrence of one event, or combination of events, specified by one or more controller resists CR0-CRm when enabled. PMC0-PMCn; 72). Events that can be countered by PMCs 72 in response to the settings of CRs 74 include cache hits, cache misses, number of entries in a particular queue, access latency for L2 cache hits, Access latency for L2 cache misses, and the like. Each of the PMCs 72 and CRs 74 are preferably memory mapped registers that can be read and written by the associated processor 10 via a load instruction and a store instruction.

Referring to Figure 3, one exemplary embodiment of the H-MESI memory coherency protocol of the present invention is shown. Higher level caches preferably implement the conventional MESI protocol, whereas the H-MESI protocol preferably implements the lowest level [eg, implementation of the data processing system 8 described in FIG. 1] in the memory hierarchy. In the example only L2 caches 14a-14n]. However, in alternative embodiments of the data processing system 8, the H-MESI protocol may be implemented at each level of the cache in the memory hierarchy at the expense of additional inter-cache communication traffic.

As shown in FIG. 3, the H-MESI cache coherency protocol is a conventional modification (M), exclusion (E), and sharing (S) of the MESI protocol identified by reference numerals 80, 82, 84, and 86, respectively. , Invalid (I) states. Moreover, the H-MESI memory coherency protocol of the present invention is a data item (e.g., cache line) stored in the corresponding path of the data array 34, although the address tag stored in the associated tag field 40 is valid. , Or cache sector) includes a hovering (H) state 90 indicating invalid.

In one preferred embodiment, the coherency status field 42 in each entry of each L2 cache directory 32 is stored in the tag field 40 and the corresponding path of the data array 34 at power up. Initialized to I state 86 indicating that all of the data is invalid. L1 cache directory entries are similarly initialized to an invalid state in accordance with conventional MESI protocols. Then, the coherency state of one cache line (or cache sector) stored in one of the L2 caches 14a-14n in the invalid state 86 is transmitted to the processors 10a-10n. Depending on the type of memory request made and the response of the memory hierarchy to these requests, it may be updated to one of the M state 80, the E state 82, or the S state 84.

For example, if processor 10a makes a read request in response to a load instruction, L1 cache 12a first determines whether the requested data resides in L1 cache 12a. In response to a hit in the L1 cache 12a, the L1 cache 12a simply supplies the requested data to the processor 10a. However, in response to a miss in L1 cache 12a, L1 cache 12a issues a read request to L2 cache 14a via a cross-cache connection. In response to a hit in the L2 cache 14a, the requested data is supplied to the L1 cache 12a by the L2 cache 14a, and the L1 cache 12a requests the data in connection with the appropriate MESI coherency state. Stores the data and sends the requested data to the processor 10a. However, if a read request is missed both in the L1 cache 12a and the L2 cache 14a, the cache controller 36 of the L2 cache 14a issues the read request on the interconnect 16 in one transaction, which is Snoop by the respective L2 caches 14b-14n.

Snooping a read request on interconnect 16, and in response, the cache controller 36 of each of the L2 caches 14b-14n causes the requested data to be its data array 34, or L1 caches 12b-. Determine whether it resides in the relevant one of 12n). If none of the L2 caches 14b-14n or L1 caches 12b-12n store the required data, then each of the L2 caches 14a-14n is null response to the L2 cache 14a. ), And then request data from system memory 18. When the requested data is returned from the system memory 18 to the L2 cache 14a, the cache controller 36 exports the requested data to the L1 cache 12a, and sends the requested data to its data array 34. And updates the coherency status field 42 associated with the path for storing the requested data from the I state 86 to the E state 82 as indicated by reference numeral 100. As in the conventional MESI protocol, E state 82 indicates that the associated cache line is valid but does not reside in any other cache at the second level of the memory hierarchy.

Similarly, if either the L1 caches 12b-12n or the L2 caches 14b-14n store the requested data in the E state 82, or the S state 84 and so in the L2 cache 14a. If a shared response is made to the read request placed on the interconnect 16, the L2 cache 14a retrieves the requested data from the system memory 18. In this case, however, the coherency state of the path of the L2 cache 14a that stores the requested data transitions from the I state 86 to the S state 84, as indicated at 102. Other caches of L2 caches 14 that store the requested data in E state 82 are also updated to S state 84 as indicated at 104.

If the data requested by the processor 10a does not reside in the L1 cache 12a and the L2 cache 14a and is stored in the M state 80 in the L1 cache 12n, for example, the L2 cache ( The cache controller 36 of 14n responds to the read request with one retry and signals the L1 cache 12n to send the requested data to the memory. At that time, the coherency state of the requested data in the L1 cache 12n and the L2 cache 14n is updated to the S state 84 as indicated by reference numeral 106. Then, when the L2 cache 14a sends a read request back on the interconnect 16, the L2 cache 14n makes a shared response, and the L2 cache 14a from the system memory 18 as described above. Get the requested data. In one optional embodiment that supports so-called modification intervention, the required data is supplied by the cache controller 36 of the L2 cache 14n rather than by the system memory 18, thereby reducing the access latency. have.

If, instead of one read request, the " read with intent to modify " request indicates that the L1 cache 12a intends to exclusively use one memory storage location for the purpose of the processor 10a making the modification. If so, follow the process described above to obtain a cache line that includes the specified memory storage location. However, when the requested cache line is obtained, the L1 cache 12a stores the requested cache line in a modified state. Moreover, since the "Modify Purpose Read" transaction indicates that other copies of the requested cache line are stale, other L1 caches and L2 caches must indicate that the copies of the requested cache line are invalid. In L1 caches 12b-12n, all copies of the required cache line are simply marked as invalid. However, the coherency state of copies of the requested cache line stored in L2 caches 14b-14n is updated to I state 86 as in a conventional multiprocessor data processing system using cross-validation (XI). It doesn't work. Instead, according to an important feature of the present invention, each of the L2 caches 14b-14n storing one copy of the required cache line one by one may be selected from the S state 84, the M state 80, or the E state 82. Update the coherency status field 42 with respect to its copy, as indicated by reference numerals 110, 112, and 114, respectively, in the state to the H state 90. As mentioned above, the H state 90 indicates that the tag stored in the tag field 40 remains valid but the associated cache line in the data array 34 is invalid. Entries in one cache directory 32 invalidate specific data blocks and kill other snooped transactions that require data invalidation, that is, transactions that certainly invalidate a particular data block and invalidate any modified data. Flushes, which are transactions that copy to system memory, declaims, which are transactions that invalidate copies of the cache line marked in response to the storage to be modified and shared in the remote caches in response. In response, and the like, it is similarly updated to the H state 90.

As referenced by reference numerals 116, 118, and 120, one cache directory entry may be stored in the H state 90 in the E state 82, the M state 80, in accordance with the type of transactions received in the cache. Or transition to S state 84, respectively. For example, since the data retrieved from the system memory 18 is stored only in the L2 cache 14a among all the L2 caches 14a-14n, the processor 10a may execute the [L1 cache 12a and L2 cache ( 14a) After both miss], if a read request is received to receive a null response from L2 caches 14b-14n, the directory entry of L2 cache 14a in H state 90 responds (reference number 86). Transition to E state 82). On the other hand, if the processor 10a shows the intention of storing data in one path of the L1 cache 12a in the H state 90, the L1 cache 12a informs the L2 cache 14 of the intention. Present a "Modify Purpose Read" transaction on the interconnect 16. As described above, copies of the requested cache line stored in the L2 caches 14b-14n are snooped to the modification purpose read transaction, and in response are updated to the H state 90, and the L1 caches 12b- Copies of the requested cache line stored in 12n) are marked invalid. Once the requested cache line returns to the L1 cache 12a and the processor 10a updates the cache line, the cache line is marked as modified in the L1 cache 12a to indicate that the cache line is valid. Depending on the implementation, the modified cache line may not be written back to the system memory 18, but may be stored in succession in the L2 cache 14a (eg, in response to an L1 castout). If so, the coherency status field 42 of the L2 cache 14a associated with the modified cache line is updated to the M state 80 as indicated at 118. Finally, the L2 cache directory entry of one H state 90 is updated to S state 84 in response to a number of different request / response scenarios.

First, when the associated processor 10 makes one read request to the address specified by the (valid) address tag of the tag field 40, and the at least one L2 cache 14 responds with a shared response, the H state ( L2 directory entry of 90 transitions to S state 84. More importantly, the L2 directory entry in H state 90 remains in the S state (without the need for associated processor 10 to issue one data request or L2 cache 14 to initiate one transaction on interconnect 16). 84). As described above, each of the L2 caches 14a-14n snoops all transactions on the interconnect 16. If one of the L2 caches 14a-14n includes an updated (ie valid) copy of the data, for example, the L2 cache 14a is stored in the L2 cache 14a in the H state 90. If one snoops a transaction by another one of the L2 caches 14b-14n, the cache controller 36 of the L2 cache 14a samples the data from the interconnect 16 and retrieves the snooped data. Stored in data array 34, and update the associated coherency state field 42 from H state 90 to S state 84. Of course, the L2 cache 14a also supports a response to a snooped transaction if a response is needed to maintain coherency. For example, if the snooped transaction is a read request, the L2 cache 14a samples the requested data so that the requesting L2 cache can store the requested data in the S state 84 rather than the E state 82. It must support a shared response that indicates its intention. Transactions on the interconnect 16 that can be snooped in this way in relation to valid address tags to update invalid data are data to system memory 18 due to read transactions, write transactions, and cache line cast outs. Reverse records, and so forth.

State transitions made in the exemplary embodiment of the H-MESI memory coherency protocol described in FIG. 3 are summarized in Table 1 below.

State transition Causes Notes I → E CPU read request with null response I → S CPU read request with shared or modified response I → M CPU "read with intent to modify; (rwitm)" E → S Read request snoop E → M CPU rwitm E → H Data invalidation request snoop Snooped data invalidation requests are rwitm, dclaim, kill, flush, etc. S → M CPU rwitm Issue a dclaim on the interconnect. S → H Data invalidation request snoop M → S Read request snoop If a modification response is supported, supply data. M → H Data invalidation request snoop If the snooped transaction is rwitm, supply the data when modification intervention is supported. H → E CPU read request with null response H → S CPU read request with shared response or modified response; Snoop for read, or write request H → M CPU rwitm

According to an important feature of the present invention, the H-MESI protocol can be implemented precisely or imprecise. The precise implementation of the H-MESI protocol requires that the L2 caches 14a-14n always sample the data that can be obtained on the interconnect 16 in order to refresh the invalid cache lines to the H state 90. In contrast, the coarse implementation allows L2 caches 14a-14b to selectively sample the data on interconnect 16 to refresh the cache lines to H state 90. In the example embodiment described in FIG. 2, each of the L2 caches 14 is independent of the other remaining L2 caches, either in fine mode or in coarse mode based on the state of the mode bit 62 of its mode register 60. It can work as either.

Operating the L2 caches 14a-14n in fine mode is particularly useful when debugging, or performance-tuning, because the operation of the fine mode makes the software behavior more predictable and makes the software timing more consistent. There is a benefit in performance-tuning. Moreover, in fine mode, data requests that miss at both levels of the local cache (and require the local L2 cache 14 to send one transaction on the interconnect 16) are generally rare and are possible in software. Act as "signs of bugs". Moreover, in an embodiment of the present invention that supports modification intervention, the precise H-MESI protocol is required by the processor 10 and data stored in H state 90 in the local L2 cache 14 is modified intervention (i.e., Ensure that it can always be supplied. The major disadvantage of operating one L2 cache 14 in fine mode is that the above update cannot be performed, for example, because the write queue 52 of the L2 cache 14 is full, the L2 cache line. Snooped transactions that can update to H state 90 must be retried.

Since it is desirable not to retry the operations necessary for performing optimal updates to the cache lines in the H state 90, for example read requests, generally while the L2 caches 14a-14n are in normal operation. Is preferably in the coarse mode. As mentioned above, the coarse mode operation causes the update of the cache lines to the H state 90 selectively. In the preferred embodiment, when one L2 cache 14 is in coarse mode, updates of cache lines to H state 90 are only written to queue 52 (or one publicly supported directory write, if implemented). Only if the queue has less than the threshold number of entries. Therefore, when the mode bit 62 exceeds the number of entries already in the write queue 52 above a predetermined threshold, the hardware in the L2 cache 14 or software executed by the associated processor 10 in response. One of them may be used to be set to a state corresponding to the coarse mode. However, other embodiments of the present invention may selectively execute the update of the L2 cache lines to the H state 90 based on other criteria as will be described in detail below.

In the exemplary embodiment of the data processing system 8 shown in FIG. 2, each of the L2 caches 14a-14n may be independently set to fine or non-precision mode by software or hardware, or both. Can be. For example, if a software control of the operating mode of the L2 cache 14a is desired, the processor 10a may simply set the mode bit 62 by executing a store instruction targeting the mode register 60. Optionally, the software allows the PMCs 72 to counter the occurrence of events of interest, such as the addition and deletion of entries in the write queue 52, L2 cache misses, access latency in the case of L2 cache misses, and the like. Values 74 may be stored. The software can then access the values of the PMCs 72 of interest by executing the load instructions. When one of the values of the PMCs 72, or a combination thereof, exceeds the determined thresholds of the software, in response, the software may set the mode bit 62 to select the appropriate one of the fine mode and the coarse mode. . For example, if the L2 cache 14a is operating in coarse mode and the number of L2 cache misses is greater than the predetermined percentage of the total number of L2 accesses, the software may set the mode bit 62 to correspond to fine mode. Can be set.

Hardware control of the operating mode of the L2 caches 14a-14n may be similarly implemented by the performance monitor 70. In one exemplary embodiment, when the number of occurrences of one selected event, or combination of events, gathered in one or more PMCs 72 exceeds a predetermined threshold, in response, each performance monitor 70 generates a mode bit ( Logic for generating a signal that sets 62) to a particular state. The event of interest, or the selection of events and the enablement of the PMCs 72 may be determined by any settings of the performance monitor 70, or by software executed by the associated processor 10. Can be. In another embodiment, when the number of occurrences of one selected event, or combination events, exceeds a predetermined threshold, in response, the performance monitor 70 may be set to generate a performance monitor interrupt (PMI). have. The PMI is serviced by the associated processor 10 executing an interrupt handler that changes the state of the mode bit 62.

As described above, the present invention supports an improved method and system for maintaining memory coherency in a multiprocessor data processing system. The improved memory coherency protocol supported by the present invention allows a processor associated with one invalid data item stored in one cache associated with a valid address tag to automatically have valid data without having to issue an explicit read or write request. To be updated. In this way, data invalidated by the activity of the remote processors can be refreshed before the local processor can access the data, thereby substantially eliminating the need to retrieve data from the remote cache or system memory. Can be reduced. As cache lines are updated without accessing or requiring memory, the debate over memory access and system-wide lock is also substantially reduced.

Although the invention has been specifically described and described in connection with one exemplary embodiment, those skilled in the art can understand that various changes in form and details are possible herein without departing from the spirit and scope of the invention. . For example, an exemplary embodiment of one memory coherency protocol described in FIG. 3 is used to initialize directory entries when I state 86 is only powered on and re-enter from another state. May be modified in a direction to remove the state. If the I state 86 is removed, the coherency state field of each directory entry may be initialized to the H state 90 upon power up, and the tag field of each L2 directory entry is at least the same homology. Within a class, it can be initialized with only one tag value. Moreover, it should be understood that the performance monitor 70 of FIG. 2 may optionally be implemented as one system-wide performance monitor coupled to the interconnect 16 rather than multiple separate performance monitors inside each L2 cache 14. do.

Claims (18)

1. A method of maintaining cache coherency in a data processing system comprising a plurality of processors each associated with one of a plurality of caches, the method comprising: Storing said data item in a first one of said plurality of caches in association with an address tag specifying an address of a data item; Setting a cache indicator of the first cache to a first state indicating that the data item is valid; If another one of the plurality of caches intends to store at the address specified by the address tag while the coherency indicator is set to the first state, in response to the Updating a coherency indicator to a second state indicating that the address tag is valid but the data item in the first cache is invalid How to include. The method of claim 1, wherein the data processing system comprises an interconnect coupling the plurality of processors and the data item is a first data item. Snooping the interconnect to identify a data transmission on the interconnect in relation to the address specified by the address tag; While the coherency indicator is set to the second state, detect data transmission on the interconnect in association with the address specified by the address tag, and in response, detect the second data in association with the address tag. Replacing the first data by storing in the first cache and updating the coherency indicator to a third state indicating that the second data item is valid How to include more. 3. The method of claim 2, wherein updating the coherency indicator to a third state indicating that the second data item is valid further comprises: the second data item being one of the first cache and the plurality of caches. Updating the coherency indicator with a shared state indicating that it is also stored in the other. 2. The method of claim 1, wherein setting the coherency indicator of the first cache to a first state indicating that the data item is valid comprises: modifying the coherency indicator in the first cache a modified state ( setting to one of a modifed state, a shared state, and an exclusive state. The data processing system of claim 1, wherein the data processing system further comprises a low level memory from which the first cache retrieves data, the plurality of processors including one first processor associated with the first cache, the data item Includes a first data item, the method comprising The plurality of caches, not the low level memory, in response to a request of the first processor for data associated with the address specified by the address tag while the coherency indicator is set to the second state. Obtaining a valid second data item associated with the address from another one of the following. 2. The method of claim 1, further comprising setting the coherency indicator to an invalid state indicating that both the address tag and the data item are invalid. A cache for supporting cache coherency in a data processing system each including a plurality of processors each associated with one of a plurality of caches, the cache comprising: A data storage location for storing data items; A tag storage location for storing an address tag specifying an address of the data item included in the data storage location; If the data item is stored at the data storage location, it is set in response to this to a first state indicating that the data item is valid, and among the plurality of caches while a coherency indicator is set to the first state. If another dictates the intention to store at the address specified by the address tag, in response the coherency is set to a second state indicating that the address tag is valid but the data item at the data storage location is invalid. Indicator Cache containing. 8. The system of claim 7, wherein the data item is a first data item and the data processing system further comprises an interconnect coupling the plurality of processors, wherein the cache is Means for snooping the interconnect to identify on the interconnect one data transmission initiated by another one of the plurality of caches in association with the address specified by the address tag and comprising a second data item; , If the coherency indicator detects data transmission on the interconnect with respect to the address specified by the address tag while the coherency indicator is set to the second state, in response to the second data item in association with the address tag Means for replacing the first data item by storing the data in the data storage device; Means for updating the coherency indicator with a third state indicating that the second data item is valid Cache containing more. 9. The apparatus of claim 8, wherein the means for updating the coherency indicator to a third state indicating that the second data item is valid further comprises: the second data item being another of the cache and the plurality of caches. Means for updating the coherency indicator with a shared state indicating that all are stored in one. 8. The cache of claim 7, wherein said first state of said coherency indicator comprises one of a modified state, a shared state, and an excluded state. 10. The system of claim 7, wherein the cache is a first cache, the plurality of processors comprises one first processor associated with the first cache, and wherein the data processing system is capable of retrieving data by the first cache. Further includes one low level memory, wherein the cache is One of the plurality of caches other than the lower level in response to a request of the first processor for data associated with the address specified by the address tag while the coherency indicator is set to the second state; Means for obtaining valid data associated with the address from another one. 8. The cache of claim 7, wherein the coherency indicator further comprises an invalid state indicating that both the address tag and the address entry are invalid. In a data processing system, Interconnect, A plurality of processors coupled to the interconnect; Multiple caches, each associated with one of the multiple processors Including, wherein the first cache of the plurality of caches are A data storage device for storing data items; A tag storage device configured to store an address tag specifying an address of the data item included in the data storage device; If the data item is stored at the data storage location, it is set in response to this to a first state indicating that the data item is valid, and among the plurality of caches while a coherency indicator is set to the first state. If another dictates the intention to store at the address specified by the address tag, in response the coherency is set to a second state indicating that the address tag is valid but the data item at the data storage location is invalid. A system comprising an indicator. The method of claim 13, wherein the data item is a first data item, and the first cache is Means for snooping the interconnect to identify on the interconnect a data transmission initiated by another one of the plurality of caches in association with the address specified by the address tag and comprising a second data item; If the coherency indicator detects a data transmission on the interconnect in association with the address specified by the address tag while the coherency indicator is set to the second state, in response to the second tag in association with the address tag; Means for replacing the first data item by storing a data item in the data storage device; Means for updating the coherency indicator with a third state indicating that the second data item is valid The system further comprising. 15. The apparatus of claim 14, wherein the means for updating the coherency indicator to a third state indicating that the second data item is valid further comprises: the second data item being another of the cache and the plurality of caches. Means for updating the coherency indicator with a shared state indicating that all are stored in one. The system of claim 13, wherein the first state of the coherency indicator comprises one of a modified state, a shared state, and an excluded state. The system of claim 13, wherein the plurality of processors comprises one first processor associated with the first cache, wherein the data processing system comprises A low level memory through which the first cache can retrieve data; The plurality of non-lower levels in response to a request by the first processor for data associated with the address specified by the address tag while the coherency indicator is set to the second state. Means for obtaining valid data associated with the address from another one of the caches The system further comprising. 14. The system of claim 13, wherein the coherency indicator further comprises an invalid state indicating that both the address tag and the address item are invalid.