KR19990061654A - Segment Sync Signal Detection Device of Digital TV Receiver - Google Patents

Abstract

The present invention relates to a core segment sync signal detecting circuit used for frame synchronization of a high-definition television, comprising a segment sync signal correlator unit, a memory maximum position detector unit, and a size comparator. By operating at double speed of symbol clock, it is robust to timing error and facilitates timing recovery performed in the next stage.The double signal of symbol clock is divided into even and odd columns to accumulate the correlation value for each signal sequence and maximize the maximum value. Find and compare the size through the size comparator, and output a large column.

Description

Segment Sync Signal Detection Device of Digital TV Receiver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to high definition televisions, and more particularly to segment synchronization of digital television receivers used for frame synchronization of 8 VSB high definition television receivers, which more robustly acts on timing errors and enables faster timing recovery after segment synchronization signal detection. It relates to a signal detection device.

In general, in order to properly interpret data received by a receiver in a Grand Alliance-HDTV transmission system, the receiver must operate in synchronization with the frame structure of the data. This synchronization of the receiver with the frame structure of the received data is called frame synchronization or segment synchronization. Frame synchronization is a constant signal transmitted from a transmitter, that is, a frame marker or a synchronization code. This is done by detecting a synchronization codeword at the receiving end.

Since the GA-HDTV transmission system uses a higher residual sideband modulation method having a carrier, the received signal input through the tuner, channel filtering, and carrier recovery is divided into I-channel and Q-channel signal components. Have The GA-HDTV transmission system performs segment synchronization and symbol clock recovery using only I-channel signal components among them.

In the GA-HDTV transmission system, a video signal transmitted in transmission and reception of a digital TV signal may have various forms. Of these signals, the segment sync signals and the field sync signals transmitted for synchronization purposes have an important role in reconstruction of the video signal, so they should be less affected by noise. In addition, since the sync signal does not contain video information, it has a limitation that it cannot occupy a large part of the transmitted video signal. 1 shows a structure of a segment synchronization signal used in a GA-HDTV system. In order to generate a segment synchronization signal that is less affected by noise and does not occupy a large part of the video signal as described above, the GA-HDTV system is set to ± 5 as shown in FIG. A binary signal with two levels and four symbol periods is used as a synchronization signal.In the case of the high-speed data cable transmission mode, as shown in Fig. 1 (B), it has a value of ± 9 two levels and a period of four symbols. A binary signal with is used as a segment synchronization signal.

2 shows a structure of a transmission data frame used in a GA-HDTV system. In order to display 20 images per second, one frame has a length of 48.4 ms, and one frame is divided into an even field and an odd field. Each field is composed of 313 segments, a segment synchronization signal having a length of four symbols is inserted at the beginning of each segment, and a field synchronization signal is inserted at the beginning of the field. Segment sync signal has a length of four symbols compared to the length of the entire segment consisting of 832 symbols, but this causes degradation of synchronization performance. In order to overcome this deterioration, the data segment synchronization signal is overcome by inserting the data segment synchronization signal at a predetermined position, that is, at the beginning of each segment.

In order to detect a segment sync signal in a GA-HDTV system, a segment sync signal is first detected using a property of being periodically transmitted and a symbol clock is recovered using the segment sync signal. The detected segment sync signal is used not only for symbol clock recovery but also for automatic gain control (AGC). That is, the AGC mode of GA-HDTV system is largely divided into noncoherent AGC mode and coherent AGC mode. In the synchronous AGC mode, precise gain control is made by using the correlation value of the detected segment sync signal. Do it.

The receiver of the GA-HDTV system detects the intermediate frequency signal and the synchronization signal by passing the intermediate frequency signal output from the tuner to the intermediate frequency filter and the synchronization detector to recover the symbols. Since the synchronization signal is detected first in the baseband signal processing, the detection of the segment synchronization signal is a factor in determining the performance of the initial synchronization of the system.

In the GA-HDTV system, the segment synchronization signal and the field synchronization signal are transmitted at regular intervals to achieve frame synchronization between the transmitter and the receiver. The segment synchronizing signal detecting unit performs a function of detecting the position of the segment synchronizing signal by using a correlation value between the segment synchronizing signal transmitted at a predetermined interval and a reference pattern determined by a known segment synchronizing signal.

On the other hand, since the receiver performs the restoration of the symbol clock and the automatic gain adjustment by using the detected segment synchronization signal, the segment synchronization detector must keep track of the position of the segment synchronization signal. However, there is a case where the position of the segment sync signal obtained by a temporary operation error or impulse noise of the transmitter or receiver is lost. In order to prevent the loss of the segment sync signal, it is necessary to have a function of restoring the lost segment sync signal again.

3 is a block diagram showing the configuration of a conventional segment sync signal detector. The segment sync correlator 31 calculates and outputs a correlation value of the I-channel signal component of the sampled VSB signal inputted from the intermediate frequency filter and the sync detector with the reference pattern determined by the known segment sync signal. The adder 32 adds and outputs a correlation value corresponding to the same position in the current segment and the previous segment correlation value. The memory 33 stores the correlation value output from the adder 32 and outputs the stored correlation value to the adder 32 so that the correlation value is cumulatively calculated. The control logic generator 34 generates a read and write signal for controlling the memory 33. The peak detector 35 detects the position of the maximum value among the accumulated correlation values.

The I-channel signal component of the sampled VSB signal without symbol clock synchronization is used to calculate a correlation value with the reference pattern determined by the segment sync signal which already knows the values sampled in the segment sync correlator 31. . The calculated correlation values are cyclically accumulated in the memory 33 over several segment periods, and since the correlation values calculated by each segment synchronizing signal have a constant direction, the value increases gradually as they accumulate for several segment periods. Since random data that are not segment sync signals are independent of each other and can be regarded as random variables having an average value of 0, when the correlation values are accumulated over a sufficient number of segments, the cumulative result is accumulated by the segment sync signals. It will appear smaller than the correlation value. Therefore, the segment sync signal detector finds the position of the symbol having the maximum value among the accumulated correlation values and determines the position of the segment sync signal.

However, the segment sync signal detector has to be designed to be robust against timing errors because the sync signal must be detected in a situation where timing recovery is not performed. When sampling is performed at the correct position (timing) for each input symbol, the difference between the correlation value accumulated at the synchronization signal position and the correlation value accumulated at an arbitrary data position may appear much larger than when a sampling error exists. have. As shown in Fig. 4A, when sampling is performed once per symbol, the worst sampling point 44 is the point where the optimum sampling point 41, amplitude error 42, and phase error 43 become the largest. (Worst Case Sampling Point) may occur, the worst sampling error may exist, which may be a factor that makes it difficult to detect the synchronization signal.

However, as shown in Fig. 4 (B), if each sample is sampled twice at two sampling positions (15, 16) and the segment synchronization signal is taken at a larger position, the segment synchronization signal is less susceptible to timing error. Can be detected.

The present invention is to solve the above problems,

SUMMARY OF THE INVENTION An object of the present invention is to provide a segment synchronization signal detection apparatus of a digital television receiver, which is capable of correcting a timing error and is not affected by the timing error.

It is another object of the present invention to provide a segment synchronization signal detection apparatus of a digital television receiver which is robust to timing errors by selecting a larger value among the correlation values accumulated at each sampling position by sampling twice per symbol.

In order to achieve the above object, the apparatus for detecting a segment synchronization signal according to the present invention samples twice for each symbol, accumulates a correlation value calculated for the two samples, and has a larger cumulative value among the accumulated values of the two samples. By taking the segment sync signal at the symbol corresponding to the position of the segment sync signal, it is possible to detect the segment sync signal with less amplitude error and phase error. Therefore, as in the case of sampling once per symbol, the worst sampling point does not exist, thereby designing a segment sync signal detector which is less susceptible to timing errors. In addition, by dividing the input data into even (EVEN) and odd (ODD) sequence, it is possible to operate by lowering the operating frequency to the symbol rate.

A segment synchronization signal correlator; Memory; A maximum value position detector; It consists of a loss detector and a size comparator. The segment sync signal detector operates on an input signal at twice the speed of the symbol clock to operate without being affected by timing errors, and performs timing recovery in the next stage. In addition, the processing speed can be reduced by processing the signals input twice as much as the symbol clock, and by dividing the input signal into even and odd columns, the correlation value is accumulated for each signal sequence, and the maximum value is found and compared in the size comparator. Is used as a selection signal to detect a large column and determine the position of the segment synchronization signal.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 (A) and (B) are structural diagrams of a segment synchronization signal used in a GA-HDTV system.

2 is a structural diagram of a transmission data frame used in a GA-HDTV system.

3 is a block diagram showing the configuration of a conventional segment sync signal detector.

4A illustrates a case where sampling is performed once per symbol.

4B shows a case of sampling twice at two sampling positions per symbol.

5 is a block diagram showing the configuration of a segment synchronization signal detector according to the present invention.

Figure 6 (A) is a block diagram showing the configuration of a signal classifier applied to the present invention,

Fig. 6B is a timing diagram of the input / output signals.

7 is a block diagram showing the configuration of a peak detector according to the present invention.

8 is a block diagram showing a configuration of a maximum value comparison and position detection unit according to the present invention.

Explanation of symbols for the main parts of the drawings

50: A / D converter 51: Signal classifier

52, 53: first and second segment sync correlator 54, 55: first and second adder

56, 57: first and second memory 58: control logic generation unit

59: peak detector 60: multiplexer

Fig. 5 is a block diagram showing the configuration of the segment sync signal detector according to the present invention.

The A / D converter 50 samples the intermediate frequency signal at 21.52 MHz, locks the phase, and outputs it. Signal classifier 51 is A / D change section 50 and DFPLL (56) to shift an even signal (even) and the odd-numbered signal by the symbol signal input to the 21.52 MHz via (odd to be sampled has a random timing phase error And print it out. The first segment sync correlator 52 correlates with the reference pattern of the symbol clock signal determined by the segment synchronizing signal which already knows the even-numbered sampled I-channel signal component inputted from the signal classifier 51. Calculate and output The second segment sync correlator 53 correlates with the reference pattern of the symbol clock signal determined by the segment synchronizing signal which already knows the sampled I-channel signal component corresponding to the odd number input from the signal classifier 51. Calculate and output The first adder 54 and the second adder 55 add and output a correlation value corresponding to the same position in the previous segment and the current segment. The first memory 56 stores the correlation value output from the first adder 54 and outputs the stored correlation value to the first adder 54 so that the correlation value is cumulatively calculated. The second memory 57 stores the correlation value output from the second adder 55 and outputs the stored correlation value to the second adder 55 so that the correlation value is cumulatively calculated. The control logic generation unit 58 generates a read, write signal and a clear signal for controlling the first and second memories 56 and 57. The peak detector 59 detects and outputs the maximum value and its position among the correlation values accumulated by the first and second adders 54 and 55. The maximum value comparator 60 compares the cumulative maximum correlation value of the first adder 54 outputted from the peak detector 59 with the cumulative maximum correlation value of the second adder 55, and selects a larger one. 61 is used as the selection signal. The multiplexer 61 selects one of cumulative maximum correlation values of the first and second adders 54 and 55 output from the peak detector 59 according to the signal output from the maximum comparator 60. Output

Hereinafter, the operation and effect of the present invention will be described with reference to the drawings.

The signal passing through the tuner and the intermediate frequency processor A / D change unit 50 is locked to the frequency and phase through a carrier recovery unit. The 21.52 MHz symbol signal output from the DFPLL 50 'is input to the signal classifier 51 and alternately classified into an even signal and an odd signal.

Fig. 6A is a block diagram showing the configuration of the signal classifier applied to the present invention, and Fig. 6B is a timing diagram of the input / output signals.

The signal classifier 51 according to the present invention receives a 21.52 MHz symbol signal output from the DFPLL 50 'as its input terminal D and a first D flip-flop 61 which receives a 10.76 MHz signal as its clock terminal. And a second D flip-flop that receives a 21.52 MHz symbol signal output from the A / D conversion unit 50 through its input terminal D, inverts the 10.76 MHz signal into the inverter 63, and receives its clock terminal. 62). The 21.52 MHz symbol signal output from the A / D converter 50 is input to the input terminal D of the first D flip-flop 61 and 21.52 at the rising edge of the 10.76 MHz clock signal b. Even pulses P ₀ , P ₂ ,... Among the pulses constituting the MHz symbol signal a are output from the output terminal Q (see (d) of FIG. 6 (B)). On the other hand, the symbol signal a input to the input terminal D of the 2D flip-flop 62 receives the 21.52 MHz symbol signal a at the rising edge of the inverted signal c of the 10.76 MHz clock signal. The odd pulses P ₁ , P ₃ ,..., Constituting the pulses are output from the output terminal Q (see (e) of FIG. 6 (B)).

The even-numbered even pulses P ₀ , P ₂ ,... Output from the signal classifier 51 are input to the first segment sync correlator 52 to determine a symbol clock determined by a segment synchronization signal known in advance. The output is correlated with the reference pattern of the signal. Similarly, the odd-numbered pulses P ₁ , P ₃ ,... Output from the signal classifier 51 are input to the second segment sync correlator 53 to determine a symbol clock determined by a segment synchronization signal known in advance. The output is correlated with the reference pattern of the signal.

The signals output from the first and second segment sync correlators 52 and 53 are input to the first adder 54 and the second adder 55 so that a correlation value corresponding to the same position in the previous segment and the current segment is obtained. Is added. The signal output from the first segment sync correlator 52 is input to the first adder 54 and added to the signal output from the first memory 56. The correlation signal added by the first adder 54 is stored in the first memory 56. The first memory 56 has a structure of FIFO (First In First Out) and has a size of 832 bits corresponding to the length of one segment. The control logic generation unit 58 alternately controls the write and read states until 832 symbols are stored in the first memory 56, and is added to the first adder 54 in the write state. And stores the output signal in the first memory 56. Then, the oldest signal among the signals stored in the first memory 56 is read and applied to the first adder 54 in the read state. The same matters regarding the first memory 56 apply to the second memory 57 as well.

Fig. 7 is a block diagram showing the configuration of the peak detector according to the present invention.

The peak detector 59 according to the present invention receives the even-number correlation value and the odd-number correlation value accumulated in the first adder 54 and the second adder 55, respectively, and obtains a maximum value and a segment sink for each. It consists of two parts of the same configuration to detect. Here, a part of detecting the maximum value and the segment sink in the even correlation value output from the first adder 54 will be described.

The maximum value comparison and position detection unit 71 detects the position of the maximum value symbol by comparing the correlation value of the current symbol inputted by the first adder 54 with the correlation value of the previous symbol, and accumulates the number of times by a predetermined number of segments. An update signal generator 73 for generating an update signal in the segment, and the maximum value comparison and position detector 71 receives the position of the maximum symbol and the position of the current symbol and generates a segment sync signal when the two values match. The segment sync generator 72 and the maximum value comparison and position detector 71 receive the position of the maximum symbol and the position of the current symbol and accumulate a predetermined number of times to obtain the position of the maximum value obtained from the current accumulation and the previous accumulation. A maximum position storing unit 74 for comparing the obtained maximum position and outputting a segment lock signal seq_lock to the segment sync generating unit 72 when the maximum position is the same; The segment sync checker 75 which compares the position of the maximum symbol with the position of the maximum symbol found in the cumulative process by the large value comparison and position detector 71 to determine a loss state and generates an initialization signal (lose_lock) when the loss is lost. It consists of.

8 is a block diagram showing the configuration of the maximum value comparison and position detection unit according to the present invention.

The comparator 81 outputs one signal when the correlation value of the current symbol is large by comparing the correlation value of the current symbol input from the first adder 54 and the input value of the first adder 54. A flip-flop unit 82 for receiving and outputting a signal from the comparator 81 by receiving a correlation value of a current symbol, a 832 modular counter 83 for counting a 10.76 MHz clock signal, and the 832 modular A 32 modular counter 84 for counting a carry signal output from the counter 83, an AND gate U _{1 for} receiving and carrying a carry from the 832 modular counter 83 and the 32 modular counter 84, and The first latch unit 85 receives the count signal from the 832 modular counter 83 and outputs the count signal output from the first latch unit 85 when the first signal is output from the comparator 81. the first signal receiving output from the AND gate (U ₁₎ It consists of the second latch section 86 for outputting by.

The comparator 81 compares the correlation value of the current symbol output from the first adder 54 and the correlation value of the previous symbol output from the flip-flop unit 82 and outputs one signal when the correlation value of the current symbol is large. . The flip-flop unit 82 receives a correlation value of the current symbol input from the first adder 54 to the input terminal, receives one signal from the comparator 81, and outputs the signal to the comparator 81. Therefore, when the correlation value of the current symbol output from the first adder 54 is not greater than the correlation value of the previous symbol output from the flip-flop unit 82, the correlation value of the previous symbol output from the flip-flop unit 82. Is the same value, and if the correlation value of the current symbol is larger than the correlation value of the previous symbol output from the flip-flop unit 82, the correlation value of the previous symbol output from the flip-flop unit 82 is The correlation value is changed.

On the other hand, the 832 modular counter 83 counts a 10.76 MHz clock signal and outputs the position of the current symbol, which is a count result, to the first latch unit 85, and the first latch unit 85 latches the count result. When the comparator 81 outputs a signal that the correlation value of the current symbol is greater than the correlation value of the previous symbol, the comparator 81 outputs the signal to the second latch unit 86. Further, the carry C ₁ output from the 832 modular counter 83 is output to the 32 modular counter 84 and the end gate U ₁ . 32 modular counter 84, and outputs to the carry AND gate with the carry (C ₂₎ by counting the (C ₁₎ at the 32nd count (U _1). To the AND gate (U ₁₎ outputs a first signal to the carry (C ₁₎ and 32 carry a second latch section 86 to end calculating the (C ₂₎ of the modular counter 84 of 832 modular counter 83, the The maximum value position signal applied to the input terminal of the two latches 86 is outputted. Since the peak detector 59 according to the present invention is composed of two parts of the same configuration including the configuration described above for the even correlation value and the odd correlation value output from the first adder 54 and the second adder 55. In this case, the description of the part of detecting the maximum value and the segment sync in the even correlation value output from the first adder 54 is equally applicable to the odd correlation value output from the second adder 55.

The even maximum correlation value max_even and the odd maximum correlation value max_odd output from the peak detector 59 are inputted to the maximum value comparator 60 and compared. The even maximum correlation value max_even is an odd maximum correlation. If greater than the value max_odd, a signal for selecting even-segment sync is output to the multiplexer 61. The multiplexer 61 receives an even segment sync sync_even and an odd segment sync sync_odd from the segment sync generator 72 of the peak detector 59 according to a comparison result signal input from the maximum comparator 60. An even segment sync (sync_even) or an odd segment sync (sync_odd) is selected and output.

As described above, according to the present invention, the segment sync detector is robustly designed against timing errors and is not affected by the timing error. Sampling at fewer sampling points enables faster timing recovery after segment sync signal detection.

Claims (8)

In the segment synchronization signal detection apparatus of high-definition television, An A / D converter for sampling an intermediate frequency signal from the A / D converter and a DFPLL for locking the phase; A signal classifier for alternately classifying the symbol signal input from the DFPLL into an even signal and an odd signal; First and second segment sinks that calculate and output a reference pattern and a correlation value of a symbol clock signal determined by a segment synchronizing signal previously known for even-numbered and odd-numbered sampled signal signals input from the signal classifier. A correlator; A first adder and a second adder for adding and outputting a previous segment correlation value and a correlation value corresponding to the same position in the current segment; First and second memories for storing correlation values output from the first and second adders and outputting the stored correlation values to the first and second adders to accumulate correlation values; A control logic generator for generating signals for controlling the first and second memories; A peak detector for respectively detecting a maximum value and a position among correlation values accumulated and output from the first and second adders; A multiplexer for selecting and outputting one of cumulative maximum correlation values of the first and second adders output from the peak detector; And a maximum value comparator for outputting a signal for selecting a larger one by comparing the cumulative maximum correlation value of the first adder and the cumulative maximum correlation value of the second adder output from the peak detector. Segment synchronization signal detection device of a receiver. The segment synchronization signal of claim 1, wherein the signal classifier classifies the symbol signal output from the DFPLL into an even signal in a period of high symbol clock and an odd signal in a low period. Detection device. The 1D flip-flop of claim 1, wherein the signal classifier receives a 21.52 MHz symbol signal output from the DFPLL as its input terminal, and receives a 10.76 MHz signal as its clock terminal. And a second D flip-flop that receives the output 21.52 MHz symbol signal through its input terminal D, inverts the 10.76 MHz signal into an inverter, and receives it as its clock terminal. Synchronous signal detection device. The apparatus of claim 1, wherein the reference patterns of the first and second segment sync correlators correspond to respective symbol values of a segment sync signal having a length of four symbols. The apparatus of claim 1, wherein the adder accumulates a correlation value by adding a signal output from the segment sync correlator and a signal output from a memory. The method of claim 1, wherein the peak detector The digital television receiver according to claim 1, wherein the first adder and the second adder receive the even correlation value and the odd correlation value, respectively, and are composed of two parts having the same configuration for detecting the maximum value and the segment sync for each of the first and second adders. Segment synchronization signal detection device. The method of claim 6, wherein the peak detector, A maximum value comparison and position detection unit for detecting a position of the maximum value symbol by comparing the correlation value of the current symbol with the correlation value of the previous symbol input from the first adder; An update signal generator for accumulating the positions of the maximum value symbols output from the maximum value comparison and position detector by a predetermined number of segments and generating an update signal in the last accumulated segment; A segment sync generator which receives the position of the maximum symbol and the position of the current symbol from the maximum value comparison and position detector and generates a segment sync signal when the two values match; The maximum value comparison and position detection unit receives the position of the maximum symbol and the position of the current symbol accumulates a predetermined number of times and compares the position of the maximum value obtained from the current accumulation and the maximum value obtained from the previous accumulation, the segment sync occurs when the same A maximum value position storage unit which outputs a segment lock signal seq_lock by a negative value; The maximum value comparison and position detection unit receives the position of the maximum symbol and the position of the maximum symbol obtained from the current accumulation, and determines the loss state of the segment synchronization signal to the segment sync check unit that generates an initialization signal (lose_lock). 8 V S Segment synchronization signal detection device characterized in that the configuration. The method of claim 7, wherein the maximum value comparison and position detection unit, A comparator configured to compare a correlation value of a current symbol input from the first adder with a correlation value of a previous symbol and output one signal when the correlation value of the current symbol is large; A flip-flop unit which receives a correlation value of a current symbol input from the first adder to an input terminal and receives and outputs one signal from the comparator; 832 modular counter for counting 10.76 MHz clock signals; A 32 modular counter for counting a carry signal output from the 832 modular counter; An AND gate receiving and carrying a carry from the 832 modular counter and the 32 modular counter; A first latch unit receiving a count signal from the 832 modular counter and outputting the count signal when one signal is output from the comparator; And a second latch unit for receiving the count signal output from the first latch unit and outputting the count signal output from the AND gate.