[go: up one dir, main page]

KR19990046833A - Thin film transistor for liquid crystal display device and manufacturing method - Google Patents

Thin film transistor for liquid crystal display device and manufacturing method Download PDF

Info

Publication number
KR19990046833A
KR19990046833A KR1019970051745A KR19970051745A KR19990046833A KR 19990046833 A KR19990046833 A KR 19990046833A KR 1019970051745 A KR1019970051745 A KR 1019970051745A KR 19970051745 A KR19970051745 A KR 19970051745A KR 19990046833 A KR19990046833 A KR 19990046833A
Authority
KR
South Korea
Prior art keywords
amorphous silicon
film
silicon film
insulating film
concentration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
KR1019970051745A
Other languages
Korean (ko)
Other versions
KR100490041B1 (en
Inventor
김주희
Original Assignee
윤종용
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 윤종용, 삼성전자 주식회사 filed Critical 윤종용
Priority to KR1019970051745A priority Critical patent/KR100490041B1/en
Publication of KR19990046833A publication Critical patent/KR19990046833A/en
Application granted granted Critical
Publication of KR100490041B1 publication Critical patent/KR100490041B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes

Landscapes

  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

액정 표시 장치용 박막 트랜지스터의 활성층을 다결정 규소와 비정질 규소의 이중막으로 형성한다. 이러한 박막 트랜지스터를 형성하기 위하여는, 게이트 절연막으로 니켈, 구리, 팔라듐 등의 금속 원자가 혼합되고 Si-O 기가 함유된 가시 광선 투과율이 높은 유기 절연막을 이용하며, 그 위에 수소의 농도가 10% 이상이며 다른 불순물의 농도는 5E+19/㎤ 이하인 비정질 규소막과 탄소, 산소, 질소 중 적어도 하나의 농도가 5E+20/㎤ 이상인 비정질 규소막을 차례로 증착한다. 기판의 전면에서 엑시머 레이저 어닐링을 하여 하부 규소막의 결정화를 통한 다결정 규소막을 형성한다. 이 때 하부 규소막 위에 형성되어 있는 상부 규소막은 Eopt(optical band gap)이 커서 레이저의 에너지를 많이 흡수하지 못하므로 비정질 상태로 유지되고, 하부 규소막은 수소의 농도가 높고 하부 규소막 아래의 유기 절연막에 포함되어 있는 니켈, 구리, 팔라듐 등의 금속 원자가 열에 녹아 하부 규소막으로 녹아 들어가 촉매 역할을 하므로 결정화가 잘 된다. 따라서 낮은 파워의 레이저로도 결정화가 가능하게 되어 상부 규소막의 비정질 규소의 결정화를 억제할 수 있다.The active layer of the thin film transistor for liquid crystal display device is formed of a double film of polycrystalline silicon and amorphous silicon. In order to form such a thin film transistor, an organic insulating film having a high visible light transmittance in which metal atoms such as nickel, copper and palladium are mixed and containing Si—O groups is used as the gate insulating film, and the concentration of hydrogen is 10% or more thereon. The other impurity concentration is deposited in an amorphous silicon film having a concentration of 5E + 19 / cm 3 or less, and an amorphous silicon film having a concentration of at least one of carbon, oxygen, and nitrogen of 5E + 20 / cm 3 or more. Excimer laser annealing is performed on the entire surface of the substrate to form a polycrystalline silicon film through crystallization of the lower silicon film. At this time, the upper silicon film formed on the lower silicon film is kept in an amorphous state because the optical band gap (Eopt) is large and does not absorb much energy of the laser. Metal atoms such as nickel, copper, and palladium contained in melt in heat, melt into the lower silicon film, and act as a catalyst, thereby crystallizing well. Therefore, crystallization is possible even with a laser of low power, and the crystallization of amorphous silicon of the upper silicon film can be suppressed.

Description

액정 표시 장치용 박막 트랜지스터 및 제조 방법Thin film transistor for liquid crystal display device and manufacturing method

본 발명은 액정 표시 장치용 박막 트랜지스터 및 그 제조 방법에 관한 것이다.The present invention relates to a thin film transistor for a liquid crystal display device and a manufacturing method thereof.

액티브 매트릭스(active matrix) 액정 표시 장치의 스위칭 소자로 많이 이용되는 박막 트랜지스터의 경우, 비정질 규소(amorphous silicon)나 다결정 규소(polysilicon)를 활성층으로 주로 사용한다.In the case of a thin film transistor that is frequently used as a switching element of an active matrix liquid crystal display, amorphous silicon or polysilicon is mainly used as an active layer.

비정질 규소를 활성층으로 하는 박막 트랜지스터는 저온에서 증착이 가능하며 박막 트랜지스터의 누설 전류(leakage current)가 낮다는 이점이 있으나 전자의 이동도(mobility)가 낮아 대화면 동화상 표시 장치에의 적용이 어렵다는 단점을 가지고 있다.Thin film transistors using amorphous silicon as an active layer can be deposited at low temperatures and have a low leakage current. However, low mobility of electrons makes it difficult to be applied to a large screen moving image display device. Have.

한편, 다결정 규소를 활성층으로 하는 박막 트랜지스터는 비정질 규소 박막 트랜지스터에 비해 2자리수 정도 큰 전자 이동도를 갖고 있으나, 비저항이 작아 누설 전류가 크다는 단점을 가지고 있다.On the other hand, a thin film transistor using polycrystalline silicon as an active layer has an electron mobility of about two orders of magnitude as compared to an amorphous silicon thin film transistor, but has a disadvantage in that a leakage current is large due to a small specific resistance.

본 발명의 과제는 높은 전자 이동도와 낮은 누설 전류를 갖는 박막 트랜지스터를 구현하는 것이다.An object of the present invention is to implement a thin film transistor having high electron mobility and low leakage current.

도 1은 본 발명의 실시예에 따른 박막 트랜지스터 기판의 단면도이다.1 is a cross-sectional view of a thin film transistor substrate according to an exemplary embodiment of the present invention.

이와 같은 과제를 해결하기 위하여 본 발명에서는 전자 이동도가 높은 다결정 규소와 누설 전류가 낮은 비정질 규소의 다중막을 활성층으로 하는 박막 트랜지스터를 형성한다.In order to solve such a problem, in the present invention, a thin film transistor including a multi-layer of polycrystalline silicon having high electron mobility and amorphous silicon having a low leakage current as an active layer is formed.

이제 본 발명의 실시예에 대하여 첨부된 도면을 참고로 하여 상세히 설명한다.Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

도 1은 본 발명의 실시예에 따른 박막 트랜지스터 기판의 단면도이다.1 is a cross-sectional view of a thin film transistor substrate according to an exemplary embodiment of the present invention.

도 1에 나타난 바와 같이, 유리 등의 투명한 절연 기판(10) 위에 게이트 전극(2)이 형성되어 있고, 게이트 전극(2) 위에 게이트 절연막(3)이 전면적으로 형성되어 있다. 게이트 절연막(3)은 니켈, 구리, 팔라듐(Pd ; palladium) 등 금속 원자가 혼합되고 Si-O 기가 함유된 가시 광선 투과율이 높은 유기 절연막으로 형성되어 있다. 이러한 유기 절연막을 게이트 절연막으로 이용하는 것은 유기 절연막에 함유된 Si-O기로 인하여 이후에 게이트 절연막(3) 위에 형성되는 다결정 규소막(4)의 계면 특성이 우수하게 되기 때문이다.As shown in FIG. 1, the gate electrode 2 is formed on the transparent insulating substrate 10, such as glass, and the gate insulating film 3 is formed on the gate electrode 2 whole surface. The gate insulating film 3 is formed of an organic insulating film having a high visible light transmittance in which metal atoms such as nickel, copper, and palladium (Pd; palladium) are mixed and containing Si—O groups. This organic insulating film is used as the gate insulating film because the Si-O group contained in the organic insulating film makes excellent the interfacial characteristics of the polycrystalline silicon film 4 formed on the gate insulating film 3 later.

게이트 전극(2) 상부의 게이트 절연막(3) 위에는 다결정 규소막(4)이 형성되어 있고, 그 위에 비정질 규소막(5)과 저항 접촉층으로 이용되는 고농도로 도핑된 n+ 비정질 규소막(61, 62)이 차례로 형성되어 있다.The polysilicon film 4 is formed on the gate insulating film 3 on the gate electrode 2, and the highly doped n + amorphous silicon film 61 used as the ohmic contact film 5 and the ohmic contact layer is formed thereon. 62 are formed one after the other.

n+ 비정질 규소막(61, 62)의 상부에는 게이트 전극(2)을 중심으로 양쪽으로 소스 전극(71)과 드레인 전극(72)이 형성되어 있다. 그 위에는 드레인 전극(72)을 노출시키는 접촉 구멍(contact hole)을 가지고 있는 보호막(8)이 형성되어 있다. 보호막(8) 위에는 ITO(indium tin oxide) 등의 투명 도전 물질로 이루어져 있으며 보호막에 형성되어 있는 접촉 구멍을 통하여 드레인 전극(72)과 연결되는 화소 전극(9)이 형성되어 있다.The source electrode 71 and the drain electrode 72 are formed on both sides of the n + amorphous silicon films 61 and 62 around the gate electrode 2. On it, a protective film 8 having a contact hole for exposing the drain electrode 72 is formed. On the passivation layer 8, a pixel electrode 9 made of a transparent conductive material such as indium tin oxide (ITO) and the like is connected to the drain electrode 72 through a contact hole formed in the passivation layer.

이제, 본 발명의 실시예에 따른 박막 트랜지스터 기판을 제조하는 방법에 대하여 설명한다.Now, a method of manufacturing a thin film transistor substrate according to an embodiment of the present invention will be described.

먼저, 유리 등의 투명한 절연 기판(10) 위에 금속을 증착하고 패터닝하여 게이트 전극(2)을 포함하는 게이트 패턴을 형성한다. 다음, 니켈, 구리, 팔라듐(Pd ; palladium) 등 금속 원자가 혼합되고 Si-O 기가 함유된 가시 광선 투과율이 높은 유기 절연막(3)을 코팅한다.First, a metal is deposited and patterned on a transparent insulating substrate 10 such as glass to form a gate pattern including the gate electrode 2. Next, nickel, copper, palladium (Pd; palladium), such as metal atoms are mixed, and the organic insulating film 3 having a high visible light transmittance containing a Si-O group is coated.

그 위에 수소의 농도가 10% 이상이며 다른 불순물의 농도는 5E+19/㎤ 이하인 비정질 규소막(이하 "하부 규소막"이라 한다)을 증착한다. 그리고, 그 위에 탄소, 산소, 질소 중 적어도 하나의 농도가 5E+20/㎤ 이상인 비정질 규소막(이하 "상부 규소막"이라 한다)을 증착한다.An amorphous silicon film (hereinafter referred to as "lower silicon film") having a concentration of hydrogen of 10% or more and other impurities of 5E + 19 / cm 3 or less is deposited thereon. Then, an amorphous silicon film (hereinafter referred to as "upper silicon film") having a concentration of at least one of carbon, oxygen, and nitrogen of 5E + 20 / cm 3 or more is deposited thereon.

기판의 전면에서 엑시머 레이저 어닐링(ELA ; excimer laser annealing)을 하여 하부 규소막을 결정화하여 다결정 규소막을 형성한다. 이 때 하부 규소막 위에 형성되어 있는 상부 규소막은 Eopt(optical band gap)이 커서 레이저의 에너지를 많이 흡수하지 못하므로 비정질 상태로 유지되고, 하부 규소막은 수소의 농도가 높고 하부 규소막 아래의 유기 절연막에 포함되어 있는 니켈, 구리, 팔라듐 등의 금속 원자가 열에 녹아 하부 규소막으로 녹아 들어가 촉매 역할을 하므로 결정화가 잘 된다. 따라서 낮은 파워의 레이저로도 결정화가 가능하게 되어 상부 규소막의 비정질 규소의 결정화를 억제할 수 있다. 다음, 불산(HF) 용액을 사용하여 상부 규소막 위에 형성된 오염막을 제거한다. 그리고, 상부 규소막 위에 고농도로 도핑된 n+ 비정질 규소막을 증착하고, 3개의 규소막을 함께 패터닝한다.An excimer laser annealing (ELA) is performed on the entire surface of the substrate to crystallize the lower silicon film to form a polycrystalline silicon film. At this time, the upper silicon film formed on the lower silicon film is kept in an amorphous state because the optical band gap (Eopt) is large and does not absorb much energy of the laser. The lower silicon film has a high concentration of hydrogen and an organic insulating film under the lower silicon film. Metal atoms such as nickel, copper, and palladium contained in melt in heat, melt into the lower silicon film, and act as a catalyst, thereby crystallizing well. Therefore, crystallization is possible even with a laser of low power, and the crystallization of amorphous silicon of the upper silicon film can be suppressed. Next, a fouling film formed on the upper silicon film is removed using a hydrofluoric acid (HF) solution. Then, a highly doped n + amorphous silicon film is deposited on the upper silicon film, and the three silicon films are patterned together.

다음, 금속을 증착하고 패터닝하여 소스/드레인 전극(71, 72)을 포함하는 데이터 패턴을 형성한다. 그리고, 소스/드레인 전극(71, 72)을 마스크로 하여 n+ 비정질 규소막을 식각한다.Next, a metal is deposited and patterned to form a data pattern including the source / drain electrodes 71 and 72. Then, the n + amorphous silicon film is etched using the source / drain electrodes 71 and 72 as masks.

그 위에 보호막(8)을 증착하여 패터닝하고, 마지막으로 화소 전극(9)을 증착하고 패터닝하여 박막 트랜지스터 기판을 완성한다.The protective film 8 is deposited thereon and patterned, and finally, the pixel electrode 9 is deposited and patterned to complete the thin film transistor substrate.

본 발명에서와 같이, 다결정 규소와 비정질 규소의 이중막으로 박막 트랜지스터의 활성층을 형성함으로써 높은 전자 이동도와 낮은 누설 전류를 갖는 박막 트랜지스터를 얻을 수 있다.As in the present invention, a thin film transistor having high electron mobility and low leakage current can be obtained by forming an active layer of a thin film transistor using a double film of polycrystalline silicon and amorphous silicon.

Claims (10)

게이트 전극,Gate electrode, 상기 게이트 전극 위에 형성되어 있는 게이트 절연막,A gate insulating film formed on the gate electrode, 상기 게이트 전극 상부의 상기 게이트 절연막 위에 형성되어 있는 다결정 규소층,A polysilicon layer formed on the gate insulating film over the gate electrode, 상기 다결정 규소층 위에 형성되어 있는 비정질 규소층,An amorphous silicon layer formed on the polycrystalline silicon layer, 상기 비정질 규소층 위에, 상기 게이트 전극을 중심으로 양쪽으로 형성되어 있는 소스 전극 및 드레인 전극을 포함하는 액정 표시 장치용 박막 트랜지스터.And a source electrode and a drain electrode formed on both sides of the gate electrode on the amorphous silicon layer. 제1항에서,In claim 1, 상기 비정질 규소층 위에 형성되어 있는 도핑된 비정질 규소층을 더 포함하는 액정 표시 장치용 박막 트랜지스터.And a doped amorphous silicon layer formed on the amorphous silicon layer. 제2항에서,In claim 2, 상기 게이트 절연막은 니켈, 구리, 팔라듐 등의 금속 원자가 혼합되고 Si-O기가 함유된 유기 절연막으로 이루어진 액정 표시 장치용 박막 트랜지스터.The gate insulating film is a thin film transistor for a liquid crystal display device comprising an organic insulating film containing a Si-O group mixed with a metal atom, such as nickel, copper, palladium. 제3항에서,In claim 3, 상기 비정질 규소층은 탄소, 산소, 질소 중 적어도 하나의 농도가 5E+20/㎤ 이상인 비정질 규소로 이루어진 액정 표시 장치용 박막 트랜지스터.And the amorphous silicon layer is formed of amorphous silicon having a concentration of at least one of carbon, oxygen, and nitrogen of 5E + 20 / cm 3 or more. 투명 기판 위에 게이트 전극을 형성하는 단계,Forming a gate electrode on the transparent substrate, 상기 게이트 전극 위에 게이트 절연막을 형성하는 단계,Forming a gate insulating film on the gate electrode; 상기 게이트 절연막 위에 하부 비정질 규소막을 증착하는 단계,Depositing a lower amorphous silicon film on the gate insulating film, 상기 하부 비정질 규소막 위에 상부 비정질 규소막을 증착하는 단계,Depositing an upper amorphous silicon film on the lower amorphous silicon film, 상기 하부 비정질 규소막을 결정화하는 단계,Crystallizing the lower amorphous silicon film, 상기 상부 비정질 규소막 위에 도핑된 비정질 규소막을 증착하는 단계,Depositing a doped amorphous silicon film on the upper amorphous silicon film, 상기 3개의 규소막을 패터닝하는 단계,Patterning the three silicon films, 상기 도핑된 비정질 규소막 위에 소스 전극 및 드레인 전극을 형성하는 단계,Forming a source electrode and a drain electrode on the doped amorphous silicon film, 상기 소스 전극 및 드레인 전극을 마스크로 하여 상기 도핑된 비정질 규소막을 식각하는 단계를 포함하는 액정 표시 장치용 박막 트랜지스터의 제조 방법.And etching the doped amorphous silicon film using the source electrode and the drain electrode as masks. 제5항에서,In claim 5, 상기 게이트 절연막은 니켈, 구리, 팔라듐 중 적어도 하나의 금속 원자가 혼합되고 Si-O 기가 함유된 유기 절연막을 코팅하여 형성하는 액정 표시 장치용 박막 트랜지스터의 제조 방법.The gate insulating film is a method of manufacturing a thin film transistor for a liquid crystal display device formed by coating an organic insulating film containing at least one of the metal atoms of nickel, copper, palladium mixed with Si-O group. 제6항에서,In claim 6, 상기 하부 비정질 규소막은 수소의 농도가 10% 이상이며 다른 불순물의 농도는 5E+19/㎤ 이하인 비정질 규소로 형성하는 액정 표시 장치용 박막 트랜지스터의 제조 방법.And the lower amorphous silicon film is formed of amorphous silicon having a hydrogen concentration of 10% or more and another impurity concentration of 5E + 19 / cm 3 or less. 제7항에서,In claim 7, 상기 상부 비정질 규소막은 탄소, 산소, 질소 중 적어도 하나의 농도가 5E+20/㎤ 이상인 비정질 규소로 형성하는 액정 표시 장치용 박막 트랜지스터 기판의 제조 방법.And the upper amorphous silicon film is formed of amorphous silicon having a concentration of at least one of carbon, oxygen, and nitrogen of 5E + 20 / cm 3 or more. 제8항에서,In claim 8, 상기 하부 비정질 규소막을 결정화하는 단계는 상기 기판의 전면에서 엑시머 레이저 어닐링을 하는 단계인 액정 표시 장치용 박막 트랜지스터의 제조 방법.And crystallizing the lower amorphous silicon layer is an excimer laser annealing on the entire surface of the substrate. 제9항에서,In claim 9, 상기 엑시머 레이저 어닐링을 하는 단계 이후에 불산 용액을 사용하여 상부 비정질 규소막 위에 형성된 오염막을 제거하는 단계를 더 포함하는 액정 표시 장치용 박막 트랜지스터의 제조 방법.And removing the contaminant film formed on the upper amorphous silicon film by using a hydrofluoric acid solution after the excimer laser annealing.
KR1019970051745A 1997-10-09 1997-10-09 Thin Film Transistor for Liquid Crystal Display and Manufacturing Method Expired - Fee Related KR100490041B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019970051745A KR100490041B1 (en) 1997-10-09 1997-10-09 Thin Film Transistor for Liquid Crystal Display and Manufacturing Method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970051745A KR100490041B1 (en) 1997-10-09 1997-10-09 Thin Film Transistor for Liquid Crystal Display and Manufacturing Method

Publications (2)

Publication Number Publication Date
KR19990046833A true KR19990046833A (en) 1999-07-05
KR100490041B1 KR100490041B1 (en) 2005-09-15

Family

ID=37304767

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970051745A Expired - Fee Related KR100490041B1 (en) 1997-10-09 1997-10-09 Thin Film Transistor for Liquid Crystal Display and Manufacturing Method

Country Status (1)

Country Link
KR (1) KR100490041B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101026808B1 (en) * 2004-04-30 2011-04-04 삼성전자주식회사 Method of manufacturing thin film transistor array panel
US8202758B2 (en) 2005-12-08 2012-06-19 Samsung Electronics Co., Ltd. Thin film transistor array panel and method of manufacturing the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102823695B1 (en) 2021-06-25 2025-06-25 삼성디스플레이 주식회사 Pixel and organic light emitting diode display device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05226656A (en) * 1992-02-13 1993-09-03 Hitachi Ltd Thin film semiconductor device and manufacturing method thereof
JPH0855993A (en) * 1994-08-12 1996-02-27 Fuji Xerox Co Ltd Thin film transistor
KR0154817B1 (en) * 1995-08-25 1998-10-15 김광호 Thin film transistor for liquid crystal display device and manufacturing method thereof
JPH09172186A (en) * 1996-12-02 1997-06-30 Casio Comput Co Ltd Method for manufacturing thin film transistor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101026808B1 (en) * 2004-04-30 2011-04-04 삼성전자주식회사 Method of manufacturing thin film transistor array panel
US8202758B2 (en) 2005-12-08 2012-06-19 Samsung Electronics Co., Ltd. Thin film transistor array panel and method of manufacturing the same
KR101230305B1 (en) * 2005-12-08 2013-02-06 삼성디스플레이 주식회사 Thin film transistor array panel and method for manufacturing the same

Also Published As

Publication number Publication date
KR100490041B1 (en) 2005-09-15

Similar Documents

Publication Publication Date Title
US6537843B2 (en) Thin film transistor and method of manufacturing the same
US8049830B2 (en) Liquid crystal display device and fabrication method thereof
US20070019123A1 (en) Liquid crystal display panel and method of fabricating thereof
US7790582B2 (en) Method for fabricating polysilicon liquid crystal display device
KR100308854B1 (en) Manufacturing method of liquid crystal display device
US7015122B2 (en) Method of forming polysilicon thin film transistor
US7414691B2 (en) Liquid crystal display device with prevention of defective disconnection of drain/pixel electrodes by forming two conductive layers on top of entire pixel electrode and then removing a portion of both therefrom
KR20120007764A (en) Array substrate including thin film transistor using micro polysilicon and manufacturing method thereof
KR100490041B1 (en) Thin Film Transistor for Liquid Crystal Display and Manufacturing Method
KR100303711B1 (en) Thin film transistor with polycrystalline/amorphous double active layers
US7166501B2 (en) Method for fabricating polycrystalline silicon liquid crystal display device
KR20020090428A (en) Process for crystallizing amorphous silicon and its application - fabricating method of thin film transistor and TFT-LCD
US20050167634A1 (en) Etchant for nickel silicide
KR101599280B1 (en) Method of fabricating an array substrate
KR100539583B1 (en) Method for crystallizing Silicon and method for manufacturing Thin Film Transistor (TFT) using the same
KR20040050768A (en) Method of fabricating Thin Film Transistor for Liquid Crystal Display Device with driving circuit
KR101022569B1 (en) Thin film transistor and its manufacturing method
US8018545B2 (en) Method of fabricating a liquid crystal display device
KR100956938B1 (en) LCD and its manufacturing method
KR100749872B1 (en) Silicon Thin Film Transistor and Manufacturing Method Thereof
JPS62132367A (en) thin film field effect transistor
KR950003942B1 (en) Method of manufacturing thin film transistor for lcd
KR101258080B1 (en) Liquid crystal display device and method for fabricating thereof
KR0163901B1 (en) Ion Shower Doping Method and Structure
KR970005952B1 (en) Thin film transistor & method of manufacturing the same

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

D13-X000 Search requested

St.27 status event code: A-1-2-D10-D13-srh-X000

D14-X000 Search report completed

St.27 status event code: A-1-2-D10-D14-srh-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

R17-X000 Change to representative recorded

St.27 status event code: A-5-5-R10-R17-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R14-asn-PN2301

FPAY Annual fee payment

Payment date: 20130430

Year of fee payment: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

FPAY Annual fee payment

Payment date: 20140430

Year of fee payment: 10

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

FPAY Annual fee payment

Payment date: 20150430

Year of fee payment: 11

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 11

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20160510

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20160510

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000