KR19990018934A - Layout method of a nonvolatile semiconductor memory device having NOR cells - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a cell array out method of a semiconductor memory device, comprising: a transfer transistor for transferring a voltage of a bit line in a memory cell array; In a semiconductor memory device including cells, a ground and a bit line formed of metal regions, the active region of the cells are arranged in the same direction as the metal region of the bit line, the cell transistor is connected to the word line thereon The polys are sequentially arranged for the gates of the gates, and then the cells connected in parallel with the transfer transistors are connected to the conductive regions.

Description

Layout method of non-volatile semiconductor memory device having nor cells

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a cell layout method of a nonvolatile semiconductor memory device.

In recent years, semiconductor memory devices that are released in recent years tend to operate at low voltages or become complex semiconductor devices combining independent semiconductor devices. Therefore, development of a process and design technology for the low voltage memory cell should be accompanied. In general, random access memory (ROM) is divided into two types of cells. The first is a nand type, and the next is a nor type. It will layout the memory cell array.

1 is a partial illustration of a cell array of NAND structure.

Referring to FIG. 1, the cells are connected in series to a transistor to which a string select signal is applied as a gate. The main purpose is to minimize the area of the chip when the cells are laid out, because the increase in netdie will reduce the competitiveness of the product. The area is minimized by using the NAND structure as shown in FIG. In addition, when the array is formed of the NAND structure, not only the area of the chip may be reduced but also the operating current flows less.

FIG. 2 is a diagram illustrating the layout of FIG. 1, which shows a case where there are two string lines having the same structure as in FIG. 1.

Hereinafter, only the layout of one string line will be described. The metal regions 10a and 20 for the ground and the bit line exist, and the active region 30a for the cell transistors M1 to M32 is the metal region 10a. Is formed above. Cells are connected in series by sequentially arranging polys on the active region 30a for the gates of the cell transistors M1 to M32 to which the word lines W / Li are connected. Then the metal contacts for the bit lines and grounds complete the layout configuration.

3 shows cells with a NOR structure.

In the NOR structure, the word lines are connected to the gates, the drains are connected to the bit lines, and the cell transistors MR1 to MR32 which are grounded are connected to the selection transistors M0 in parallel. Therefore, as the cells are connected in parallel between the bit line and the ground, selecting any one of them has an advantage that the operation is performed smoothly, especially at low voltage and low current. 4 is a diagram illustrating a layout of NOR-type cells according to FIG. 3. In the NOR type, it can be seen that cells are connected to the bit line in parallel by forming channels in the active region and connecting the cells to the bit line and the ground. However, since chip area minimization is a top priority in product competition, the NAND structure is preferred to the NOR structure in which the cells are connected in parallel.

However, as described above, the NAND structure has the effect of reducing the area of the chip, but since all cells operate only when they are connected, a problem occurs that causes malfunction at low voltage and low current. In addition, the NOR structure has the advantage of easy operation at low voltage and low current, but the unit layout area is three times larger than the NAND structure using the same design rule, and the layout is more than six times when configuring the entire memory cell array. The problem is that the area is increased.

An object of the present invention is to provide a nonvolatile semiconductor memory device capable of operating at low voltage and low current, and also reducing the unit layout area of a chip by forming a NAND structure of a cell array having a NOR structure.

1 is a circuit diagram showing the configuration of one NAND cell unit constituting a memory cell array of a semiconductor memory device:

2 is a plan view showing a layout pattern for one NAND cell unit constituting a memory cell array:

3 is a circuit diagram illustrating a configuration of NOR cells constituting a memory cell array:

4 is a plan view showing a layout pattern of a portion of a memory cell array having a NORcell structure according to an embodiment of the present invention:

* Explanation of symbols on the main parts of the drawings

100a and 100b: metal regions 140a and 140b: first active region

160a, 160b: second active region 180a, 180b: conductive region

(Configuration)

According to one aspect of the present invention, a semiconductor memory device includes a transfer transistor for transferring a voltage of a bit line in a memory cell array, and cells connected in parallel to the transfer transistor. The bit line is formed of metal regions, the active regions of the cells are disposed in the same direction as the bit region of the metal region, and poly is sequentially arranged for the gate of the cell transistor to which the word line is connected. The cells connected in parallel with the transfer transistors are connected to a conductive area.

In a preferred embodiment, the conductive region is arranged in the same direction as the metal region which is the bit line.

In a preferred embodiment, the conductive region is characterized by weaker conductivity than metal and higher conductivity than resistance.

According to another aspect of the present invention, in a semiconductor memory device in which two transfer transistors and cells are connected in parallel to each transfer transistor in a memory cell array, an active region in which the transfer transistors are formed has one bit line on one side thereof. Are connected in common with each other, and the other is connected to ground, respectively, and two polys are arranged in a direction opposite to a bit line on the active region and connected in parallel with the transfer transistors for gates to which different transfer signals are applied. In order to connect the transistors, the conductive region, which is electrically conductive but resistive, is disposed in the same direction as the bit line.

(Example)

Hereinafter, a cell layout method of a semiconductor memory device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 3 to 4.

Referring to FIG. 4, a cell array having a NOR structure arranges polys in a line in an active region of cells similarly to a NAND structure, and a portion in which cells are commonly connected to each other in a select transistor is formed in a region different from a metal region. This can reduce the total chip area.

3 shows a portion of a cell array of a NOR structure.

Referring to FIG. 3, a cell array includes a select transistor M0 having a gate connected to a string select signal S / S, a drain connected to a bit line, and a source connected to cells in common, and a source of the transistor. The cells MR1 to MR32 are connected between one node and ground in parallel. This simply shows that the cells are separately connected to one selection transistor M0. The cells are transistors in which drains are commonly connected to the gate and the first node to which a word line is connected, and the sources are grounded.

4 is a diagram illustrating a layout of a NOR cell array, which illustrates a case in which one more cell array having the same configuration as that of FIG. 3 is added.

Referring to FIG. 4, first metal regions 100a and 100b which are ground and a second metal region 120 which is a bit line BL are disposed on a substrate region. A first active region 140 for the selection transistor M0 is formed on the first metal regions 100a and 100b which are ground and the second metal region 120 for the bit line. The polys of the gate to which the selection signal S / S is applied are disposed on the first active regions 100a and 100b, and the second metal region 120 and the first active region 140 are connected to the bit lines. ). Second active regions 160a and 160b for cell transistors MR1 to M32 are formed on the first metal regions 100a and 100b except for the first active region 140. In this case, the second active regions 160a and 160b are disposed in the same direction as the second metal region 120 which is the bit line, and gates of the cells connected to the word line are formed of polys. 160b) is arranged in an opposite direction to the bit line. The first metal regions 100a and 100b and the second active regions 160a and 160b are interconnected for the sources of the cell transistors MR1 to MR32 that are grounded to ground. The NOR structure described above is identical to the NAND structure in which polys are sequentially arranged on the second active region, except that the metal contacts for the sources are made.

Subsequently, for the common connection between the first node and the drains of the cell transistor, a conductive region 180 having a lower conductivity than the metal and a higher conductivity than the resistance is disposed, and then the first node and the drain are connected through the contact. In this case, a metal may be used for the connection between the first node N1 and the drain, but this causes a problem in that the total number of metals increases to increase the total chip area. Therefore, if the conductive film is used instead of the metal, the first node N1 and the drain can be interconnected, and the area can be reduced.

By arranging the cell array having the NOR structure as above, the active regions of the cells are arranged in series with the layout of the NAND structure, and instead, the conductive regions are disposed instead of the metal regions for connection with the nodes where the cells are connected in parallel. The number of metals can be reduced and the total chip area is reduced as the cells are arranged in series.

By arranging the cell array having the NOR structure as described above in the NAND structure, the active area of the cells is arranged in series, thereby reducing the layout area.

Claims (4)

A cell layout method of a semiconductor memory device comprising a transfer transistor transferring a voltage of a bit line in a memory cell array, and cells connected in parallel to the transfer transistor. The ground and the bit line are formed of metal regions, the active regions of the cells are arranged in the same direction as the bit region of the metal region, and poly is sequentially arranged for the gate of the cell transistor to which the word line is connected. Next, the cell layout method of the semiconductor memory device, characterized in that for connecting the cells connected in parallel with the transfer transistor in a conductive region. The method of claim 1, And the conductive region is arranged in the same direction as the bit region of the metal region. The method of claim 1, And the conductive region is less conductive than metal and more conductive than resistance. A cell layout method of a semiconductor memory device in which cells are connected in parallel to two transfer transistors and each transfer transistor in a memory cell array. The active regions in which the transfer transistors are formed are connected to one bit line in common, the other to ground, respectively, and two polys are formed on the active line for gates to which different transfer signals are applied. Arranged in the opposite direction to And electrically conducting, but resistive, a conductive region higher than a metal in the same direction as the bit line for connecting transistors connected in parallel with the transfer transistor.