KR19990005439A - Ferroelectric capacitor of semiconductor device and manufacturing method thereof - Google Patents
Ferroelectric capacitor of semiconductor device and manufacturing method thereof Download PDFInfo
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- KR19990005439A KR19990005439A KR1019970029636A KR19970029636A KR19990005439A KR 19990005439 A KR19990005439 A KR 19990005439A KR 1019970029636 A KR1019970029636 A KR 1019970029636A KR 19970029636 A KR19970029636 A KR 19970029636A KR 19990005439 A KR19990005439 A KR 19990005439A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000010409 thin film Substances 0.000 claims abstract description 75
- 238000000034 method Methods 0.000 claims description 15
- 239000010410 layer Substances 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 239000012790 adhesive layer Substances 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims 2
- 230000006641 stabilisation Effects 0.000 claims 1
- 238000011105 stabilization Methods 0.000 claims 1
- 238000000151 deposition Methods 0.000 description 5
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000002425 crystallisation Methods 0.000 description 3
- 230000008025 crystallization Effects 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 125000002524 organometallic group Chemical group 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910003446 platinum oxide Inorganic materials 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
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Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
본 발명은 반도체 제조 분야에 관한 것임.The present invention relates to the field of semiconductor manufacturing.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
본 발명은 반도체 장치의 SBT 강유전체 캐패시터의 누설전류 및 유전손실을 방지하는 캐패시터 및 그 제조방법을 제공하고자 함.An object of the present invention is to provide a capacitor and a manufacturing method thereof for preventing leakage current and dielectric loss of an SBT ferroelectric capacitor of a semiconductor device.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
본 발명은 SBT 강유전체 캐패시터의 유전체를 SBT 비정질 박막/SBT 다결정질 박막/SBT 비정질 박막의 적층 구조로 형성하여 누설 전류를 방지함.The present invention forms a dielectric of an SBT ferroelectric capacitor in a stacked structure of an SBT amorphous thin film, an SBT polycrystalline thin film, and an SBT amorphous thin film to prevent leakage current.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 장치 제조에 이용됨.Used to manufacture semiconductor devices.
Description
본 발명은 반도체 제조 분야에 관한 것으로, 특히 차세대 고집적 반도체 장치의 캐패시터로 개발이 진행되고 있는 SBT 강유전체 캐패시터 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor manufacturing, and more particularly, to an SBT ferroelectric capacitor, which is being developed as a capacitor for a next-generation highly integrated semiconductor device, and a manufacturing method thereof.
일반적으로, 반도체 장치의 고집적화에 따라 반도체 메모리 장치의 충분한 정전 용량을 제공하기 위하여 전하저장 전극의 표면적을 증가시키는 방향으로 많은 연구가 진행되어 왔다.In general, many studies have been conducted in the direction of increasing the surface area of the charge storage electrode in order to provide a sufficient capacitance of the semiconductor memory device in accordance with the high integration of the semiconductor device.
그러나, 1 기가 DRAM급 이상의 초고집적 반도체 장치에서는 전하저장 전극의 구조를 복잡하게 함으로써 표면적을 증가시키는 방법으로는 반도체 장치의 동작에 필요한 충분한 정전용량을 확보할 수 없다.However, in a highly integrated semiconductor device of 1 Gigabyte or more, a method of increasing the surface area by complicating the structure of the charge storage electrode cannot secure sufficient capacitance required for the operation of the semiconductor device.
따라서, 전하저장 전극의 구조의 변경에 의한 단순한 표면적 증가가 아닌 유전율이 큰 물질 예를 들어, BST, PZT, STO 등을 사용함으로써 초고집적 반도체 장치의 동작에 필요한 정전 용량을 확보할 수 있는 FeRAM 제조 관련 기술에 대한 연구가 진행되고 있다.Therefore, FeRAM fabrication that can secure the capacitance required for the operation of an ultra-high density semiconductor device by using a material having a high dielectric constant such as BST, PZT, STO, etc., rather than simply increasing the surface area due to the change of the structure of the charge storage electrode. Research on related technologies is ongoing.
첨부된 도면 도 1은 종래 기술에 따라 형성된 SrBi2Ta2O9(이하 SBT라 칭함) 강유전체 캐패시터의 단면을 도시한 것이다.1 is a cross-sectional view of a SrBi 2 Ta 2 O 9 (hereinafter referred to as SBT) ferroelectric capacitor formed according to the prior art.
도시된 바와 같은 구조의 종래의 SBT 강유전체 캐패시터의 제조는 소정의 하부층(10) 상부에 백금(Pt), 금속산화물 박막 등의 하부 전극(11)을 형성하고, 그 상부에 SBT 강유전체 박막(12)을 증착한 다음, 그 상부에 상부 전극(13)을 형성하는 공정을 거쳐 형성된다. 이때, SBT 강유전체 박막(12)은 고온 증착이나 열처리 등을 통해 다결정화된다. 이는 다결정질(polycrystalline) 결정 구조하에서 SBT 강유전체 박막은 높은 유전 상수와 잔류 분극 특성 등 강유전체로서의 성질을 제대로 나타낼 수 있기 때문이다.The manufacture of a conventional SBT ferroelectric capacitor having a structure as shown in the figure forms a lower electrode 11 such as platinum (Pt) or a metal oxide thin film on a predetermined lower layer 10, and the SBT ferroelectric thin film 12 thereon. After the deposition, it is formed through a process of forming the upper electrode 13 thereon. At this time, the SBT ferroelectric thin film 12 is polycrystalline through high temperature deposition or heat treatment. This is because an SBT ferroelectric thin film can exhibit ferroelectric properties such as high dielectric constant and residual polarization characteristics under a polycrystalline crystal structure.
그러나, 다결정질 박막은 결정립 계면(grain boundary)이 누설전류의 전도 경로로 이용되기 때문에, 누설전류 및 유전손실의 증가를 가져오게 되어 결국 반도체 장치의 특성을 열화시키는 문제점이 있다.However, the polycrystalline thin film has a problem that the grain boundary (grain boundary) is used as the conduction path of the leakage current, resulting in an increase in the leakage current and the dielectric loss, thereby deteriorating the characteristics of the semiconductor device.
또한, 이러한 누설 전류를 줄이기 위해서 다양한 전극을 사용하거나, 불순물을 첨가하는 등 다양한 방법이 시도되고 있으나 아직 만족할만한 결과를 가져오지 못하고 있다.In addition, various methods, such as using various electrodes or adding impurities, have been tried to reduce the leakage current, but have not yet produced satisfactory results.
본 발명은 강유전체를 사용한 캐패시터 중 SBT 강유전체 캐패시터의 누설전류 및 유전손실을 방지하는 캐패시터 및 그 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a capacitor and a method of manufacturing the same for preventing leakage current and dielectric loss of an SBT ferroelectric capacitor among capacitors using a ferroelectric.
도 1은 종래 기술에 따라 형성된 강유전체 캐패시터의 단면도.1 is a cross-sectional view of a ferroelectric capacitor formed in accordance with the prior art.
도 2는 본 발명의 일실시예에 따라 형성된 강유전체 캐패시터의 단면도.2 is a cross-sectional view of a ferroelectric capacitor formed in accordance with one embodiment of the present invention.
도 3은 본 발명의 일실시예에 따른 강유전체 캐패시터 제조 공정 흐름도.3 is a flow chart of a ferroelectric capacitor manufacturing process according to an embodiment of the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
20 : 하부층20: lower layer
21 : 하부 전극21: lower electrode
22,24 : SBT 비정질 박막22,24: SBT amorphous thin film
23 : SBT 다결정질 박막23: SBT polycrystalline thin film
25 : 상부 전극25: upper electrode
상기 목적을 달성하기 위하여 본 발명의 캐패시터는 소정의 하부층 상에 배치된 하부 전극; 상기 하부 전극 상부에 차례로 적층된 제1 SrxBiyTa2O9비정질 박막, SrxBiyTa2O9다결정질 박막 및 제2 SrxBiyTa2O9비정질 박막; 및 상기 제2 SrxBiyTa2O9비정질 박막 상부에 배치된 상부 전극을 포함하여 이루어진다.In order to achieve the above object, the capacitor of the present invention comprises: a lower electrode disposed on a predetermined lower layer; A first Sr x Bi y Ta 2 O 9 amorphous thin film, an Sr x Bi y Ta 2 O 9 polycrystalline thin film and a second Sr x Bi y Ta 2 O 9 amorphous thin film sequentially stacked on the lower electrode; And an upper electrode disposed on the second Sr x Bi y Ta 2 O 9 amorphous thin film.
또한, 본 발명의 캐패시터 제조방법은 반도체 기판상에 형성된 소정의 하부층 상에 하부 전극을 형성하는 제1 단계; 상기 하부 전극 상부에 제1 SrxBiyTa2O9비정질 박막을 형성하는 제2 단계; 상기 제1 SrxBiyTa2O9비정질 박막 상부에 SrxBiyTa2O9다결정질 박막을 형성하는 제3 단계; 상기 SrxBiyTa2O9다결정질 박막 상부에 제2 SrxBiyTa2O9비정질 박막을 형성하는 제4 단계; 상기 제2 SrxBiyTa2O9비정질 박막 상부에 상부 전극을 형성하는 제5 단계; 및 상기 상부 전극, 상기 제2 SrxBiyTa2O9비정질 박막, 상기 SrxBiyTa2O9다결정질 박막, 상기 제1 SrxBiyTa2O9비정질 박막 및 상기 하부 전극을 차례로 선택적 식각하는 제6 단계를 포함하여 이루어진다.In addition, the capacitor manufacturing method of the present invention comprises a first step of forming a lower electrode on a predetermined lower layer formed on a semiconductor substrate; Forming a first Sr x Bi y Ta 2 O 9 amorphous thin film on the lower electrode; Forming a Sr x Bi y Ta 2 O 9 polycrystalline thin film on the first Sr x Bi y Ta 2 O 9 amorphous thin film; A fourth step of forming a first 2 Sr x Bi y Ta 2 O 9 thin film amorphous to the crystalline thin film is the upper Sr x Bi y Ta 2 O 9 ; A fifth step of forming an upper electrode on the second Sr x Bi y Ta 2 O 9 amorphous thin film; And the upper electrode, the second Sr x Bi y Ta 2 O 9 amorphous thin film, the Sr x Bi y Ta 2 O 9 polycrystalline thin film, the first Sr x Bi y Ta 2 O 9 amorphous thin film and the lower electrode And a sixth step of selective etching in turn.
이하, 첨부된 도면 도 2 내지 도 3을 참조하여 본 발명의 일실시예를 상술한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명의 일실시예에 따라 형성된 강유전체 캐패시터의 단면을 도시한 것이다.Figure 2 shows a cross section of a ferroelectric capacitor formed in accordance with one embodiment of the present invention.
도시된 바와 같이 본 발명의 일실시예에 따른 강유전체 캐패시터는 실리콘 기판 상에 형성된 소정의 하부층(20)과, 그 상부에 차례로 적층된 하부 전극(21), SBT 비정질 박막(22), SBT 다결정질 박막(23), SBT 비정질 박막(24) 및 상부 전극(25)으로 구성된다.As shown, a ferroelectric capacitor according to an embodiment of the present invention includes a predetermined lower layer 20 formed on a silicon substrate, a lower electrode 21 sequentially stacked on the upper portion, an SBT amorphous thin film 22, and an SBT polycrystalline. The thin film 23, the SBT amorphous thin film 24, and the upper electrode 25 are comprised.
도 3에 상기 구조를 가지는 강유전체 캐패시터를 형성하기 위한 공정 흐름도를 도시하였다. 이하, 편의상 도 2의 도면 부호를 사용하여 설명한다.3 shows a process flow for forming a ferroelectric capacitor having the above structure. Hereinafter, for convenience, description will be made using reference numerals of FIG. 2.
우선, 실리콘 기판 상에 소정의 하부층(20)을 형성하고, 전체구조 상부에 하부 전극(21)을 형성한다. 여기서, 하부 전극(21)은 백금 또는 금속산화물 박막 등을 사용하여 형성하며, 하부 전극(21) 증착 전에 접착층(glue layer)을 증착하기도 하며, 그 상부에 불순물 확산 방지막을 더 얇게 증착하기도 한다.First, a predetermined lower layer 20 is formed on a silicon substrate, and a lower electrode 21 is formed on the entire structure. Here, the lower electrode 21 is formed using a platinum or metal oxide thin film, or the like, and deposits an adhesive layer (glue layer) before depositing the lower electrode 21, and may further deposit a thinner impurity diffusion prevention layer on the upper electrode.
다음으로, 하부 전극(21) 상부에 30㎚ 내지 50㎚ 두께의 얇은 SBT 비정질 박막(22)을 형성한다. SBT 비정질 박막(22)의 형성은 스퍼터링 등의 물리적 증착법이나 유기금속화학증착법 등의 화학적 증착법이 모두 가능하며, 상온 내지 300℃ 정도의 온도에서 형성하여 결정화가 이루어지지 않도록 한다.Next, a thin SBT amorphous thin film 22 having a thickness of 30 nm to 50 nm is formed on the lower electrode 21. The SBT amorphous thin film 22 may be formed by physical vapor deposition such as sputtering or chemical vapor deposition such as organometallic chemical vapor deposition, and may be formed at a temperature of about 300 ° C. to prevent crystallization.
SBT 비정질 박막(22)의 조성 비율은 SBT의 조성식 SrxBiyTa2O9에서 x=0.6∼1.0, y=1.0∼1.5의 비율로 하여 후속 열처리시에 발생하는 비스무스(Bi)의 휘발 및 반응으로 인한 손실에 대비하도록 한다.The composition ratio of the SBT amorphous thin film 22 is a ratio of x = 0.6 to 1.0 and y = 1.0 to 1.5 in the composition formula Sr x Bi y Ta 2 O 9 of SBT. Be prepared for losses due to reaction.
계속하여, SBT 비정질 박막(22) 상부에 SBT 다결정질 박막(23)을 50㎚ 내지 300㎚ 두께로 형성한다. SBT 다결정질 박막(23)은 플라즈마 화학기상증착(PECVD) 방식 등의 상대적으로 저온 공정이 가능한 방식을 사용하여, 하부의 SBT 비정질 박막(22)이 결정화 되지 않도록 한다. 또한, 결정화를 위한 열처리 공정에서도 단시간의 급속열처리 방식을 사용하여 하부의 SBT 비정질 박막(22)이 결정화되는 것을 방지한다.Subsequently, an SBT polycrystalline thin film 23 is formed on the SBT amorphous thin film 22 to have a thickness of 50 nm to 300 nm. The SBT polycrystalline thin film 23 uses a relatively low temperature process such as a plasma chemical vapor deposition (PECVD) method, so that the lower SBT amorphous thin film 22 is not crystallized. In addition, in the heat treatment process for crystallization, the rapid thermal treatment method for a short time is used to prevent the lower SBT amorphous thin film 22 from crystallization.
다음으로, SBT 다결정질 박막(23) 상부에 다시 SBT 비정질 박막(24)을 30㎚ 내지 50㎚ 두께로 증착한다. 그 증착 방법은 SBT 비정질 박막(22)의 증착 방식과 거의 동일하며, 추후 고온 공정에서의 비스무스 휘발에 대비하여 비스무스의 조성비를 SBT 비정질 박막(22)의 경우보다 조금 더 크게 즉 y=1.1∼1.7 정도로 하여 형성한다.Next, the SBT amorphous thin film 24 is deposited again on the SBT polycrystalline thin film 23 to a thickness of 30 nm to 50 nm. The deposition method is almost the same as the deposition method of the SBT amorphous thin film 22, and the bismuth composition ratio is slightly larger than that of the SBT amorphous thin film 22, i. It is formed to an extent.
끝으로, SBT 비정질 박막(24) 상부에 상부 전극(25)을 증착하고, 사진 및 식각 공정을 사용하여 패턴을 정의한 다음, 열처리를 실시하여 캐패시터를 안정화시킨다.Finally, the upper electrode 25 is deposited on the SBT amorphous thin film 24, the pattern is defined using a photolithography and an etching process, and then heat treated to stabilize the capacitor.
상기한 SBT 비정질 박막(22,24)은 SBT 다결정질 박막(23)에 비해 유전상수도 작고, 강유전체로서의 특성을 나타내지 못하지만, 박막 내부에 물질 전달 경로가 형성되지 않기 때문에 누설전류나 유전손실이 매우 작다. 누설전류는 전극을 통해서 소자 외부로 빠져 나가는 것이므로 SBT 다결정질 박막과 상하부 전극 사이에 비정질 박막을 형성시키면 누설전류의 이동 경로를 막을 수 있다. 이러한 효과를 얻기 위해서는 SBT 비정질 박막(22,24)의 두께가 그다지 두꺼울 필요가 없으므로, 유전상수의 감소 등 강유전체 특성에 열화를 가져오는 영향은 미미할 것으로 여져진다.The SBT amorphous thin films 22 and 24 have a smaller dielectric constant than the SBT polycrystalline thin film 23 and do not exhibit characteristics as ferroelectrics, but leakage currents and dielectric losses are very small since no material transfer path is formed in the thin film. . Since the leakage current flows out of the device through the electrode, forming an amorphous thin film between the SBT polycrystalline thin film and the upper and lower electrodes may prevent the leakage current from moving. In order to obtain such an effect, the thickness of the SBT amorphous thin films 22 and 24 does not need to be very thick. Therefore, the effect of deteriorating ferroelectric properties such as a decrease in the dielectric constant is considered to be minimal.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기한 바와 같이 본 발명은 SBT 다결정질 박막과 상하부 전극 사이에 SBT 비정질 박막을 형성함으로써 누설전류를 방지하며, 그에 따른 유전손실을 최소화함으로써 반도체 장치의 신뢰도 저하를 방지한다.As described above, the present invention prevents leakage current by forming an SBT amorphous thin film between the SBT polycrystalline thin film and the upper and lower electrodes, and prevents a decrease in reliability of the semiconductor device by minimizing the dielectric loss.
또한, 본 발명은 비교적 저온에서 모든 공정이 이루어지므로, 열적 응력에 의한 반도체 장치의 물성 열화를 방지할 수 있다.Further, in the present invention, since all processes are performed at a relatively low temperature, it is possible to prevent deterioration of physical properties of the semiconductor device due to thermal stress.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010045968A (en) * | 1999-11-09 | 2001-06-05 | 박종섭 | Method of manufacturing a capacitor in a semiconductor device |
| KR20050010650A (en) * | 2003-07-22 | 2005-01-28 | 주식회사 하이닉스반도체 | Method of manufacturing ferroelectric capacitor |
| KR100476030B1 (en) * | 2000-04-28 | 2005-03-10 | 샤프 가부시키가이샤 | Semiconductor device having ferroelectric thin film and fabricating method therefor |
| KR20220012794A (en) * | 2020-07-23 | 2022-02-04 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Feram with laminated ferroelectric film and method forming same |
| KR102382148B1 (en) * | 2020-10-30 | 2022-04-04 | 서울과학기술대학교 산학협력단 | Silicon based capacitor based on deposition thin film on a three dimensional structure and its manufacturing method |
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| JPH01315124A (en) * | 1988-06-15 | 1989-12-20 | Matsushita Electric Ind Co Ltd | Thin-film capacitor |
| JPH05347391A (en) * | 1992-06-16 | 1993-12-27 | Seiko Epson Corp | Ferroelectric storage device |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010045968A (en) * | 1999-11-09 | 2001-06-05 | 박종섭 | Method of manufacturing a capacitor in a semiconductor device |
| KR100476030B1 (en) * | 2000-04-28 | 2005-03-10 | 샤프 가부시키가이샤 | Semiconductor device having ferroelectric thin film and fabricating method therefor |
| US6936876B2 (en) | 2000-04-28 | 2005-08-30 | Sharp Kabushiki Kaisha | Semiconductor device having ferroelectric thin film and fabricating method therefor |
| KR20050010650A (en) * | 2003-07-22 | 2005-01-28 | 주식회사 하이닉스반도체 | Method of manufacturing ferroelectric capacitor |
| KR20220012794A (en) * | 2020-07-23 | 2022-02-04 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Feram with laminated ferroelectric film and method forming same |
| US11665909B2 (en) | 2020-07-23 | 2023-05-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | FeRAM with laminated ferroelectric film and method forming same |
| US11844226B2 (en) | 2020-07-23 | 2023-12-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | FeRAM with laminated ferroelectric film and method forming same |
| DE102020134634B4 (en) * | 2020-07-23 | 2025-06-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Ferroelectric random access memory (FERAM) with stacked ferroelectric film and method for forming the same |
| US12356631B2 (en) | 2020-07-23 | 2025-07-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | FeRAM with laminated ferroelectric film and method forming same |
| KR102382148B1 (en) * | 2020-10-30 | 2022-04-04 | 서울과학기술대학교 산학협력단 | Silicon based capacitor based on deposition thin film on a three dimensional structure and its manufacturing method |
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