KR19990004567A - Planarization method of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planarization method of a semiconductor device, and by selectively doping an interlayer insulating film of a cell region, and then planarizing by a CMP method, it is possible to effectively eliminate the step difference between the cell region and the peripheral circuit region. By preventing dishing, the thickness of the planarization film can be reduced, and the deposition time and polishing time can be reduced by minimizing the thickness of the planarization film. In addition, in the device isolation layer planarization process, by selectively doping the device isolation layer in the center of the wafer, the polishing rate of the doped device isolation layer is increased to increase the polishing uniformity, thereby improving device characteristics.

Description

Planarization method of semiconductor device

The present invention relates to a planarization method of a semiconductor device, and more particularly, to a planarization method of a semiconductor device capable of alleviating a step between a cell region and a peripheral circuit region by selectively doping activating ions in a cell region to increase polishing rate.

In general, in the manufacture of semiconductor devices, a process of forming metal wirings for electrically connecting various devices such as transistors, bit lines, capacitors, and the like is involved.

However, as the devices are formed by deposition, patterning, and etching of necessary materials, a step is generated between the cell area in which the devices are concentrated and the peripheral circuit area, and the step increases rapidly with the device density.

In order to alleviate such a step, until now, BPSG (Borophosphosiligate Glass) having excellent fluidity has been deposited and flowed, or an O ₃ -TEOS CVD oxide film has been used as a planarization film, but they only allow relatively narrow planarization. However, there is a problem in that planarization of a large area between the cell area and the peripheral circuit area is limited.

If the planarization layer is not formed as described above, the depth of focus is different for each part in the lithography process performed in the subsequent process, so that defocus occurs and as a result, it is impossible to form a uniform pattern on the semiconductor substrate. In order to improve the planarization characteristics, the BPSG was deposited and then flowed, and the step was removed by applying a conventional chemical mechanical polishing (CMP), but the step still remained.

Therefore, as a complementary method, studies have been made to apply a planarization method using a polishing stop layer such as a nitride film, but the polishing rate of the nitride film is about 1/5 to 1/10 lower than that of the BPSG film. The reverse step phenomenon, in which the cell region is polished more than the peripheral circuit region, may result in the loss of the interlayer insulation ability, which is the original purpose of the planarization film.

In addition, the nitride film tends to increase in nitriding particles after polishing, which requires the addition of various cleaning processes such as HF vapor cleaning in subsequent processes. As the nitride film remains on the interlayer insulating film in the peripheral circuit area after the planarization process, a process complexity occurs to add a process for removing it, and device characteristics deteriorate due to difficulty in the development / etching process. do.

In addition, the uniformity in the wafer is important in the device isolation planarization process. When the conventional CMP planarization process is performed, a center thick phenomenon occurs in which the wafer center device isolation film is less polished than the device isolation film at the wafer edge. Therefore, if the polishing continues to remove the wafer center device isolation layer, the device isolation layer at the edge of the wafer is excessively polished, and thus the device isolation capability is lost. If the nitride film is removed after the wafer center device isolation film is polished less, polysilicon remains on the side of the transistor to form a bridge, thereby deteriorating device characteristics, thereby lowering the yield and reliability of the semiconductor device. There is a problem.

Therefore, the present invention is to solve the above problems, an object of the present invention is to selectively remove the ion doping in the cell region to break the Si-O bond of the interlayer insulating film to increase the penetration rate by water molecules to increase the polishing rate by CMP The present invention provides a planarization method of a semiconductor device capable of improving the manufacturing yield and reliability of the semiconductor device by removing the step between the cell region and the peripheral circuit region by increasing.

1A-1D are cross-sectional views illustrating the planarization process steps of an interlayer insulating film in accordance with the method of the present invention.

2A through 2D are cross-sectional views illustrating a planarization process step of device isolation layers according to the method of the present invention.

Description of the main parts of the drawing

1: silicon substrate 2: field oxide film

3: cell area 4: peripheral circuit area

5 Step before flattening 6 Step after flattening

7, 8: photosensitive film 9: doping all over the wafer

10: interlayer insulating film after planarization 11: trench

12 pad nitride film 13 wafer edge die

14: wafer center die 15: device isolation film

16: device isolation film after general planarization process

17,18 photosensitive film 20 device isolation film after planarization

The method of the present invention for achieving the above object,

In the interlayer insulating film planarization method of a semiconductor element,

Forming a planarization insulating film on a semiconductor substrate having a step formed by a cell region where the device is dense and a peripheral circuit region having a low density;

Coating a photoresist with a predetermined thickness on the planarization insulating film;

Selectively removing the photoresist formed in the cell region;

Doping a dopant atom that can break the Si—O bond of the interlayer insulating film to the entire surface of the wafer,

It is characterized by consisting of a step of planarization by the CMP method.

In addition, the method of the present invention for achieving the above object,

In the device isolation film planarization method of a semiconductor device,

Forming a device isolation film on the semiconductor substrate,

Applying a photoresist on the device isolation layer;

Selectively removing the photoresist formed at the center of the wafer;

Doping a dopant atom that can break the Si—O bond of the device isolation layer over the entire wafer;

Removing photoresist in the peripheral circuit area;

It is characterized by consisting of a step of planarization by the CMP method. Hereinafter, a planarization method of a semiconductor device according to the present invention will be described with reference to the accompanying drawings.

1B-1D are cross-sectional views illustrating interlayer insulating film planarization process steps according to the method of the present invention;

1A is a cross-sectional view illustrating a state in which a cell region having a high pattern density and a peripheral circuit region having a relatively low pattern density are planarized according to a conventional planarization method.

First, referring to FIG. 1A, in the cell region 3 and the peripheral circuit region 4 before polishing, there is a step to the degree (5) shown. At this time, if the flattening process is performed to remove the step (5), the peripheral circuit area 4 is also polished at the same time by the elastic deformation of the flattening pad while the high cell step 3 is polished. Step) will continue to exist. In order to remove the above step (6), the planarization target film must be deposited thicker and the polishing amount must be increased.

However, there is a disadvantage in that the overall polishing uniformity worsens as the polishing amount increases, so that a planarization target film having a predetermined thickness or more cannot be deposited.

FIG. 1B is a view illustrating a method of planarizing an interlayer insulating film in a semiconductor device according to the method of the present invention to solve the above problems and to improve the degree of planarization.

Referring to FIG. 1B, first, PBSG is deposited in the cell region 3 and the peripheral circuit region 4 with an interlayer insulating film at about 8.000-30,000 kPa, and flows at 200-1,000 ° C.

A photoresist is applied over the interlayer insulating film and the photoresist in the cell region 3 is selectively developed / etched so that the photoresist remains only in the peripheral circuit region 4.

Next, dopants are implanted under predetermined conditions, and dopant atoms such as hydrogen, antimony, arsenic, phosphorus, boron, and fluorine may break the Si—O bond of the interlayer insulating film at 500-1300 ° C., 1E10-1.0E20 dose, 5 The dopant amount and diffusion rate in the cell region 3 are controlled by doping with energy of -50 KeV (see Fig. 1c).

Referring to FIG. 1D, the photoresist in the peripheral circuit region 4 is removed and the doped interlayer insulating film is planarized by the CMP method.

2B to 2D are diagrams illustrating a method of preventing a center Seek phenomenon occurring after a general planarization process when the planarization is performed by doping the device isolation layer of the wafer center die by adjusting the polishing rate in the device isolation planarization process.

2A is a view showing the planarization by the conventional device isolation film planarization chamber.

First, referring to FIG. 2A, the thickness of the device isolation film at the back of the wafer center is thicker than that of the edge die, as shown in FIG. 16 after polishing.

Figure 2b shows a device isolation planarization method according to the method of the present invention to solve the above problems and improve the uniformity.

Referring to FIG. 2B, first, for example, O ₃ -TEOS is deposited on the entire surface of about 4,000 to 20,000 μs and annealed to 500-1200 ° C. as an isolation layer.

A photoresist is applied on the device isolation layer and the photoresist at the center of the wafer is selectively developed / etched to form photoresist only at the edge of the wafer.

Referring to FIG. 2C, the photoresist at the center of the dopant reactor is doped with an isolation layer, the photoresist is removed, and planarization is performed by the CMP method.

At this time, the slurry used is a slurry for the oxide film is PH 10-12, using a suspension of silica particles and DI water of 100-300nm size.

2D is a view showing the planarized state.

As described above, by selectively doping the interlayer insulating film of the cell region in accordance with the method of the present invention, by the planarization by the CMP method it is possible to effectively remove the step difference between the cell region and the peripheral circuit region, and also characterized by The thickness of the planarization target film may be reduced while preventing dishing. This method also has the effect of reducing the deposition time and polishing time by minimizing the thickness of the planarization target film.

In addition, in the device isolation planarization process according to the method of the present invention, by selectively doping the device isolation layer in the center of the wafer, the polishing rate of the doped device isolation layer may be faster, thereby increasing device uniformity, thereby improving device characteristics.

Claims (18)

In the method of planarizing the interlayer insulating film of a semiconductor device, Forming a planarization insulating film on a semiconductor substrate having a step formed by a cell region where the device is dense and a peripheral circuit region having a low density; Coating a photoresist with a predetermined thickness on the planarization insulating film; Selectively removing the photoresist formed in the cell region; Doping a dopant atom that can break the Si—O bond of the interlayer insulating film to the entire surface of the wafer, Removing residues of the photoresist; The planarization method of the semiconductor element characterized by including the process of planarization by CMP method. The method of claim 1, wherein the interlayer insulating film is formed of any one of BPSG, O ₃ -TEOS, and HDP-CVD oxide film. The planarization method of a semiconductor device according to claim 1, wherein the thickness of said interlayer insulating film is 4,000-30,000 kPa. The method of claim 1, wherein after the interlayer insulating film is formed, heat treatment is performed at 200-1200 ° C. The method of claim 1, wherein any one of antimony, arsenic, phosphorus, boron, gold, nitrogen, hydrogen, zirconium, and germanium is used as the dopant atom. The planarization method of a semiconductor device according to claim 1, wherein the doping and heat treatment are performed at a temperature of 500-1300 ° C. The method of claim 1, wherein the doping concentration is 1.0E10-1.0E20 dose. The method of claim 1, wherein the doping energy is 5-50 KeV. The planarization method of claim 1, wherein the planarization slurry has a pH of 10-11 and a suspension containing 100-150 nm silica particles and DI water as an abrasive. In the device isolation film planarization method of a semiconductor device, Forming a device isolation film on the semiconductor substrate, Applying a photoresist on the device isolation layer; Selectively removing the photoresist formed at the center of the wafer; Doping a dopant atom that can break the Si—O bond of the device isolation layer over the entire wafer; Removing photoresist in the peripheral circuit area; The planarization method of the semiconductor element characterized by including the process of planarization by CMP method. The method of claim 10, wherein the interlayer insulating film is formed of one of BPSG, O ₃ -TEOS, and HDP-CVD oxide film. The planarization method of a semiconductor device according to claim 10, wherein the thickness of said interlayer insulating film is 4,000-30,000 kPa. The planarization method of a semiconductor device according to claim 10, wherein after the interlayer insulating film is formed, heat treatment is performed at 200-1200 ° C. The method of claim 10, wherein any one of antimony, arsenic, phosphorus, boron, gold, nitrogen, hydrogen, zirconium, and germanium is used as the dopant atom. The planarization method of a semiconductor device according to claim 10, wherein the doping treatment is performed at a temperature of 500-1300 ° C. The method of claim 10, wherein the doping concentration is 1.0E10-1.0E20 dose. 11. The method of claim 10, wherein the doping energy is 5-50 KeV. The planarization method of claim 10, wherein the planarization slurry has a pH of 10-11 and a suspension containing 100-150 nm silica particles and DI water as an abrasive.