KR19990004561A - Device Separation Method of Semiconductor Device - Google Patents
Device Separation Method of Semiconductor Device Download PDFInfo
- Publication number
- KR19990004561A KR19990004561A KR1019970028688A KR19970028688A KR19990004561A KR 19990004561 A KR19990004561 A KR 19990004561A KR 1019970028688 A KR1019970028688 A KR 1019970028688A KR 19970028688 A KR19970028688 A KR 19970028688A KR 19990004561 A KR19990004561 A KR 19990004561A
- Authority
- KR
- South Korea
- Prior art keywords
- oxide film
- hdp
- exposed
- cvd
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Plasma & Fusion (AREA)
- Element Separation (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
본 발명은 반도체 소자의 소자분리막 제조방법에 관한 것으로, 반도체 기판 하부에 다양한 폭과 간격을 갖는 트랜치를 형성한 다음, 상기 트랜치를 완전히 매립하는 HDP-산화막을 형성하고 그 상부에 CVD-산화막을 형성한 후, 두차례의 CMP 공정을 실시하되 일차로 단차가 높은 부위의 CVD-산화막을 연마하고, HF계 용액을 사용하여 노출된 HDP-산화막을 선택적으로 식각하여 일정 부분을 제거한 다음, 이차로 잔류 CVD-산화막과 HDP-산화막을 연마하여 소자분리막을 형성함으로써 반도체 소자의 공정 수율 및 신뢰성을 향상시키는 기술에 관한 것이다.The present invention relates to a method for manufacturing a device isolation film of a semiconductor device, and to form a trench having various widths and gaps in the lower portion of the semiconductor substrate, and then to form an HDP-oxide film to completely fill the trench and to form a CVD oxide film thereon Afterwards, two CMP processes are carried out, but the first step is to polish the CVD-oxide film having a high step and selectively etch the exposed HDP-oxide film using an HF-based solution to remove a portion, and then remain in the secondary. The present invention relates to a technique for improving the process yield and the reliability of a semiconductor device by polishing an CVD oxide film and an HDP oxide film to form a device isolation film.
Description
본 발명은 반도체 소자의 소자분리막 제조방법에 관한 것으로, 특히 두차례의 CMP공정을 실시하여 균일한 두께를 갖는 소자분리막을 형성함으로써 반도체 소자의 공정수율 및 신뢰성을 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a device isolation film of a semiconductor device, and more particularly, to a technology for improving process yield and reliability of a semiconductor device by forming a device isolation film having a uniform thickness by performing two CMP processes.
일반적으로, 반도체 소잔느 트랜지스터나 캐패시터와 같은 소자들이 형성되는 활성영역과 소자들이 동작이 서로 방해되지 않도록 활성영역들을 분리하는 소자 분리영역으로 구성되어 있다.In general, an active region in which elements such as a semiconductor transistor and a capacitor are formed, and an element isolation region separating the active regions so that the operation does not interfere with each other.
반도체 소자의 고집적화 추세에 따라 소자분리영역을 감소시키기 위하여 종래의 로코스(LOCOS)방법(버즈빅의 발생을 피할 수 없어서 활성영역의 폭이 작아지는 단점이 있다.) 보다는 실리콘 기판을 식각하여 트랜치를 만들고 산화막을 증착한 후 증착된 산화막을 CMP(chemical mechanical polishing 이하, CMP)하여 상기 산화막을 평탄화하여 소자분리 산화막을 제조하는 방법에 대한 연구가 많이 진행되고 있다.In order to reduce the isolation region according to the trend of higher integration of semiconductor devices, a trench is formed by etching a silicon substrate rather than the conventional LOCOS method (the disadvantage of the occurrence of a buzz big is reduced.) After the deposition of the oxide film and the deposition of the oxide film CMP (chemical mechanical polishing, CMP) by the planarization of the oxide film has been studied a lot of methods for producing a device isolation oxide film.
특히, 상기 트랜치를 메우기 위한 산화막으로 좁은 폭의 트랜치에 대한 틈새 메움(gap fill) 특성이 우수한 고밀도 플라즈마 화학기상증착 산화막(high density plasma chemical vapor deposition oxide 이하, HDP)의 사용에 대한 연구가 많이 진행되고 있다.In particular, many studies have been conducted on the use of high density plasma chemical vapor deposition oxide (HDP), which has excellent gap fill characteristics for narrow trenches as an oxide film to fill the trench. It is becoming.
도 1a 내지 1b 는 종래 기술에 따른 반도체 소자의 소자분리막 공정단면도이다.1A to 1B are cross-sectional views of a device isolation film of a semiconductor device according to the related art.
먼저, 반도체 기판(1) 상부에 패드산화막과 질화막을 순차적으로 형성한 다음, 소자분리용 마스크로 질화막(5)패턴과 패드산화막(3)을 순차적으로 형성한다.First, the pad oxide film and the nitride film are sequentially formed on the semiconductor substrate 1, and then the nitride film 5 pattern and the pad oxide film 3 are sequentially formed as a device isolation mask.
다음, 상기 패턴(5,3)들을 식각장벽으로 반도체 기판(1)의 하부에 트랜치(7)을 형성한다.Next, the trenches 7 are formed in the lower portion of the semiconductor substrate 1 by etching the patterns 5 and 3.
그 다음, 상기 트랜치(7)을 매립하는 일정 두께의 HDP-산화막(9)을 형성한다.(도 1a 참조)Next, an HDP oxide film 9 having a predetermined thickness filling the trench 7 is formed (see FIG. 1A).
다음, CMP공정으로 상기 질화막(5)이 노출될때 까지 연마하여 평탄화한다.(도 1b 참조)Next, by the CMP process, the nitride film 5 is polished and planarized until the nitride film 5 is exposed (see FIG. 1B).
상기와 같은 종래 기술에 따르면, 상기 HDP-산화막 형성시 스퍼터링(sputtering) 공정이 동시에 진행되므로 HDP-산화막을 증착한 후의 형상은 질화막패턴의 면적이 증가할수록 증착되는 두께가 증가하게 된다.According to the prior art as described above, since the sputtering process is performed at the time of forming the HDP-oxide film, the shape after the deposition of the HDP-oxide film is increased as the area of the nitride film pattern is increased.
따라서, 셀영역과 주변회로 영역에 증착된 HDP-산화막의 두께 및 형상에 있어서 큰 차이를 보이게 된다.Therefore, there is a big difference in the thickness and shape of the HDP oxide film deposited in the cell region and the peripheral circuit region.
또한, 셀영역과 주변회로 영역에 증착된 HDP-산화막의 두께가 다름으로 인해 CMP 연마시 종말점을 결정하기가 힘들어진다.In addition, it is difficult to determine the end point during CMP polishing due to the difference in the thickness of the HDP oxide film deposited in the cell region and the peripheral circuit region.
즉, 셀영역의 질화막패턴이 드러날때 까지 CMP연마를 하여도 질화막 폭이 넓은 주면회로 영역은 셀영역 보다 초기 두께가 두꺼움으로 HDP-산화막이 일정부분 잔류하게 된다.That is, even if CMP polishing is performed until the nitride pattern of the cell region is revealed, the main circuit circuit region having a wider nitride layer has a thicker initial thickness than the cell region, so that the HDP-oxide film remains in a certain portion.
이와 같이 남아있는 HDP-산화막은 후속 공정인 고온 인산용액에 의한 질화막 제거공정시 질화막의 완전한 제거가 불가능함으로 액티브영역의 소자형성이 어렵게 된다.As such, the remaining HDP-oxide film cannot be completely removed from the nitride film removal process by the high temperature phosphoric acid solution, which is a subsequent process, thus making it difficult to form an active device.
또한, 상기 주변영역에 남아있는 HDP-산화막을 제거하기 위하여 연마시간을 증가시키면 되면 셀영역의 질화막패턴도 연마되어 활성영역으로 작용하는 하부의 실리콘기판 까지 연마될뿐만 아니라, 소자분리 산화막까지도 연마되어 산화막의 두께를 감소시키게 됨으로써 소자의 전기적 특성이 저하되는 문제점이 있다.In addition, if the polishing time is increased to remove the HDP-oxide film remaining in the peripheral region, the nitride layer pattern of the cell region is also polished to not only polish the lower silicon substrate serving as the active region, but also the device isolation oxide film. By reducing the thickness of the oxide film there is a problem that the electrical characteristics of the device is lowered.
이에, 본 발명은 상기한 문제점을 해결하기 위한 것으로 반도체 기판의 하부에 형성된 트랜치를 매립하는 HDP-산화막 상부에 CVD-산화막을 형성한 다음, CMP 공정으로 단차가 높은 부위를 우선적으로 연마하여 제거한 후, HF계 용액을 사용하여 상기 HDP-산화막을 일부분 제거한 다음, 다시 CMP공정으로 연마하여 평탄화된 소자분리막을 형성함으로써 소자의 공정 수율 및 신뢰성을 향상시키는 반도체 소자의 소자분리막 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention is to solve the above-mentioned problems, and after forming a CVD oxide film on the HDP oxide oxide buried trench formed in the lower portion of the semiconductor substrate, and then by removing the first step of polishing the high step by CMP process To provide a device isolation film manufacturing method of a semiconductor device to improve the process yield and reliability of the device by removing a portion of the HDP-oxide using HF-based solution, and then polished by CMP process to form a planarized device isolation film. There is this.
도 1a 내지 도 1b 는 종래기술에 따른 반도체 소자의 소자분리막 공정단면도1A to 1B are cross-sectional views of a device isolation film process of a semiconductor device according to the related art.
도 2a 내지 도 2c 는 본 발명에 따른 반도체 소자의 소자분리막 제조공정도2a to 2c is a manufacturing process of the device isolation film of the semiconductor device according to the present invention
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
1, 20 : 반도체 기판 3, 22 : 패드산화막1, 20: semiconductor substrate 3, 22: pad oxide film
5, 24 : 질화막 7, 26 : 트랜치5, 24: nitride film 7, 26: trench
9, 28 : HDP-산화막 30 : CVD-산화막9, 28: HDP oxide film 30: CVD oxide film
상기 목적을 달성하기 위해 본 발명에 따른 반도체 소자의 소자분리막 제조 방법은In order to achieve the above object, a device isolation film manufacturing method of a semiconductor device according to the present invention
반도체 기판 상부에 패드산화막과 질화막을 순차적으로 형성하는 공정과,Sequentially forming a pad oxide film and a nitride film on the semiconductor substrate;
소자분리용 마스크로 반도체 기판이 노출될때 까지 식각하여 질화막패턴과 패드산화막패턴을 형성하는 공정과,Forming a nitride film pattern and a pad oxide film pattern by etching until the semiconductor substrate is exposed as a device isolation mask;
상기 패턴들을 식각장벽으로 반도체 기판의 하부가 노출되는 트랜치를 형성하는 공정과,Forming a trench in which the lower portion of the semiconductor substrate is exposed by etching the patterns;
상기 트랜치 측벽을 열산화시키는 공정과,Thermally oxidizing the trench sidewalls;
상기 트랜치를 매립하는 일정 두께의 HDP-산화막을 형성하는 공정과,Forming an HDP oxide film having a predetermined thickness to fill the trench;
상기 HDP-산화막 상부에 CVD-산화막을 형성하는 공정과,Forming a CVD oxide film on the HDP oxide film;
CMP공정으로 상기 CVD-산화막의 일적부분을 선택적으로 연마하여 상기 HDP-산화막을 노출시키는 공정과,Selectively polishing a portion of the CVD oxide film by a CMP process to expose the HDP oxide film;
상기 노출된 HDP-산화막을 HF계 용액을 이용하여 일정부분을 제거하는 공정과,Removing the exposed portion of the HDP-oxide using HF-based solution;
재차 CMP공정으로 상기 CVD-산화막과 HDP-산화막을 연마하여 평탄화하는 공정을 한다.The CMP process is followed by polishing and planarizing the CVD oxide film and the HDP oxide film.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 소자분리막 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a device isolation film manufacturing method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2b 는 본 발명에 따른 반도체 소자의 소자분리막 제조공정도이다.2A through 2B are diagrams illustrating a process of fabricating an isolation layer of a semiconductor device according to the present invention.
먼저, 반도체 기판(20) 상부에 패드산화막과 질화막을 순차적으로 형성한다.First, a pad oxide film and a nitride film are sequentially formed on the semiconductor substrate 20.
이때, 상기 패드산화막은 100 ~ 500Å 두께로 형성하고, 상기 질화막은 500 ~ 3000Å 두께로 형성한다.In this case, the pad oxide film is formed to a thickness of 100 ~ 500Å, the nitride film is formed to a thickness of 500 ~ 3000Å.
다음, 소자분리용 마스크로 상기 반도체 기판(20)이 노출될때 까지 식각하여 질화막(24)패턴과 패드산화막(22)패턴을 형성한다.Subsequently, the semiconductor substrate 20 is etched using the device isolation mask to expose the nitride film 24 pattern and the pad oxide film 22 pattern.
그 다음, 상기 패턴(24,22)들을 식각장벽으로 이용하여 반도체 기판(20) 하부에 일정 깊이의 트랜치(26)를 형성한다.Next, the trenches 26 having a predetermined depth are formed under the semiconductor substrate 20 by using the patterns 24 and 22 as etching barriers.
이때, 상기 트랜치(26)는 1500 ~ 6000Å 두께의 깊이로 형성한다.At this time, the trench 26 is formed to a depth of 1500 ~ 6000Å thickness.
다음, 열산화 공정을 실시하여 상기 트랜치(26) 측벽에 100 ~ 500Å 두께의 열산화막(도시 않됨)을 형성한다.Next, a thermal oxidation process is performed to form a thermal oxidation film (not shown) having a thickness of 100 to 500 Å on the sidewalls of the trench 26.
그 다음, 상기 트랜치(26)를 매립하는 일정 두께의 HDP-산화막(28)을 형성한다.Next, an HDP-oxide film 28 having a predetermined thickness filling the trench 26 is formed.
이때, 상기 HDP-산화막(28)을 2000 ~ 20000Å 두께로 형성한다.At this time, the HDP-oxide film 28 is formed to a thickness of 2000 ~ 20000Å.
다음, 상기 HDP-산화막(28) 상부에 500 ~ 3000Å 두께의 CVD-산화막(30)을 형성한다.Next, the CVD oxide film 30 having a thickness of 500 to 3000 Å is formed on the HDP oxide film 28.
그다음, CMP공정으로 상기 CVD-산화막(30)의 일정부분을 선택적으로 연마하여 상기 HDP-산화막(28)을 노출시킨다.Then, a portion of the CVD oxide film 30 is selectively polished by a CMP process to expose the HDP oxide film 28.
이때, 상기 CVD-산화막(30)은 도프않된 CVD산화막 또는 인이 인-스튜 도프된 도프된 CVD산화막이거나 다결정실리콘 또는 비정질실리콘 중의 하나를 선택하여 증착한다.At this time, the CVD oxide film 30 is a dope CVD oxide film or a doped CVD oxide film phosphorus-in-doped, or select one of polycrystalline silicon or amorphous silicon to deposit.
여기서, 상기 연마제의 함량을 조절하기 위해 슬러리와 순수를 1 ~ 50배로 희석하며, 연마 압력은 1 ~ 6PSI 인 범위에서 형성한다.Here, in order to adjust the content of the abrasive, the slurry and the pure water are diluted by 1 to 50 times, and the polishing pressure is formed in the range of 1 to 6PSI.
이때, 연마 압력이 높을 수록 연마패드의 변형에 의하여 단차가 낮은 부분에 증착된 상기 CVD-산화막(30)도 연마되기 때문에 이를 방지하기 위해서다.(도 2a 참조)At this time, as the polishing pressure is higher, the CVD oxide film 30 deposited on the lower step portion is also polished due to the deformation of the polishing pad, so as to prevent this (see FIG. 2A).
다음, 상기 노출된 HDP-산화막(28)을 HF계 용액을 이용한 습식 또는 건식 공정으로 일정부분을 제거한다.Next, a portion of the exposed HDP oxide layer 28 is removed by a wet or dry process using an HF-based solution.
이 때, 상기 HDP-산화막(28)의 건식식각은 HF와 H2O의 혼합가스를 사용하며, 상기 HDP-산화막(28)의 습식용액은 HF와 H2O 또는 BOE와 H2O의 혼합액를 사용한다.At this time, the dry etching of the HDP-oxide film 28 uses a mixed gas of HF and H 2 O, the wet solution of the HDP-oxide film 28 is a mixture of HF and H 2 O or BOE and H 2 O use.
여기서, 상기 HDP-산화막(28)의 습식용액은 HF와 H2O의 혼합액비가 1 : 10 ~ 1 : 100 이며, BOE와 H2O의 혼합액비가 1 : 10 ~ 1 : 100 이다.(도 2b 참조)Here, the wet solution of the HDP-oxide film 28 has a mixed liquid ratio of HF and H 2 O of 1: 10 to 1: 100, and a mixed liquid ratio of BOE and H 2 O of 1: 10 to 1: 100. (FIG. 2B). Reference)
다음, 재차 CMP공정으로 상기 CVD-산화막(30)과 HDP-산화막(28)을 연마하여 평탄화한다.Next, the CVD oxide film 30 and the HDP oxide film 28 are polished and planarized again by a CMP process.
이 때, 상기 CMP공정시 연마용 슬러리는 SiO2, Al2O3, TiO2또는 CeO2이거나 KOH 또는 NH4OH 중의 하나를 선택하여 사용하며, 연마제 함량은 무게분율로 1 ~ 20 % 이다.At this time, the polishing slurry in the CMP process is SiO 2 , Al 2 O 3 , TiO 2 or CeO 2 or one selected from KOH or NH 4 OH, the abrasive content is 1 to 20% by weight fraction.
여기서, CMP공정을 거치게 되면 넓은 활성영역 즉 넓은 질화막(24) 상부의 중심부에 연마되지 않은 산화막이 잔류하는 것을 근본적으로 방지할 수 있다.(도 2c 참조)Here, through the CMP process, it is possible to fundamentally prevent the unpolishing oxide film from remaining in the center of the wide active region, that is, the upper part of the wide nitride film 24 (see FIG. 2C).
상기한 바와같이 본 발명에 따르면, 두차례의 CMP공정을 실시하여 소자분리막을 형성함으로써 액티브영역의 폭이 넓을수록 증착되는 두께가 증가하는 현상에 관계없이 CMP공정을 적용하여 균일한 두께로 평탄화할 수 있어 소자의 공정수율 및 신뢰성을 향상시키는 이점이 있다.As described above, according to the present invention, two CMP processes are performed to form a device isolation film, thereby flattening to a uniform thickness by applying a CMP process regardless of a phenomenon in which the thickness of the active region increases as the width of the active region increases. It can be advantageous to improve the process yield and reliability of the device.
Claims (16)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970028688A KR100444311B1 (en) | 1997-06-28 | 1997-06-28 | Device Separation Method of Semiconductor Device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970028688A KR100444311B1 (en) | 1997-06-28 | 1997-06-28 | Device Separation Method of Semiconductor Device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990004561A true KR19990004561A (en) | 1999-01-15 |
| KR100444311B1 KR100444311B1 (en) | 2004-11-08 |
Family
ID=37362220
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970028688A Expired - Fee Related KR100444311B1 (en) | 1997-06-28 | 1997-06-28 | Device Separation Method of Semiconductor Device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100444311B1 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100453908B1 (en) * | 2002-07-23 | 2004-10-20 | 아남반도체 주식회사 | Chemical solution for etching oxide of semiconductor device |
| KR100478484B1 (en) * | 2002-10-09 | 2005-03-28 | 동부아남반도체 주식회사 | Formation method of trench in semiconductor device |
| KR100821488B1 (en) * | 2006-12-28 | 2008-04-14 | 동부일렉트로닉스 주식회사 | Method of forming isolation film for semiconductor device |
| KR100857575B1 (en) * | 2002-06-21 | 2008-09-09 | 매그나칩 반도체 유한회사 | Device Separation Method of Semiconductor Device |
| CN117766511A (en) * | 2024-02-20 | 2024-03-26 | 芯联集成电路制造股份有限公司 | Fuse structure and preparation method thereof, semiconductor integrated circuit and preparation method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5913342A (en) * | 1982-07-15 | 1984-01-24 | Toshiba Corp | Manufacture of semiconductor device |
| US4962064A (en) * | 1988-05-12 | 1990-10-09 | Advanced Micro Devices, Inc. | Method of planarization of topologies in integrated circuit structures |
| JP2919880B2 (en) * | 1989-11-17 | 1999-07-19 | 富士通株式会社 | Method for manufacturing semiconductor device |
-
1997
- 1997-06-28 KR KR1019970028688A patent/KR100444311B1/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100857575B1 (en) * | 2002-06-21 | 2008-09-09 | 매그나칩 반도체 유한회사 | Device Separation Method of Semiconductor Device |
| KR100453908B1 (en) * | 2002-07-23 | 2004-10-20 | 아남반도체 주식회사 | Chemical solution for etching oxide of semiconductor device |
| KR100478484B1 (en) * | 2002-10-09 | 2005-03-28 | 동부아남반도체 주식회사 | Formation method of trench in semiconductor device |
| KR100821488B1 (en) * | 2006-12-28 | 2008-04-14 | 동부일렉트로닉스 주식회사 | Method of forming isolation film for semiconductor device |
| CN117766511A (en) * | 2024-02-20 | 2024-03-26 | 芯联集成电路制造股份有限公司 | Fuse structure and preparation method thereof, semiconductor integrated circuit and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100444311B1 (en) | 2004-11-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100428805B1 (en) | Structure of Trench Isolation and Method of Forming The Same | |
| KR100543455B1 (en) | Device Separating Method of Semiconductor Device | |
| US6080628A (en) | Method of forming shallow trench isolation for integrated circuit applications | |
| US6171929B1 (en) | Shallow trench isolator via non-critical chemical mechanical polishing | |
| EP0954022B1 (en) | Method for providing shallow trench isolation of transistors | |
| KR19980085035A (en) | Trench Forming Method with Rounded Profile and Device Separation Method of Semiconductor Device Using the Same | |
| KR0172792B1 (en) | Method of manufacturing isolation for semiconductor device | |
| US20010029083A1 (en) | Method for forming shallow trench isolation structure | |
| KR100444311B1 (en) | Device Separation Method of Semiconductor Device | |
| JP2000036533A (en) | Manufacture of semiconductor device | |
| KR100315034B1 (en) | Manufacturing method of semiconductor device | |
| KR100359858B1 (en) | Method of forming device isolation film in semiconductor device | |
| KR100305145B1 (en) | Method of forming shallow trench isolation layer in semiconductor device | |
| KR100451499B1 (en) | Device Separating Method of Semiconductor Device | |
| KR20080084293A (en) | Manufacturing method of semiconductor device | |
| KR20010009416A (en) | Trench-type isolation method using a thin nitride film | |
| KR19980060641A (en) | Device isolation insulating film manufacturing method of semiconductor device | |
| KR100557533B1 (en) | Device Separating Method of Semiconductor Device | |
| KR100954418B1 (en) | Device Separating Method of Semiconductor Device | |
| US6844237B1 (en) | Method for improving dielectric polishing | |
| KR100561974B1 (en) | Manufacturing method of semiconductor device | |
| KR19990055199A (en) | Method of forming device isolation film in semiconductor device | |
| CN115841984A (en) | Method for forming shallow trench isolation structure | |
| KR100242387B1 (en) | Method of forming an element isolation film in a semiconductor device | |
| KR20000060946A (en) | Manufacturing Method of Semiconductor Device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19970628 |
|
| PG1501 | Laying open of application | ||
| A201 | Request for examination | ||
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 20020402 Comment text: Request for Examination of Application Patent event code: PA02011R01I Patent event date: 19970628 Comment text: Patent Application |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20040225 Patent event code: PE09021S01D |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 20040728 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 20040804 Patent event code: PR07011E01D |
|
| PR1002 | Payment of registration fee |
Payment date: 20040805 End annual number: 3 Start annual number: 1 |
|
| PG1601 | Publication of registration | ||
| PR1001 | Payment of annual fee |
Payment date: 20070720 Start annual number: 4 End annual number: 4 |
|
| PR1001 | Payment of annual fee |
Payment date: 20080728 Start annual number: 5 End annual number: 5 |
|
| PR1001 | Payment of annual fee |
Payment date: 20090727 Start annual number: 6 End annual number: 6 |
|
| FPAY | Annual fee payment |
Payment date: 20100726 Year of fee payment: 7 |
|
| PR1001 | Payment of annual fee |
Payment date: 20100726 Start annual number: 7 End annual number: 7 |
|
| LAPS | Lapse due to unpaid annual fee | ||
| PC1903 | Unpaid annual fee |
Termination category: Default of registration fee Termination date: 20120809 |