KR19980082928A - Semiconductor device having pulse generating circuit for mode selection - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generator circuit, and more particularly, to a semiconductor device pulse generator circuit, comprising: generating a pulse signal by applying a power supply voltage from an external source, and selecting a mode according to the pulse signal; Voltage dividing means for receiving a power supply voltage and a ground voltage from the outside, and distributing the same to output a voltage division signal; Precharge means for precharging the voltage division signal to a positive voltage and a negative voltage to a voltage level of a power supply terminal and a ground terminal; First inverting means for receiving a power supply voltage and the voltage division signal from an outside, inverting the voltage division signal, and outputting a first inversion signal; Second inverting means receiving the first inverted signal and inverting the first inverted signal to output a second inverted signal; Delay means for delaying the second inverted signal and outputting a delayed signal; And output means for receiving the delay signal and the second inversion signal and outputting a pulse signal. Such a circuit can reduce power consumption by generating a pulse signal only once during power-up.

Description

Semiconductor device having pulse generating circuit for mode selection

The present invention relates to a pulse generating circuit, and more particularly to a pulse selection circuit for the mode selection.

The semiconductor device uses a node reset pulse signal having a pulse width of a predetermined interval in order to determine the initial operating potential of the internal node before performing the operation. In semiconductor devices or products, pulse generation circuits for mode selection are used to have various operating modes. In order to perform the operation of the various modes or to selectively use the modes by fuse or option, a reset pulse generation circuit is required.

1 is a circuit diagram showing the configuration of a pulse generating circuit.

The reset pulse generation circuit operates by receiving a chip enable master clock signal from the outside. Hereinafter, the chip enable master clock signal It is called. The master clock signal Generation of the pulse signal is determined according to the activation interval of.

Referring to FIG. 1, the pulse generation circuit includes an input circuit 10, a delay circuit 20, and an output circuit 30.

The input circuit 10 is provided with an inverter I1, the delay circuit 20 includes a plurality of inverters I2, I3, and I4, and the output circuit 30 is connected to the NAND gate D1. It is provided. Master clock signal to the inverter I1 When is applied, the master clock signal The pulse signal 1Φ ESET is generated in the activation period of. Since the pulse generator circuit applies a reset pulse signal for initializing the node to the semiconductor device, the pulse generator circuit operates even with only one pulse signal. However, no abnormality occurs.

2 is a circuit diagram showing the configuration of a mode selection circuit using a pulse generation circuit.

Master clock signal The pulse signal 1Φ ESET generated for each activation period of is applied to the mode selection circuit. However, when the fuse is connected before that, a low level mode is selected. However, when the reset pulse signal 1Φ ESET generated from the pulse generating circuit is applied, the fuse is cut off and a high level mode is selected.

However, the pulse generating circuit as described above generates an unnecessary pulse signal that is activated every interval in which the master clock signal applied from the outside is activated. Accordingly, unnecessary power is consumed in the mode selection circuit which performs the operation every time according to not only one pulse signal but also other pulse signals. When the pulse generation circuit is connected to the mode selection circuit, even if the fuse is cut, a problem arises in that a current path is formed in a specific portion and power is consumed accordingly.

Accordingly, it is an object of the present invention to provide that only one reset pulse signal is generated when operating power is applied to a semiconductor device, thereby preventing power consumption.

1 is a circuit diagram showing a configuration of a pulse generating circuit according to a conventional embodiment;

2 is a circuit diagram showing in detail the configuration of a mode selection circuit to which a pulse generation circuit is applied;

3 is a circuit diagram showing in detail the configuration of a pulse generating circuit according to an embodiment of the present invention;

4 is an output waveform diagram comparing and comparing output waveforms of pulse signals according to an exemplary embodiment of the present invention;

* Explanation of symbols on main parts of the drawings

100: voltage distribution circuit 200: precharge circuit

300: first inversion circuit 400: second inversion circuit

500: delay circuit 600: output circuit

(Configuration)

According to one feature for achieving the above object, in the semiconductor device that generates a pulse signal by receiving a power supply voltage from the outside, and applying a power supply voltage and ground voltage from the outside Voltage dividing means for receiving and dividing this to output a voltage dividing signal; Precharge means for precharging the voltage division signal to a positive voltage and a negative voltage to a voltage level of a power supply terminal and a ground terminal; First inverting means for receiving a power supply voltage and the voltage division signal from an outside, inverting the voltage division signal, and outputting a first inversion signal; Second inverting means receiving the first inverted signal and inverting the first inverted signal to output a second inverted signal; Delay means for receiving the second inverted signal and delaying the second inverted signal to output a delayed signal; And output means for receiving the delay signal and the second inversion signal and outputting a pulse signal.

In a preferred embodiment of such a circuit, the voltage distribution means is a transistor in which the sources and the drains are connected in series between the first node, the power supply terminal to which a power supply voltage is applied from the outside, and the first node, and the gates are interconnected. And a resistor, one end of which is connected to the first node and the other end of which is connected to a ground terminal.

In a preferred embodiment of such a circuit, the first inverting means includes a PMOS transistor having a source connected to the power supply terminal, a drain connected to the output terminal, a drain connected to the output terminal, and a gate connected to the gate of the PMOS transistor. And an NMOS transistor interconnected with the source and grounded.

In a preferred embodiment of such a circuit, the delay means comprises a second node, a third node, at least one odd number of inverters connected in series between the second node and the third node, and a power supply voltage at one end. And a resistor connected to one of the output terminals of the inverters, and a capacitor connected to the resistor in parallel with one end of the inverter.

In a preferred embodiment of such a circuit, the output means includes a NAND gate having one input terminal connected to the second node, a type force terminal connected to the third node, and an input terminal connected to the output terminal of the NAND gate. And an inverter connected to and outputting the pulse signal to a type force terminal.

(Example)

The novel pulse generating circuit of the present invention generates only one reset pulse signal when a power supply voltage is applied, and a mode selection circuit operating by receiving the reset pulse signal maintains a mode until an external power source is otherwise applied. We reduce power consumption.

Referring to the drawings according to the preferred embodiment of the present invention 2 to 3, 4 as follows.

The reset pulse generation circuit includes a voltage distribution circuit 100, a precharge circuit 200, a first inversion circuit 300, a second inversion circuit 400, a delay circuit 500, and an output circuit 600. . The voltage distribution circuit 100 includes transistors M4 and M5 having a source and a drain connected in series between a power supply terminal 1 to which a power supply voltage VCC is applied from the outside and a first node, and a gate of which is connected to each other. And a resistor R1 connected between the first node and the ground terminal 2 to which the ground voltage VSS is applied. The precharge circuit 200 includes diodes D1 and D2 to which a power supply voltage VCC and a ground voltage VSS are applied to an anode, and cathodes are connected in series. The first inversion circuit 300 includes transistors M6 and M7 to which a power supply voltage VCC and a ground voltage VSS are applied to a source, a drain is interconnected, and a gate is also interconnected.

The second inversion circuit 400 is provided with one inverter I8. The delay circuit 500 includes an odd number of inverters I9, I10, and I11 connected in series between the second node and the third node. Finally, the output circuit 600 includes a NAND gate D2 to which input terminals are connected to the delay circuit 500 and the second node, and an inverter I12 connected to an output terminal of the NAND gate D2. have.

Referring to FIG. 3, the voltage distribution circuit 100 divides the power supply voltage VCC and the ground voltage VSS applied from the outside and outputs the same to the first node. It should be noted that the power supply voltage VCC is a voltage rising with a constant slope. Since the voltage distribution circuit 100 is composed of transistors M4 and M5, a voltage lowered by a threshold voltage of the transistor is transmitted to the first node. At this time, if the voltage output to the first node is greater than the power supply voltage VCC as a positive potential, it is precharged to the power supply voltage level through the diode D1, and the voltage output to the first node is a negative potential. If less than the ground voltage (VSS) as a precharge to the ground voltage level through the diode (D2). The voltage transferred to the first node is transferred to the gates of the PMOS transistor M6 and the NMOS transistor M7 of the first inverting circuit 400.

If the voltages applied to the gates are higher than the threshold voltage of the transistor M7, the NMOS transistor M7 is turned on to discharge current to ground, and a signal of logic ″ 0 ″ is output to the output terminal. The operation of the first inverting circuit 300 including the transistors M6 and M7 is determined depending on whether the voltage applied to the gate is higher or lower than the threshold voltage of the transistor. When a low voltage is previously applied to the first inversion circuit 300, a signal of logic ″ 1 ″ is output, and a second node, which is an output terminal of the second inversion circuit 400, maintains a signal of logic ″ 0 ″.

As the voltage applied to the first inversion circuit 300 is higher than the threshold voltage of the transistor, the second inversion circuit 400 transitions the logic ″ 0 ″ signal of the second node to a signal of logic ″ 1 ″. do. The signal of logic ″ 1 ″ is applied to the inverter I9 of the delay circuit 500 so that the third node is changed to the signal of logic ″ 1 ″. This is changed when the power supply voltage VCC is larger than the sum of the threshold voltage Vtb of the PMOS transistor and the threshold voltage Vtn of the NMOS transistor.

As a result, the output circuit 600 outputs the reset pulse signal 1ΦESET which is activated by logic ″ 1 ″. The reset pulse signal 1ΦESET which is deactivated to the logic ″ 0 ″ is output after the predetermined delay time due to the signal of the logic ″ 0 ″ of the third node that has passed through the delay circuit 500. The reset pulse signal 1Φ ESET is then maintained in an inactive state for a while. At this time, the width of the generated pulse signal is as much as the delay time generated from the delay circuit 500, and accordingly the reset pulse signal 1Φ ESET is activated.

The delay circuit 500 may further include a resistor R2 and a capacitor C as well as inverters I9, I10, and I11 to adjust the width of the reset pulse signal according to a delay time.

2, a pulse generating circuit having the configuration as shown in FIG. 3 is required for the mode selection circuit. The mode selection circuit is a current path including a switching circuit 40, a fuse 50, and a transistor M2 that are always turned on by receiving a power supply voltage VCC and a ground voltage VSS from an external source. Circuit 60, a latch circuit 70 composed of transistor M3 and inverter I5, and a delay circuit 80 composed of even inverters I6, I7. The switching circuit 40 is always turned on due to the ground voltage VSS applied from the outside to form a current path. In the latch circuit 70, as the fuse 50 is connected, the fourth node maintains a logic ″ 1 ″. The logic ″ 1 ″ of the fourth node becomes a logic ″ 0 ″ through the inverter I5, and the logic ″ 0 ″ is transferred to the NMOS transistor M3 and turned off. Accordingly, the fourth node latches a signal of logic ″ 1 ″. The delay circuit 80 delays and outputs the signal of logic " 1 " generated from the inverters I6 and I7. This selects the mode of logic ″ 1 ″.

However, when the reset pulse signal 1ΦESET of one stage of logic ″ 1 ″ generated from the pulse generating circuit is applied to the mode selection circuit, the connection of the fuse is disconnected. When a reset pulse signal 1ΦESET of logic " 1 " is applied to the mode select circuit, transistor M2 of current pass circuit 60 is turned on to send current to ground. As a result, the fourth node becomes a logic " 0 " and the connection with the fuse 50 is disconnected. The signal of logic ″ 0 ″ becomes logic ″ 1 ″ via inverter I5 of latch circuit 70, and the signal is applied to NMOS transistor M3 to turn on transistor M3. Therefore, the fourth node is latched with a signal of logic ″ 0 ″. The delay circuit 80 selects the mode of logic ″ 1 ″ by delaying the signal of logic ″ 1 ″ generated from the inverters I6 and I7. This is maintained until the power goes down to a certain level.

Figure 4 shows the output waveform diagram of the reset pulse signal generated from the pulse generating circuit of the prior art and the present invention.

Referring to FIG. 4, a chip enable master clock signal applied from the outside in the related art. Pulse signal 1Φ ESET was generated each time the signal fell to the low level. Accordingly, when the pulse signals 1Φ ESET of the above stages are applied to the mode selection circuit, the operation is performed for each pulse signal. The mode selection circuit needs to select only one mode, and the power consumption is caused by performing an operation according to one or more unnecessary reset pulse signals.

However, in the present invention, the pulse signal also rises above a predetermined level of the power voltage applied from the outside, so that only one stage of the pulse signal is inactivated after a predetermined time. As a result, the mode selection circuit is operated only once by receiving only one pulse signal, thereby consuming less power. As a result, only one stage of the reset pulse signal is generated when the power is applied and raised from the outside, and the node of the semiconductor device can be initialized by selecting the mode by applying the reset pulse signal to the mode selection circuit.

As described above, when the power supply voltage is applied from the outside and rises, the pulse signal also rises from the predetermined level or more, and generates only one pulse signal which is deactivated after a delay of some time. Therefore, the mode selection circuit to which the pulse signal is applied may operate in response to the pulse signal of one stage, thereby reducing power consumption.

Claims (5)

A semiconductor device that generates a pulse signal by receiving a power supply voltage from the outside, and selects a mode according to the pulse signal. Voltage distribution means for receiving a power supply voltage and a ground voltage from an external source, dividing them, and outputting a voltage division signal; Precharge means for precharging the voltage division signal to a positive voltage and a negative voltage to a voltage level of a power supply terminal and a ground terminal; First inverting means for receiving a power supply voltage and the voltage division signal from an outside, inverting the voltage division signal, and outputting a first inversion signal; Second inverting means receiving the first inverted signal and inverting the first inverted signal to output a second inverted signal; Delay means for receiving the second inverted signal and delaying the second inverted signal to output a delayed signal; And output means for receiving the delay signal and the second inversion signal to output a pulse signal. The method of claim 1, The voltage distribution means A first node; Transistors in which the sources and the drains are connected in series and the gates are interconnected between a first terminal and a power supply terminal to which a power supply voltage is applied from the outside; And a resistor having one end connected to the first node and the other end connected to a ground terminal. The method of claim 1, The first inverting means includes a PMOS transistor having a source connected to the power supply terminal and a drain connected to an output terminal; And a NMOS transistor having a drain connected to the output terminal, a gate interconnected with a gate of the PMOS transistor, and a source grounded. The method of claim 1 The delay means A second node; A third node; At least one odd inverter connected in series between the second node and a third node; A resistor to which a power supply voltage is applied at one end and the other end thereof connected to any one of the output terminals of the inverters; And a capacitor connected in parallel with the resistor and having a power supply voltage applied to one end thereof. The method according to claim 1 or 4, The output means A NAND gate having one input terminal connected to the second node and a type force terminal connected to the third node; And an inverter having an input terminal connected to an output terminal of the NAND gate and outputting the pulse signal to a type force terminal.