KR19980082657A - Real time data observation method and device - Google Patents

Abstract

The scan cell design includes a bypass mode in which the cell's data input DI is directly connected to the cell's scan output SO by a connection that bypasses the cell's scan memory MI.

Description

Real time data observation method and device

FIELD OF THE INVENTION The present invention relates to the testing and evaluation of integrated circuit (IC) operation, and more particularly, to real time observation of selected nodes of an integrated circuit.

1 is commonly referred to as a full scan design. In this conventional scan design style, all functional memories (flip flops / latches) of the IC are separated from combinational logic and include a multiplexer 1 in front of each memory MI. By making it scanable. Since the functional memories are shared for testing, this scan design style has very low test circuit overhead. During functional operation, the multiplexer connects M1 to combinatorial logic to complete the circuit. During the test operation, the multiplexer allows M1 to capture data from combinatorial logic, shift data between M1s, and output the data to combinatorial logic. During the test, the circuit does not function because the multiplexer breaks the normal connection between M1 and the combinatorial logic during the shift (scan). Testing the combinatorial logic is accomplished by these acquisition, shift, and output steps. To operate M1 and multiplexer 1 in test mode the control input (CTL) typically comes from a series of test bus interfaces on the IC, such as the IEEE 1149.1 Test Access Port (TAP).

In microprocessors, microcontrollers and digital signal processors, for example, the full scan design of FIG. 1 can be used for emulation operations. In such emulation operations, (1) scanning the scan path to load normal data, (2) enabling the processor to run for a predetermined period of time (2), stopping the processor, and (3) scanning The steps of scanning the scan path are typically repeated so that the path checks the internal states of the processor. These emulation operations are particularly useful when program code is developed to be executed by the processor.

Figure 2 illustrates another conventional scan approach that allows scan cells to be placed or inserted basically in the functional signal paths of the circuit. The logic associated with these scan cells is dedicated to testing and not shared for functional purposes. During normal operation, the scan cells make a functional circuit connection by the DO path in DI shown through the multiplexer 2. When in functional mode, the scan cell captures and shifts out data without interrupting the normal operation of the circuit since M1s are not functionally used. When placed in test mode, the functional path between DI to DO is broken and the output of M1 is input to the circuit input through multiplexer (2). Testing is similar to that described in FIG. 1. Additional control signals are needed to operate the multiplexer 2.

3 and 4 illustrate a conventional boundary scan approach. The boundary scan applies scan cells between the IC's I / O pads and the core circuitry. During the functional mode, boundary scan cells allow normal I / O operation. When the IC is in normal mode, the boundary scan cells can be controlled to capture and shift out data because they are dedicated to the test logic. During the test mode, the normal mode of the IC is disabled and boundary scan cells are used to capture and shift out data from the input pad and to shift in and output the data to the output pad. The input boundary scan cells of FIG. 3 only allow acquisition and shift out operations at the input pad. That is, no output is possible. The input boundary scan cells of Figure 4 provide for shifting in and outputting data into the core logic. Border scan cells that output data require data to be held during a shift operation. These boundary scan cells require a second memory M2, which is used to hold data to the core / pad until M1 enters new data into M2.

In summary, scan path design is a common test technique for integrated circuits. Scan paths are created by connecting multiple scan cells in series. Scan cells are used to test functional circuits within the IC and to perform boundary scan tests on the IC's I / O. To test, the scan cells must be coupled to an internal circuit node or to the I / O of the IC. To access the scan cells, the serial scan path and the control path become the path of each scan cell.

The fact that the scan cells of the present invention are connected by (1) serial scan and routed path control via the IC, and (2) the fact that the scan cells are connected to internal nodes and / or I / O pads of the IC. I use it. The present invention modifies existing scan cells to add a small amount of circuitry so that these scan cells selectively output real-time internal node or I / O pad signal activity. The ability to select the nodes or I / O pads involved in the scan cells and paths that signal the chip enables many types of tests that are not possible today. Because the present invention uses existing scan path lines and scan cell circuits, the overhead of access is low.

1-4 show a conventional scan cell structure.

5 and 6 illustrate exemplary internal scan designs in accordance with the present invention.

6A illustrates the multiplexer of FIGS. 5-6.

7 and 8 illustrate exemplary boundary scan designs in accordance with the present invention.

9A-9F illustrate the observation capability provided by the internal scan designs of FIGS. 5-6.

10A-10E illustrate the observation capability provided by the boundary scan designs of FIGS. 7-8.

Figure 11 shows a board-level example of the observation capability of the present invention.

12 illustrates a prior art structure of a scan path in an integrated circuit.

13-14 illustrate bus routed test output features in accordance with the present invention.

FIG. 15 illustrates an alternative example to the internal scan design of FIG. 5.

15A is an explanatory diagram of the memory device of FIG. 15.

16 and 17 further illustrate exemplary boundary scan designs in accordance with the present invention.

* Explanation of symbols for main parts of drawings *

M1, M2: Memory

CTL: control input

TAP: test access port

IC: integrated circuit

Exemplary FIG. 5 illustrates how the scan cell of FIG. 1 can be upgraded with a small amount of circuitry to realize the present invention. The additional circuit shown in shaded form includes a second memory M2 and a multiplexer 2. M2 is loaded from M1 following the scan operation. Control of the M2 data and the CTL determines which input to the multiplexer 2 is output from the multiplexer 2. During a scan operation, the CTL always causes the multiplexer 2 to output data D0 to the SI (scan) input of the next scan cell at M1. When no scan is performed, the CTL causes the multiplexer 2 to be programmed by the data from M2 to select either SI or DI output from the multiplexer 2. When programmed to output DI, the OUT node for the combinational logic will be output from the multiplexer 2, otherwise SI is output. When OUT is selected, the scan cell is in observation mode and passes signal activity at the OUT node to the SI input of the next scan cell. If SI is selected, the scan cell is in bypass mode and then passes the SI input to the SI input of the next scan cell.

In the scan path of FIG. 5, what can be seen is that if the first (far left) scan cell is programmed to be in observation mode and the next scan cells are programmed to bypass mode, then the OUT signal associated with the first scan cell is Is transmitted to the SO output of the scan path. More visible, when the second scan cell is in observation mode and the next scan cells are in bypass mode, the OUT signal associated with the second scan cell is delivered to SO. Placing the selected scan cell in observation mode while other scan cells are in bypass mode allows real time observation at the SO of any signal node associated with the scan cell in the IC.

The overhead of this approach to Figure 1 is low because observations occur over existing scan path routes and the circuit area added to each scan cell is small (M2 and multiplexer 2). This is required for a full scan design because M1 is functionally used and cannot be used as a program input to the multiplexer 2. The ability to select and check the real-time operation of all nodes associated with the scan cell in the IC is a small amount of overhead Is realized.

The present invention allows IC manufacturers to use the scan path for conventional scan tests and then reuse the scan path as an embedded real-time observation structure to view the internal activity at each circuit node associated with the scan cell. The ability to use the invention to select and observe internal nodes of the IC while the IC is being functionally tested against the tester provides a new type of test that improves the manufacturer's ability to detect and diagnose speed functional errors. . This test can be repeated after the IC is assembled on the board.

Another advantage of the present invention relates to emulation. In the conventional emulation as described above, state data observation is only available at the end of execution via a scan out operation. However, the present invention allows state data visibility even during execution. The ability to view selected nodes in the IC during execution adds a new dimension to conventional technical emulation.

In order to use the present invention in the prescan design of FIG. 5 for speed visibility of internal nodes during functional testing or during emulation, a special scan operation to be defined needs to be defined. This scan operation, referred to as an observation / bypass data scan, differs from other scans in that the data scanned with M1s is updated with N2. Other scan operations do not update data M2 at M1.

As can be seen in FIG. 5, M1 is shown to serve three purposes. First, these M1s serve as the functional memory for the IC. Secondly, it serves as a scan memory for conventional test and emulation operations. Thirdly, it serves as an input memory for loading observation / bypass data into M2s. The observation / bypass data scan allows to load (update) M2s in the pattern used to select the nodes to be observed. After loading the observation / bypass pattern into M2s, another scan operation is required to load M1s into the start data state where the IC starts executing. Since the start state pattern is the last pattern scanned into M1s before the test or emulation operation starts, the pattern is not updated from M1 to M2 because it overwrites the observation / bypass pattern set before M2s.

Exemplary FIG. 6 illustrates the addition of the multiplexer 3 to the scan cell of FIG. 2 to realize another embodiment of the present invention. The reason why only the multiplexer 3 is required is that M1 can be used to program the multiplexer 3 while the IC is in the normal functional mode. Except for M1 replacing M2, the structure and operation of the additional circuit are the same as described in FIG. The advantages as described in FIG. 5 also apply to the scan cell configuration of FIG. 6. Note that since the scan cell circuit of FIG. 6 is used for testing, the functionality of the circuit is not possible during the scan setting up the test or observation functions.

FIG. 6A illustrates the multiplexer 2 that served as the multiplexer 2 of FIG. 5 or the multiplexer 3 of FIG. 6. During the scan operation, the CTL input directs the output of M1 to the multiplexer output. During non-scan times, CTL allows the data of M1 (FIG. 6) or M2 (FIG. 5) to program the multiplexer to output an SI or DI.

Exemplary FIGS. 7 and 8 illustrate that the present invention is applied to boundary scan design styles. In both figures, multiplexer 2 or multiplexer 3 provides an observation mode and a bypass mode to the boundary scan cell. The input boundary scan cells of FIG. 7 reuse the test memory M1 to program the additional multiplexer 2 as described in FIG. The output boundary scan cells of FIG. 7 reuse the test memory M2 to program the additional multiplexer 3. Both input and output boundary scan cells of FIG. 8 reuse the test memory M2 to program the additional multiplexer 3. The configuration and operation of the observation circuit are the same as described above. Like the scan cells of FIG. 6, the boundary scan cells of FIGS. 7-8 are dedicated for testing, and the scan may be performed to set up real time pad observation without disabling the operation of the IC.

Designers / manufacturers can reuse the boundary scan paths of FIGS. 7-8 for conventional ICs for IC interconnect testing and then reuse the boundary scan paths with an embedded real-time I / O observation structure at each IC pad. Observe signal activity. This capability adds value to manufacturers' ICs by providing system designers with a way to observe the IC's I / O activity in real time. This is almost equivalent to having a separate analyzer coupled to each IC pin. The present invention is useful in systems where the on-line monitoring method can be used to detect early indications of system problems. The invention can also be used as support for repairing and repairing the system. Moreover, the present invention provides on-line I / O visibility, system emulation, and hardware / software integration during system software debug.

9F to 9F illustrate the observation capability provided by the internal scan path designs of FIGS. 5 and 6. 9A shows the data path flow between the serial input (SI) and the serial output (SO) of the IC scan path when all the scan cells (SC) are in bypass mode. 9B shows the first scan cell set up in its observation mode while the other scan cells are in bypass mode. 9C-9F show that all nodes related to all scan cells can be made observable at the serial output.

10A-10E illustrate the observation capability provided by the boundary scan design styles of FIGS. 7 and 8. 10A illustrates the datapath flow between the serial input (SI) and serial output (SO) of the IC boundary scan path when all the scan cells (SC) are in their bypass mode. 10B shows that the first scan cell is set up in its input pad observation mode when the other scan cells are in bypass mode. 10C-10E show that all input and output pads associated with boundary scan cells can be made observable at the serial output.

11 conceptually illustrates the steps of how a scan controller accesses a series of ICs 1-4 on a board using the observation feature of the present invention. In the first step, the scan controller leaks data through the scan path of the ICs in the bypass mode of the present invention. The second step shows a scan controller with setup IC1 for observation of I / O pads and / or internal nodes while other ICs are in bypass mode. In this configuration, any node or I / O pad of IC1 may be selected for observation and output to the scan controller via ICs ICs 2, 3 and 4. The other steps simply show how each IC remaining in the scan path is accessed for real-time observation.

12 illustrates a conventional parallel configuration of scan paths within an IC. The IEEE 1149.1 boundary scan standard teaches using these parallel scan path structures. MX of FIG. 12 represents a multiplexer. Straight line connections between SI and SO are indicated by broken lines. If a straight line connection between the SI and the SO is available, the observed signal input to the SI from the preceding IC can simply go to the SO through the wire rather than through the scan cell (or cells) in bypass mode. When observation and bypass modes are used to use the present invention in the IEEE 1149.1 architecture, it is required that the serial output buffer 120 not be tri-state during times because the signal flows through the ICs in the scan path. Because it interferes with that.

13 illustrates an alternative method of transmitting data from the IC during observation and bypass modes. An additional test output pin (or terminal) TO is added to the IC to output data during the observation and bypass modes of the selected scan path. The TO pin is tri-state such that multiple ICs have a canvas routed TO connection at the board level. The TO pin provides an improvement over using SO in that it can be wired directly to the scan controller of the TO pin, that is, during observation, the data needs to pass through other ICs in the scan path as shown in FIG. There is no. Passing observation data through many ICs can delay data arrival to the scan controller. Using TO, data can be output directly from the IC to the scan controller.

Figure 14 illustrates the steps by which the scan controller accesses a series of ICs on the board using the observation feature of the present invention and the TO pin. In the first step, the operation of the TOs of all ICs becomes impossible. The second step represents a scan controller with setup IC1 for observing I / O pads and / or internal nodes using the TO when the TOs of other ICs are unavailable. In this configuration, data from the internal node or I / O pad of IC1 can be selected for observation and output directly to the scan controller with respect to the TO, while the data in FIG. I had to pass. The other steps simply indicate the possibility of TO real time observation of each remaining IC in the scan path.

Exemplary FIG. 15 illustrates an alternative to the scan design of FIG. 5. This alternative design provides advantages for large amounts of required circuitry. As illustrated in FIG. 5, the scan cells of FIG. 15 include a second memory M2 and a multiplexer 2. In addition, M2 is loaded from M1 during the observation / bypass scan operation and the output from M2 controls which input to multiplexer 2 is output from multiplexer 2. During the scan operation, the CTL always causes the multiplexer 2 to output the data from M1 to the SI input of the next scan cell. While no scan is performed, the CTL allows the multiplexer 2 to be programmed by the data from M2 to select the SI or M1 data to be output from the multiplexer 2 (see AND gate in FIG. 15A). When programmed to output M1 data, the IN node of the combinational logic circuit will be output from the multiplexer 2, otherwise SI is output. If IN is selected, the scan cell will be in observation mode and will pass signal activity at the IN node to the SI input of the next scan cell. If SI is selected, the scan cell is in bypass mode and passes the SI input to the SI input of the next scan cell.

The multiplexer 2 of FIG. 15 requires two input multiplexers as compared to the three input multiplexers of FIG. 5, which alleviates the multiplexer circuit by approximately 33%. Two input multiplexers can be used in FIG. 15 because the IN node to the combinational logic is selected as the observation point instead of the OUT node from the combinational logic of FIG. Since the M1 output is already input to the multiplexer, and because the M1 output is an IN node to combinatorial logic, the observation of the IN node instead of the OUT node removes the multiplexer input. The operation of the observation method is otherwise the same as described above. As shown in FIG. 1, saving of the multiplexer circuit is important in a full scan design. This is because ten million nodes will potentially be associated with each M1. If three input multiplexers are used in place of two input multiplexers, the additional circuitry required to achieve the present observation capability will be increased by approximately 33% for each node. This 33% increase is multiplied by the number of nodes in the circuit, which can be thousands, as mentioned above.

Also shown in FIG. 15B is an example of a memory serving as M2. Switch M and bus holder BH can serve as M2 because M2 has minimal output load and performance is not an important factor in design. The switch is momentarily closed to enter control into the multiplexer 2 during each observation / bypass scan operation. After the switch is opened, the bus holder maintains control of the multiplexer 2. Again, in the full scan design, it is important to minimize the circuit of M2. This is because M2 will be required to be applied to each IN node of the circuit. The circuit of M2 and the multiplexer 2 can be further alleviated by integrating them into one optimal circuit.

Although the approach of the present invention has been shown to be applied to access data for testing, it is clear that this approach can also be used to access data for other purposes.

Exemplary FIG. 16 illustrates boundary scan cells disposed on a bi-directional (I / O) pad of an IC. The IC core circuit is capable of controlling the three-state output buffer 161 connected to the I / O pad (ENA), data output (OUT) and the input driving the I / O pad if a three-state output buffer is available. Buffer 163 has an input IN for receiving data from an I / O pad. The border scan cells on the ENA, OUT and IN paths contain the data observations and bypass features described in the border scan cells of FIGS. 7 and 8, respectively. Input and output buffers are shown in FIG. 16 to indicate I / O operation. For simplicity, input and output buffers are not shown in the previous example figures, but it should be understood that these input and output buffers exist.

In Fig. 16, it is possible to observe through a boundary scan cell (lower cell) by applying data from an I / O pad using the present invention. It is also possible to observe IC core output data through the output boundary scan cell (middle cell). Moreover, it is possible to observe the possible output from the IC core through the possible boundary scan cell (upper cell). Since the input boundary scan cell observes the I / O pad data, it actually provides observation of both input and output data through the I / O pad. It should be noted that the IC output data observable by the output boundary scan cell is a subset of the observable I / O data from the input boundary scan cell, and it is possible to optimize the boundary scan cell and the observation circuit as shown in FIG. Do.

In Figure 17, the input boundary scan cell has been removed from the I / O pad. In addition, the multiplexer 1 of the output boundary scan cell has an additional input to receive data from the I / O pad and to receive additional control input from the possible boundary scan cell output. The additional input determines whether output data from the IC core or data from the I / O pad is captured to M1 through the multiplexer 1 during a conventional boundary scan test. Moreover, the multiplexer 3 of the output boundary scan cell has data from the I / O pads connected as observation data instead of the output data from the IC core as shown in FIG.

In the optimal boundary scan cell configuration of FIG. 17, only IC capable outputs, or data appearing on an I / O pad, can be observed in real time using the present invention. However, no loss in data observation as the data appearing on the I / O pads are both input data and output data from the IC, resulting in the circuit optimization shown in FIG. 17 compared to the non-optimal circuit shown in FIG. .

Although exemplary embodiments of the invention have been described above, the description is not limited to the scope of the invention and this may be practiced in various embodiments.

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Claims (2)

For the scan cell, Scan input; Data entry; Scan output; A memory circuit connected between the scan output and the scan and data inputs; And Circuitry for bypassing the memory circuit to directly connect the scan input to the scan output Scan cell comprising a. A method of operating a plurality of serially connected scan cells, the method comprising: Placing a scan cell of one of the scan cells into an observation node whose data node connected to the target circuit to be evaluated is also directly connected to the scan output of said one scan cell; And While the one scan cell is in the observation mode, placing the other one of the scan cells in bypass mode where the scan output is directly connected to the scan input. And operating a plurality of serially connected scan cells.