KR19980056996A - Thin film transistor of semiconductor device and manufacturing method thereof - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Semiconductor device manufacturing method.

2. The technical problem to be solved by the invention

To reduce the leakage current of the drain in the off state and series resistance between the source and drain in the on state to provide a thin film transistor of a semiconductor device having a drain offset structure having a high on / off current ratio and a method of manufacturing the same .

3. Summary of Solution to Invention

A gate electrode is formed on the semiconductor substrate, a floating gate electrode in the form of a spacer is formed on the sidewall of the gate electrode, a gate insulating film and an amorphous silicon film are formed on the entire structure, and a silicon ion implantation process is performed in the amorphous silicon film. Next, a method of manufacturing a thin film transistor of a semiconductor device comprising forming a source / drain region by a high concentration impurity ion implantation process using a source / drain region forming mask having a drain offset structure.

4. Important uses of the invention

Used in thin film transistor manufacturing process in semiconductor device manufacturing process.

Description

Thin film transistor of semiconductor device and manufacturing method thereof

The present invention relates to a thin film transistor of the semiconductor device and a method of manufacturing the same, and particularly, a high on / off current ratio of a thin film transistor used as a load resistance in a highly integrated SRAM device. A thin film transistor of a semiconductor device having a drain offset structure having characteristics and a method of manufacturing the same.

In general, thin film transistors (TFTs) are used in fields such as static random access memory (SRAM), liquid crystal display (LCD), and silicon on insulator (SOI).

1A to 1C are cross-sectional views of a thin film transistor manufacturing process of a semiconductor device according to the prior art.

First, FIG. 1A is a gate electrode 2 formed on a semiconductor substrate 1 on which a predetermined lower layer is already formed, and a gate oxide film 3 and an amorphous silicon film 4 are sequentially formed on an entire structure. Next, the n ^- ion implantation process for forming the channel region 4a is shown for the amorphous silicon film 4.

Subsequently, after the photoresist 5 is applied over the entire structure, the photoresist 5 is exposed and developed with a source / drain ion implantation mask for forming a drain offset region. Then, a p ⁺ ion implantation process is performed using the photoresist 5 as an ion implantation mask, so that the source / drain has a drain offset structure (reference numeral A) in which the gate electrode 2 and the drain region are separated by a predetermined distance. The formation of the region 4b is shown.

Finally, Figure 1C shows the photoresist 5 removed and then heat treated.

However, in the case of the thin film transistor having the drain offset region A as described above, the field emission occurs along the grain boundary of the polysilicon film of the source / drain region due to the high electric field at the drain side. This causes the leakage current to increase in the off state, thereby lowering the electrical characteristics of the vehicle.

In order to solve this problem, the leakage field can be reduced by reducing the drain field of the offset drain structure itself, but the current in the on state is reduced to increase the series resistance between the source and the drain, which is required for high density and high density SRAMs. There is a problem in that a thin film transistor having a high on / off current ratio cannot be formed.

The present invention devised to solve the above problems is to reduce the leakage current of the drain in the off state and the series resistance between the source / drain in the on state of the drain offset (Drain Offset) structure having a high on / off current ratio It is an object of the present invention to provide a thin film transistor of a semiconductor device and a method of manufacturing the same.

1A to 1C are cross-sectional views of a manufacturing process of a thin film transistor of a semiconductor device according to the prior art;

2A through 2C are cross-sectional views of a thin film transistor manufacturing process of a semiconductor device according to an embodiment of the present invention;

* Explanation of symbols for main parts of the drawings

10 semiconductor substrate 30 gate electrode

30: LPCVD oxide film 40: polysilicon film for floating gate electrode

40a: floating gate electrode 50: gate oxide film

60: amorphous silicon film 60a: channel region

60b: source / drain regions

In order to achieve the above object, the present invention provides a thin film transistor including a gate electrode formed on a semiconductor substrate, a gate insulating film formed on the semiconductor substrate and a gate electrode, and a channel region and a source / drain region formed on the gate insulating film. And a floating gate electrode insulated from the semiconductor substrate and the gate electrode and formed on the sidewall portion of the gate electrode.

The present invention also provides a method of manufacturing a thin film transistor having a source / drain region having a drain offset structure, the method comprising: forming a gate electrode on a semiconductor substrate, sequentially forming an insulating film and a conductive film for a floating gate electrode on the entire structure; Forming a floating gate electrode on the sidewall of the gate electrode by etching the conductive film and insulating film for the floating gate electrode without a mask, forming a gate insulating film and an amorphous silicon film on the entire structure, and greatly increasing the crystal size of the amorphous silicon film. And performing a silicon ion implantation process to form a source / drain region by a high concentration impurity ion implantation process using a source / drain region forming mask having a drain offset structure.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A to 2C are cross-sectional views illustrating a manufacturing process of a thin film transistor of a semiconductor device according to an embodiment of the present invention.

2A illustrates a process of depositing a polysilicon film for a gate electrode on a semiconductor substrate 10 on which a predetermined lower layer is already formed, and performing a dopant (n ⁺ ) doping process on the polysilicon film for a gate electrode. After the gate electrode 20 is formed by an etching process using a forming mask, an oxide film 30 having a thickness of about 250 Pa to about 500 Pa by LPCVD (LPCVD) method over the entire structure and The polysilicon film 40 for the floating gate electrode is deposited, and the impurity (n ⁺ ) doping process is performed on the polysilicon film 40 for the floating gate electrode.

Subsequently, in FIG. 2B, the polysilicon film 40 for floating gate electrode and the LPCVD oxide film 30 are etched without mask to form a floating gate electrode 40a on the sidewall of the gate electrode 20. The gate oxide film 50 and the amorphous silicon film 60 having a thickness of about 1000 Pa to 2000 Pa are sequentially formed, and then heat-treated for about 20 hours in an argon gas atmosphere of about 500 ° C to 600 ° C. The recrystallization of the silicon film 60 is shown.

Lastly, FIG. 2C shows silicon ions for increasing the crystal size of the amorphous silicon film 60 with respect to the amorphous silicon film 60 of about 1 × 10 ¹⁴ ions / cm 2 to about 10 × 10 ¹⁴ ions / cm 2. After ion implantation at a dose amount, an n ^- ion implantation process for forming a channel region 60a is performed, and an ion implantation using a source / drain ion implantation mask for forming a drain offset region. The process of p ⁺ ion implantation to form a source / drain region 60b having a drain offset structure (A) is followed by heat treatment.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

According to the present invention, the floating gate electrode remains on the sidewall of the gate electrode in the form of a spacer, thereby reducing the electric field between the drain and the gate in the off state due to the potential of the floating gate electrode, thereby reducing the leakage current. The floating gate electrode acts as an accumulation layer to reduce the series resistance between the source and the drain, thereby increasing the on-state current, thereby manufacturing a thin film transistor having a high on / off current ratio. Can improve.

Claims (8)

A conventional thin film transistor having a gate electrode formed on a semiconductor substrate, a gate insulating film formed on the semiconductor substrate and the gate electrode, a channel region formed on the gate insulating film, and a source / drain region, wherein the semiconductor substrate and the gate electrode are formed. And a floating gate electrode insulated from the gate electrode sidewall and insulated from the gate electrode. Forming a gate electrode on the semiconductor substrate, sequentially forming an insulating film and a conductive film for the floating gate electrode on the entire structure, and etching the entire surface of the floating gate electrode and the insulating film without a mask to form a floating gate on the sidewall of the gate electrode. Forming an electrode, forming a gate insulating film and an amorphous silicon film on the entire structure, performing a silicon ion implantation process to increase the crystal size of the amorphous silicon film, and forming a source / drain region mask having a drain offset structure A method of manufacturing a thin film transistor of a semiconductor device, comprising the step of forming a source / drain region by a high concentration impurity ion implantation process. 3. The thin film transistor of claim 2, further comprising performing heat treatment for recrystallization of the amorphous silicon film before performing the silicon ion implantation process to increase the crystal size of the amorphous silicon film. Manufacturing method. 4. The semiconductor device of claim 3, further comprising performing a channel ion implantation process for forming a channel region after performing a silicon ion implantation process for increasing the crystal size of the amorphous silicon film. Method for manufacturing a thin film transistor. The method of claim 3, wherein the heat treatment for recrystallization of the amorphous silicon film is performed for about 20 hours in an argon gas in a temperature range of about 500 ° C. to 600 ° C. 5. The method of claim 2, wherein the silicon ion implantation process for increasing the crystal size of the amorphous silicon film is performed by implanting silicon ions in a dose of about 1 × 10 ¹⁴ ions / cm 2 to about 10 × 10 ¹⁴ ions / cm 2. The thin film transistor manufacturing method of the semiconductor device characterized by the above-mentioned. The method of claim 2, wherein the insulating layer is formed to a thickness of about 250 kW to 500 kW by the LPCVD method. The method of claim 2, wherein the amorphous silicon film is formed to a thickness of about 1000 GPa to 2000 GPa.