KR19980045138A - Semiconductor memory device - Google Patents

Abstract

The present invention discloses a semiconductor memory device. The apparatus includes a buffer for buffering an inverted row address strobe signal, delay means for delaying an output signal of the buffer, and for transmitting and latching an output signal of the delay means in response to a signal generated in response to a clock signal. First transmission and latching means, second transmission and latching means for transmitting and latching an output signal of the first transmission and latching means in response to an inverted signal of the signal, and an output signal of the second transmission and latching means An address buffer having a first signal generating means for generating a first signal by buffering a signal, an active signal generating means for generating an active signal by combining a function selection signal, and the first signal in a first state of the active signal Second signal generating means for generating a second signal by latching the first signal; and latching the first signal in a first state of the active signal to generate a third signal. By comprising a third signal generating means for production generates a valid address upon the occurrence of said third signal. Therefore, the period tRCD can be reduced.

Description

Semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of reducing a time required for applying a row address strobe signal and a column address strobe signal.

The internal operation of the dynamic semiconductor memory device uses a combination of address signals applied from the outside to find a location in a desired cell, and simultaneously stores the stored memory information inputted with the address in a designated cell in the form of a charge, and then converts it into a voltage to generate a series of amplification processes. It carries out the function of transferring the memory information to the outside through.

In order to read the data of the memory cell in this manner, first, the valid row address information is latched by the signal PRAR generated by the row address strobe (RAS) command, and then the word line corresponding to the address information is enabled. The charge stored in the cell shares the charge with the bit line, and the bit line sense amplifier senses and amplifies the difference between the bit line and the inverted bit line generated through the charge sharing, and delivers the amplified signal to the input / output line. .

In the above operation, the column select line signal is enabled and the column select transistor is enabled at a time when the signal amplified by the bit line sense amplifier is delivered to the input / output line to a level sufficient to drive the sense amplifier of the input / output line. A column address storage (CAS) command must be applied so that it can be turned on to transfer the bitline level to the input / output lines, and thus the delay required to apply the column address strobe command even if the row address strobe command is applied. The time is called tRCD.

Time (tRCD) is a very important parameter to obtain the necessary data from memory. Especially in the application of graphic memory, time (tRCD) becomes more important as single bit access speed is important for 3D implementation. In order to improve the tRCD speed, efforts are being made in various fields.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of receiving a RAS command and reducing a delay time required for applying a CAS command.

The semiconductor memory device of the present invention for achieving the above object is a buffer for buffering the inverted row address strobe signal, a delay means for delaying the output signal of the buffer, in response to a signal generated in response to a clock signal First transmission and latching means for transmitting and latching an output signal of the delay means, second transmission and latching means for transmitting and latching an output signal of the first transmission and latching means in response to an inverted signal of the signal; And an active signal generating means for generating an active signal by combining an address buffer having a first signal generating means for buffering an output signal of the second transmission and latching means to generate a first signal, and a function selection signal. Second signal generating means for latching the first signal in a first state of an active signal to generate a second signal, and the active scene In the first state, characterized in that for generating an effective address upon the occurrence of they said third signal provided by a third signal generating means for generating a third signal by latching the first signal.

1 is a circuit diagram of an address buffer of a conventional semiconductor memory device.

2A and 2B show circuits for generating the signals PR and PRAR of the present invention, respectively.

3 is a circuit diagram of an address buffer of the semiconductor memory device of the present invention.

4 illustrates a logic circuit of the semiconductor memory device of the present invention.

5A and 5B are circuit diagrams of a signal generation circuit PR and PRAR of the present invention.

6 is an operation timing diagram for explaining the operation of the circuit of the prior art and the present invention.

Hereinafter, a conventional semiconductor memory device will be described with reference to the accompanying drawings before describing the semiconductor memory device of the present invention.

1 is a circuit diagram of an address buffer of a conventional semiconductor memory device, and includes a buffer 10, delay circuits 12 and 30, inverters 14, 18, 20, 24, 26, 32, 34, 36, 38, 40, 70, 72, 80, 82, 84, 92, 94, 96, CMOS transfer gates 16, 22, automatic pulse generator circuit 28, AND gates 42, 44, 48, 50, NAND gates 58, 60, 62, 64, 66, 68, 98, 99, PMOS transistors 74, 86, NMOS transistors 76, 78, 88, 90, and NOR gates 54, 56, 58, 60).

2A and 2B show circuits for generating signals PR and PRAR of the present invention, respectively. The circuit shown in FIG. 2A is composed of inverters 110 and 112, and the circuit shown in FIG. 114, the NAND gate 116, and the inverters 118 and 120.

FIG. 6 is an operation timing diagram for explaining the operation of the circuit shown in FIGS. 1 and 2A and B. An inverted row address strobe signal is buffered through the buffer 10 and delayed through the delay circuit 12. FIG. And latched in response to the pulse signal PCLK rising to the high level at the rising edge of the clock signal CLK and being delayed for a predetermined time and falling to the low level, the pulse signal is generated by the automatic pulse generator circuit 28, and the delay circuit. Delayed by 30 generates a signal PRP. The signal PRP is compared in the comparison circuit 200 with signals generated by the function selection signal generation circuit 100 and latched by the tri-state buffer and latch circuit 300 to generate the signal PR. That is, the signal PR rising to the high level is generated when the signal PRD rises to the high level at the high level of the function selection signal. This signal is delayed by the circuit shown in FIG. 2A to generate the signal PRD, and this signal is delayed by the circuit shown in FIG. 2B to generate the signal PRAR. When this signal PRAR occurs, a valid address signal is output.

As described above, the conventional semiconductor memory device has a disadvantage in that the generation of the signal PRAR is slow because the signal PR is generated after the function to be determined in the row address selection portion is determined. That is, in FIG. 1, an asynchronous signal that is not synchronized with the clock signal CLK is used in the logic unit for selecting a function to increase the speed, but delays the signal PRP so that the signal is sufficiently marginal with the latest asynchronous signal. A circuit 30 and an automatic pulse generator circuit 28 are used, and a tri-state buffer and a latch circuit 300 are used to latch the row address strobe signal.

3 is a circuit diagram of an address buffer of a semiconductor memory device of the present invention, which includes a buffer 10, a delay circuit 12, inverters 14, 18, 20, 24, 26, 130, 132, and CMOS transfer gates. It consists of (16, 22).

4 illustrates a logic circuit of the semiconductor memory device of the present invention, wherein the function selection circuit 100, NAND gates 134, 136, 138, 140, 144, 150, and 154 and inverters 142 shown in FIG. , 144, 146, 148, 152, 156, 158, and AND gates 160.

5A and 5B are circuit diagrams of the signal PR and PRAR generating circuits of the present invention, and FIG. 5A shows inverters 162, 174, and 176, NAND gates 164, 166, 168, and 170, and an NMOS transistor. The circuit shown in FIG. 5B is composed of a delay circuit 180, NAND gates 182, 184, and 186, inverters 190 and 192, and an NMOS transistor 188. The circuit shown in FIG.

Fig. 6 is an operation timing diagram for explaining the operation of the circuits shown in Figs. 3, 4, and 5A and B. The inverted row address strobe signal RASB is buffered by the buffer 10 and the delay circuit 12 is closed. Delay through. In response to the signal PCLK generated in response to the clock signal CLK, the output signal of the delay circuit 12 is latched and delayed by the inverters 130 and 32 to generate the signal PR. In other words, the signal PR becomes a pulse signal for shifting the level at the rising edge of the clock signal PCLK. In the present invention, the output signal PR of the address buffer is generated independently of the function selection signal. The logic circuit shown in Fig. 4 generates a signal PACT. 5A compares and latches the signals PR and PRE and the signals PR and PACT, respectively, to generate a signal PRD. FIG. 5B inputs and latches a signal comparing the RAS precharge signal and the signals PR and PACT to generate a signal PRAR. That is, the signal PRAR is latched only when the function selection signal and the signal PR are enabled at the same time. Thus, the signal PRAR is generated earlier than the period T by the conventional art.

Therefore, the semiconductor memory device of the present invention can generate the address PRAR early, thereby improving the generation speed of the effective address, improving the overall low access time, and reducing the period tRCD.

Claims (1)

A buffer for buffering the inverted row address strobe signal; Delay means for delaying the output signal of the buffer; First transmitting and latching means for transmitting and latching an output signal of said delaying means in response to a signal generated in response to a clock signal; Second transmission and latching means for transmitting and latching an output signal of the first transmission and latching means in response to the inverted signal of the signal; And an address buffer having first signal generating means for buffering an output signal of said second transmitting and latching means to generate a first signal. Active signal generating means for generating an active signal by combining a function selection signal; Second signal generating means for latching the first signal to generate a second signal in a first state of the active signal; And third signal generating means for latching the first signal in the first state of the active signal to generate a third signal to generate an effective address upon generation of the third signal. .