KR102877879B1 - Method for optical proximity correction in which consistency is maintain and method for manufacturing mask using the same - Google Patents

Abstract

A computer-readable medium including program code is disclosed. When the program code is executed by a processor, the processor executes the steps of: dividing a layout of a semiconductor chip into a plurality of patches; generating a plurality of segments from the layout of each of the plurality of patches, wherein a first patch of the plurality of patches includes first segments and a second patch includes second segments; calculating hash values corresponding to each of the first segments; calculating hash values corresponding to each of the second segments; calculating bias values of segments having a first hash value among the first segments; calculating a representative value based on the bias values; and applying the representative value to segments having the first hash value among the first segments.

Description

Method for optical proximity correction in which consistency is maintained and method for manufacturing mask using the same

The present invention relates to a semiconductor process, and more specifically, to an optical proximity correction method that maintains consistency and a mask manufacturing method using the same.

With the recent rapid development of the electronics industry, demand is increasing for electronic devices with higher performance, greater reliability, and smaller sizes. Electronic devices are implemented using semiconductor components manufactured through semiconductor manufacturing processes. Consequently, to meet these demands, the structures of semiconductor devices are becoming increasingly complex and highly integrated.

Semiconductor devices are manufactured through the photolithography process. Through this process, a layout containing various patterns is printed on a semiconductor wafer. However, as the integration of semiconductor processes increases, the distance between the image patterns on the mask is becoming increasingly close. This proximity causes interference and diffraction of light, potentially resulting in a distorted layout printed on the wafer that differs from the desired layout.

To prevent layout distortion, resolution enhancement techniques such as optical proximity correction (OPC) are utilized. However, maintaining consistency when performing OPC on patterns with identical shapes and ambient conditions is crucial for the reliability of semiconductor devices. Furthermore, the simulation process for generating bias values is time-consuming. Therefore, maintaining consistency while efficiently performing OPC is crucial.

Embodiments of the present disclosure provide an optical proximity correction method that maintains consistency for patterns having identical ambient conditions.

Furthermore, embodiments of the present disclosure provide a method for manufacturing a mask generated using optical proximity correction that maintains consistency.

In a computer-readable medium including a program code according to an embodiment of the present disclosure, when the program code is executed by a processor, the processor executes the steps of: dividing a layout of a semiconductor chip into a plurality of patches; generating a plurality of segments from the layout of each of the plurality of patches, wherein a first patch of the plurality of patches includes first segments and a second patch includes second segments; calculating hash values corresponding to the first segments and the second segments using a hash function, respectively; calculating bias values of segments having a first hash value among the first segments; calculating a representative value based on the bias values; and applying the representative value to segments having the first hash value among the first segments, wherein the hash function depends on a first characteristic value of each segment, a second characteristic value of at least one segment adjacent to each segment, and a third characteristic value between each segment and the at least one segment.

In another embodiment of the present disclosure, a computer-readable medium including a program code, when the program code is executed by a processor, the processor executes the steps of: generating a plurality of segments from a layout of a semiconductor device; calculating a hash value for each of the plurality of segments using a hash function that depends on a first characteristic value of each segment, a second characteristic value of at least one segment adjacent to each segment, and a third characteristic value between each segment and the at least one segment; calculating bias values for each of the plurality of segments; calculating a representative value based on bias values of a plurality of segments having the same hash value among the calculated hash values; and applying the representative value to the plurality of segments having the same hash value.

According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device includes the steps of: generating a plurality of segments from a layout of the semiconductor device; calculating a hash value for each of the plurality of segments using a hash function that depends on a first characteristic value of each segment, a second characteristic value of at least one segment adjacent to each segment, and a third characteristic value between each segment and the at least one segment; calculating bias values for each of the plurality of segments; calculating a representative value based on bias values of a plurality of segments having the same hash value among the calculated hash values; generating a mask corrected according to the representative value; and forming patterns on a substrate using the mask.

According to exemplary embodiments of the present disclosure, a hash value is calculated for each segment generated from a layout, taking into account the characteristics of the segment itself and surrounding segments. A representative value is then calculated for the bias values of segments with the same hash value. This calculated representative value is applied to all segments with the same hash value. Therefore, consistency is maintained between patches or between semiconductor chips.

FIG. 1 is a flowchart showing a method for designing and manufacturing a semiconductor device according to an embodiment of the present disclosure.
FIG. 2 conceptually illustrates a photolithography system used to fabricate a mask according to an embodiment of the present disclosure.
Figure 3 conceptually illustrates the layout formed on the wafer.
Figure 4 conceptually illustrates the process of dividing the outline of a layout into multiple segments in optical proximity correction.
Figure 5 conceptually illustrates the layout updated by optical proximity correction.
FIG. 6 illustrates a system for performing optical proximity correction according to an embodiment of the present disclosure.
FIG. 7 illustrates a method for performing optical proximity correction according to an embodiment of the present disclosure.
FIG. 8 illustrates a method for performing optical proximity correction according to an embodiment of the present disclosure.
FIG. 9 conceptually illustrates elements that determine a hash value of a segment according to an embodiment of the present disclosure.
FIG. 10 conceptually illustrates elements that determine a hash value of a segment according to an embodiment of the present disclosure.
FIG. 11 illustrates a method for performing optical proximity correction according to an embodiment of the present disclosure.
Figure 12 conceptually illustrates calculating a representative value from the bias values of segments of multiple patches.
FIG. 13 illustrates a method for performing optical proximity correction according to an embodiment of the present disclosure.
FIG. 14 illustrates a method for performing optical proximity correction according to an embodiment of the present disclosure.
Figure 15 conceptually illustrates the tasks assigned by the master device.
FIG. 16 is a block diagram showing a device for manufacturing a mask generated by the optical proximity correction of the present disclosure.

Hereinafter, embodiments of the present invention will be described clearly and in detail to the extent that a person having ordinary skill in the art can easily practice the present invention.

Components described with reference to terms such as unit, module, block, ~or, ~er used in the detailed description and functional blocks depicted in the drawings may be implemented in the form of software, hardware, or a combination thereof. For example, software may be machine code, firmware, embedded code, and application software. For example, hardware may include electrical circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, microelectromechanical systems (MEMS), passive components, or a combination thereof.

FIG. 1 is a flowchart showing a method for designing and manufacturing a semiconductor device according to an embodiment of the present disclosure.

At step S11, high-level design of the semiconductor integrated circuit can be performed. High-level design can mean describing the target integrated circuit in a high-level computer language. For example, a high-level language such as C can be used. Circuits designed through high-level design can be expressed more specifically through register transfer level (RTL) coding or simulation. Furthermore, the code generated through register transfer level coding can be converted into a netlist and synthesized into the entire semiconductor device. The synthesized schematic circuit is verified by a simulation tool, and an adjustment process may be performed based on the verification results.

At step S12, layout design can be performed to implement the logically completed semiconductor integrated circuit on a silicon substrate. For example, the layout design can be performed by referencing the schematic circuit synthesized in the high-level design or its corresponding netlist. The layout design can include a routing procedure that places and connects various standard cells provided from the cell library according to defined design rules.

A cell library for layout design can include information about the operation, speed, and power consumption of standard cells. Most layout design tools define cell libraries for representing circuits at a specific gate level in a layout. Layout can be a process for defining the shape and size of patterns for configuring transistors and metal wiring to be formed on a silicon substrate. For example, to actually form an inverter circuit on a silicon substrate, a layout design tool can appropriately place layout patterns such as PMOS, NMOS, N-WELL, gate electrodes, and metal wiring to be placed thereon. To this end, a suitable inverter can first be searched and selected from among the inverters already defined in the cell library.

Furthermore, routing can be performed on the selected and placed standard cells. For example, routing can be performed on the selected and placed standard cells with upper wiring. Through the routing process, the standard cells can be interconnected according to the design. Most of these processes can be performed automatically or manually by a layout design tool. For example, the placement and routing of standard cells can be performed automatically using a separate Place & Routing tool.

After routing, the layout can be verified for any design rule violations. Verification can include a Design Rule Check (DRC), which verifies that the layout conforms to the design rules; an Electronic Rule Check (ERC), which verifies that internal electrical connections are intact; and a Layout vs. Schematic (LVS), which verifies that the layout matches the gate-level netlist.

In step S13, optical proximity correction (OPC) may be performed. Using a photolithography process, layout patterns obtained through layout design may be implemented on a silicon substrate. Optical proximity correction may be a technique for correcting distortion phenomena that may occur during the photolithography process. Specifically, optical proximity correction can correct distortion phenomena, such as refraction or process effects, that occur due to the characteristics of light during exposure using the laid-out pattern. While performing optical proximity correction, the shape and position of the designed layout patterns may be slightly corrected (biased). Optical proximity correction of the present disclosure will be described in detail below.

In step S14, a photomask can be manufactured based on the layout changed by the optical proximity correction. For example, the photomask can be manufactured by using a chrome film applied on a glass substrate to describe the layout patterns.

At step S15, a semiconductor device can be manufactured using a photomask. The manufacturing process for semiconductor devices using a photomask can involve repeating various exposure and etching processes. Through these processes, the patterns configured during the layout design can be sequentially formed on a silicon substrate.

FIG. 2 conceptually illustrates a photolithography system used to manufacture a mask according to an embodiment of the present disclosure. Referring to FIG. 1 , the photolithography system (1000) may include a light source (1200), a mask (1400), a reduction projection device (1600), and a wafer stage (1800). However, the photolithography system (1000) may further include components not shown in FIG. 1 . For example, the photolithography system (1000) may further include a sensor used to measure the height and inclination of the surface of the wafer (WF).

The light source (1200) can emit light. The light emitted by the light source (1200) can be irradiated to the mask (1400). For example, the light source (1200) can include an ultraviolet light source (e.g., a KrF light source having a wavelength of 234 nm, an ArF light source having a wavelength of 193 nm, etc.). For example, the light source (1200) can further include a collimator (not shown). The collimator can convert the ultraviolet light into parallel light. The parallel light can be provided to the mask (1400). For example, the collimator can include a dipole aperture or a quadruple aperture used to increase the depth of focus of the ultraviolet light.

The mask (1400) may include image patterns used to print a layout on a wafer (WF). The image patterns may be formed as transparent areas and opaque areas. The transparent area may be formed by etching a metal layer on the mask (1400). The transparent area may transmit light emitted by the light source (1200). On the other hand, the opaque area may not transmit light. The mask (1400) may be manufactured based on optical proximity correction according to an embodiment of the present disclosure. The optical proximity correction of the present disclosure will be described in detail below.

The reduction projection device (1600) can receive light that has passed through the transparent area of the mask (1400). The reduction projection device (1600) can match the circuit patterns of the layout to be printed on the wafer (WF) with the image patterns of the mask (1400). The wafer stage (1800) can support the wafer (WF).

A transparent area included in the image patterns of the mask (1400) can transmit light emitted by a light source (1200). The light passing through the mask (1400) can be irradiated onto the wafer (WF) via a reduction projection device (1600). As a result, a layout including circuit patterns corresponding to the image patterns of the mask (1400) can be printed on the wafer (WF).

However, as the integration of semiconductor processes increases, the distance between image patterns on the mask (1400) has become much closer, and the width of the transparent area has become much narrower. Due to this "proximity," interference and diffraction of light may occur, and a distorted layout different from the desired layout may be printed on the wafer (WF). If a distorted layout is printed on the wafer (WF), the designed circuit may operate abnormally.

To prevent layout distortion, resolution enhancement technology (RET) is utilized. Optical proximity correction (OPC) is an example of a resolution enhancement technique. Through OPC, the degree of distortion, such as light interference and diffraction, is predicted in advance. Furthermore, based on the predicted results, image patterns to be formed on the mask (1400) are biased in advance. As a result, the desired layout can be printed on the wafer.

In the optical proximity correction according to an embodiment of the present disclosure, a hash value is calculated for each segment constituting a layout based on the segment's own characteristics and surrounding conditions. Furthermore, a representative value is calculated based on bias values of segments having the same hash value. The representative value can be assigned to segments having the same hash value. As a result, optical proximity correction can be uniformly performed on patterns having the same shape and surrounding conditions, and a mask (1400) closer to the intended mask can be provided.

Hereinafter, embodiments of the present invention will be described. In the following description, it is assumed that model-based optical proximity correction is performed using computer simulation. However, this assumption is not intended to limit the present invention. It will be apparent to those skilled in the art that the present invention can be applied to other types of resolution enhancement techniques.

Figure 3 conceptually illustrates a layout formed on a wafer. For example, layout (LO1) may include first circuit patterns (R1) to fourth circuit patterns (R4). However, the form of layout (LO1) illustrated in Figure 3 is merely an example to aid understanding of the present invention and is not intended to limit the present invention.

The area depicted by the solid line represents the target layout to be printed on the wafer (WF). For example, the designer of the layout (LO1) may want to print the layout (LO1) of the first circuit pattern (R1) to the fourth circuit pattern (R4) along the solid line of Fig. 2 on the wafer (WF). That is, the solid line of Fig. 3 represents the layout to be printed as the target layout. The target layout is provided as the initial design layout.

On the other hand, the area shown by the dotted line represents the layout actually printed on the wafer (WF). In reality, during the semiconductor manufacturing process, distortions such as interference and diffraction of light may occur due to the mask (1400) of FIG. 2. Due to this distortion, the first circuit pattern (R1) to the fourth circuit pattern (R4) along the dotted line of FIG. 2 may be printed on the wafer (WF) contrary to the designer's intention. If a distorted layout is printed on the wafer (WF), the designed circuit may operate abnormally contrary to the designer's intention.

To prevent layout distortion, optical proximity correction can be performed. In optical proximity correction, the design layout can be biased to reduce the error between the actual layout to be printed and the target layout based on the design layout. An example of optical proximity correction will be described with reference to FIGS. 4 and 5.

Figure 4 conceptually illustrates the process of dividing the outline of a layout into multiple segments in optical proximity correction. As an example, the process of dividing the outline of the design layout (LO1) shown in solid lines in Figure 3 into multiple segments is described.

A plurality of division points (Division Points) may be set on the outline of the design layout (LO1). For example, a first division point (PD_1) and a second division point (PD_2) may be set on the outline of the design layout (LO1). Based on the first division point (PD_1) and the second division point (PD_2), a segment (SEG) may be obtained. Similarly, based on the plurality of division points, the outline of the design layout (LO1) may be divided into a plurality of segments. A segment may mean a minimum unit on which a bias is executed.

Although the term "segmentation" is used here, it may not imply a physical division. In FIG. 4, multiple segments are depicted as being physically divided, but this is provided conceptually to aid understanding of the present invention.

In optical proximity correction, each of the segments can be subject to biasing. Each of the segments can be biased independently. For example, a segment (SEG) can be biased along one of a first direction (e.g., an outward direction of each circuit pattern corresponding to the plurality of segments) and a second direction (e.g., an inward direction of each circuit pattern corresponding to the plurality of segments) independently of other segments. Each of the segments can be biased to reduce an error between the actual layout and the target layout.

Since the process of calculating bias values is well known to those skilled in the art, a detailed description of the process will be omitted. Based on the calculated bias values, each segment can be biased. An example of an updated design layout obtained based on the biased segments will be described with reference to Fig. 5.

Fig. 5 conceptually illustrates a layout updated by optical proximity correction. To facilitate understanding, a new first circuit pattern (R1') updated from the first circuit pattern (R1) of Fig. 3 will be described as an example. Furthermore, descriptions corresponding to the second to fourth circuit patterns (R2) to (R4) of Fig. 3 will be omitted.

The solid line in Fig. 5 represents a new first biased pattern (R1') included in the updated design layout. According to the process described with reference to Fig. 4, the outline of the first circuit pattern (R1) of Fig. 3 can be divided into several segments, and each of the divided segments can be biased. As shown in Fig. 5, each of the segments can be biased along one of a first direction (e.g., outward direction) and a second direction (e.g., inward direction). As a result, a first biased pattern (R1') can be obtained.

Each segmented segment can be biased to reduce the error between the actual layout and the target layout. For example, the dotted line in Figure 5 represents the actual layout to be printed based on the updated design layout. By biasing each segmented segment, the error between the actual layout and the target layout can be reduced.

However, referring to FIGS. 3 and 4 , the upper left segment, the lower left segment, and the upper right segment of the first circuit pattern (R1) have the same ambient conditions. Therefore, it is preferable that the upper left segment, the lower left segment, and the upper right segment of the first circuit pattern (R1) have the same bias value. Nevertheless, referring to FIG. 5 , it can be seen that the upper left segment, the lower left segment, and the upper right segment of the first correction pattern (R1') are biased asymmetrically.

Of course, Figures 2 through 4 are merely examples. However, in actual optical proximity correction, segments with identical ambient conditions may be biased differently due to numerical calculation errors. In particular, as the process of calculating bias values corresponding to each segment is repeated, errors can accumulate. If a distorted design layout is printed on a wafer (WF) due to accumulated errors, the designed circuit may operate abnormally, contrary to the designer's intention.

Therefore, in an embodiment of the present invention, a segment's hash value is calculated by considering its own characteristics and the characteristics of its surrounding segment(s). If two segments have identical characteristics, not only their own characteristics but also the characteristics of adjacent segments, the hash values of each segment will be identical. A representative value can be calculated from the bias values of segments with identical hash values. As a result, optical proximity correction can be performed uniformly.

FIG. 6 illustrates a system for performing optical proximity correction according to an embodiment of the present disclosure. FIG. 7 illustrates a method for performing optical proximity correction according to an embodiment of the present disclosure. For example, FIG. 7 may illustrate a specific embodiment of the optical proximity correction step (S13) of FIG. 1. FIG. 8 illustrates a method for performing optical proximity correction according to an embodiment of the present disclosure.

In an embodiment, the system (100) of FIG. 6 includes a master device (110) and slave devices (121 to 12n). For example, the master device (110) and the slave devices (121 to 12n) may be implemented as separate computing devices. Alternatively, the master device (110) and the slave devices (121 to 12n) may each be implemented as a plurality of processor cores. Although not shown in the drawing, the system (100) may further include a storage medium in which an OPC tool for executing optical proximity correction is stored. In addition, the system (100) may further include a memory in which the OPC tool is loaded when the OPC tool is executed.

In an embodiment, the OPC tool performing optical proximity correction of the present disclosure may be a computer program product including a computer-readable program code or a computer program product including a non-transitory computer-usable medium including a computer-readable program code.

Referring to FIGS. 6 and 7, a method of optical proximity correction of the present disclosure will be described. Optical proximity correction for the layout of a semiconductor chip (A) can be performed by a master device (110) driving an OPC tool. The master device (110) can receive the layout of the semiconductor chip (A). For example, the layout of the semiconductor chip (A) can be a result of the layout design step (S12) of FIG. 1. The layout can include a plurality of circuit patterns.

The master device (110) can divide the layout of the semiconductor chip (A) into a plurality of patches (PA1 to PAn). For example, a patch may be the minimum unit processed by a slave device. The master device (110) can assign the patches (PA1 to PAn) of the semiconductor chip (A) to the slave devices (121 to 12n), respectively. Each slave device can process the assigned patch. As an example, the first slave device (121) processes the first patch (PA1).

The first slave device (121) can generate segments based on the layout included in the first patch (PA1) (S110). The process of generating segments has been previously described with reference to FIG. 4.

The first slave device (121) can calculate hash values of segments of the first patch (PA1) (S120). For example, the hash value may reflect the characteristics of the segment itself and the characteristics of at least one segment surrounding the segment. For example, segments with identical characteristics and surrounding conditions may have identical hash values. The factors determining the hash value will be described in detail with reference to FIGS. 9 and 10.

The first slave device (121) can calculate bias values of segments constituting the first patch (PA1) (S130). The bias values of the segments can be obtained based on simulation results for a grid, which is the minimum simulation unit of the OPC tool. For example, as the grid size increases, the time required to obtain a bias value may decrease, but a less precise bias value may be obtained. In other words, the consistency of segments with identical ambient conditions may be weakened. Conversely, as the grid size decreases, the time required to obtain a bias value may increase, but a more precise bias value may be obtained. In other words, the consistency of segments with identical ambient conditions may be strengthened. Meanwhile, the process of calculating the bias value is well known to those skilled in the art and will therefore be omitted.

The master device (110) can collect hash values and bias values calculated by the first slave device (121). The master device (110) can calculate a representative value based on the collected hash values and bias values (S140). As described with reference to FIG. 5, even if segments have the same ambient conditions, the bias values may differ. Therefore, to maintain consistency, the master device (110) can calculate a representative value from the bias values of segments having the same hash value. For example, the representative value may be, but is not limited to, an average value of the bias values of segments having the same hash value.

The master device (110) can update the library with representative values corresponding to segments having the same hash value (S150). For example, the library may include hash values and their corresponding bias values. Furthermore, the master device (110) can also update the library with bias values for segments having unique, non-duplicated hash values. Based on the library, the master device (110) can generate a biased pattern.

Among the segments of a semiconductor chip (A), the same bias value (i.e., representative value) is applied to segments having the same hash value. Therefore, consistency can be maintained among patterns having the same surrounding environment in multiple patches constituting the semiconductor chip (A). However, consistency is not limited to multiple patches of the same chip, and consistency can also be maintained between semiconductor chips. For example, consistency can be maintained between semiconductor chips by similarly performing the aforementioned processes for semiconductor chips (B) to (Z). This will be described with reference to FIGS. 6 and 8 .

Referring to FIGS. 6 and 8, the library can be updated (S150) according to the optical proximity correction performed on the semiconductor chip (A).

Thereafter, in order to perform optical proximity correction on the semiconductor chip (B), the master device (110) can receive the layout of the semiconductor chip (B). The master device (110) can divide the layout of the semiconductor chip (B) into a plurality of patches (PA1 to PAn). The master device (110) can assign the patches (PA1 to PAn) of the semiconductor chip (B) to the slave devices (121 to 12n), respectively.

Slave devices (121 to 12n) can each process patches (PA1 to PAn) of a semiconductor chip (B). As an example, the first slave device (121) processes the first patch (PA1) of the semiconductor chip (B). The first slave device (121) can generate segments based on the layout included in the first patch (PA1) (S210). The first slave device (121) can calculate hash values of the segments of the first patch (PA1) (S220).

Based on the hash value calculated in step S220, the library can be searched (S230). In an embodiment, the first slave device (121) can transmit the calculated hash values to the master device (110). The master device (110) can compare the hash values received from the first slave device (121) with the hash values to be stored in the library. Based on the comparison result, the master device (110) can determine whether the hash value is stored in the library.

If the search result indicates that the hash value is already stored in the library, there may be no need to newly obtain the bias value for the segment(s) corresponding to the hash value. Therefore, when generating a corrected layout for the semiconductor chip (B), the bias value stored in the library can be used as is (S260).

Conversely, if the hash value is not already stored in the library, it is necessary to newly obtain the bias value of the segment(s) corresponding to the hash value. For example, the master device (110) may instruct the first slave device (121) to calculate the bias value for the segment, and the first slave device (121) may calculate the bias value (S240). The above-described step S240 may be performed by each of the slave devices (121 to 12n) that process the patches (PA1 to PAn) of the semiconductor chip (B). The slave devices (121 to 12n) may transmit the calculated bias values and the corresponding hash values to the master device (110).

The master device (110) can calculate a representative value based on hash values and bias values (S250). The master device (110) can update the representative value corresponding to segments having the same hash value in the library (S270). The updated representative value (or bias value) can be applied when generating a corrected layout for not only the semiconductor chip (B), but also the semiconductor chip (A), the semiconductor chip (C), and the semiconductor chip (Z). In other words, consistency can be maintained between the semiconductor chips.

Meanwhile, the embodiment of FIG. 8 can have a relatively shorter library creation time compared to the embodiment of FIG. 7. This is because the process of calculating bias values for segments having the same hash value among hash values already stored in the library can be omitted. In this case, when calculating bias values for segments of a semiconductor chip (B), it is possible to reduce the size of the grid, which is the minimum simulation unit. Even if the simulation time increases by reducing the grid size, a trade-off with the secured library creation time can be possible.

FIG. 9 conceptually illustrates elements that determine a hash value of a segment according to an embodiment of the present disclosure. By way of example, the segments illustrated in FIG. 9 correspond to the segments (SEG1, SEG2, and SEG3) illustrated in FIG. 4 . The first segment (SEG1) may correspond to the first circuit pattern (R1) of FIG. 3 , and the second segment (SEG2) and the third segment (SEG3) may correspond to the third circuit pattern (R2) of FIG. 3 .

In calculating the hash value of the first segment (SEG1), a hash function that depends on multiple factors may be used. The multiple factors may be related to the segment's own values and the segment's surrounding conditions. For example, the factors affecting the hash value may include a first characteristic value related to the segment's own characteristics. The factors affecting the hash value may include a second characteristic value related to the characteristics of an adjacent segment adjacent to the segment. Furthermore, the factors affecting the hash value may include a third characteristic value related to the characteristics between the segment and the adjacent segment. Consequently, segments that have the same surrounding conditions and their own characteristics may have the same hash value.

As a factor determining the hash value of the first segment (SEG1), the length (L1) of the first segment (SEG1) may be adopted. The length (L1) of the first segment (SEG1) includes the length in the first direction (D1) and/or the length in the second direction (D2). For example, as illustrated in FIG. 9, if the first segment (SEG1) is composed of a component in the first direction (D1) and a component in the second direction (D2), each of the component in the first direction (D1) and the component in the second direction (D2) may independently function as a factor determining the hash value. In this case, the direction in which each component extends may also be adopted as a factor determining the hash value. Therefore, even if two segments have the same overall length, if the lengths in the first direction (D1) are different from each other or the lengths in the second direction (D2) are different from each other, the hash values may be different from each other.

As a factor for determining the hash value of the first segment (SEG1), the biasing direction (①) of the first segment (SEG1) may be adopted. The biasing direction may refer to the order in which the segments are simulated in grid units by the OPC tool. For example, four segments constituting one circuit pattern (e.g., R1 of FIG. 3) may have the same biasing direction. For example, FIG. 8 illustrates that the segments constituting the circuit patterns (R1 of FIG. 3) are sequentially corrected in a clockwise direction. For example, when the segments are corrected in a clockwise direction, the biasing direction may have a first value, and when the segments are corrected in a counterclockwise direction, the biasing direction may have a second value.

As a factor for determining the hash value of the first segment (SEG1), distances (D12, D13) between the first segment (SEG1) and adjacent segments may be adopted. Here, the adjacent segment may mean a segment positioned within a distance that affects the first segment (SEG1) during optical proximity correction. In addition, the adjacent segment may mean an adjacent circuit pattern that does not belong to the circuit pattern (R1 of FIG. 3) to which the first segment (SEG1) belongs. For example, the adjacent segment may refer to at least some of the segments (e.g., SEG2 and SEG3) belonging to the circuit pattern (R3 of FIG. 3) adjacent to the circuit pattern (R1 of FIG. 3) to which the first segment (SEG1) belongs.

As another factor for determining the hash value of the first segment (SEG1), the lengths (L2, L3) of the adjacent segments (SEG2, SEG3) may be adopted, respectively. The lengths (L2, L3) of the adjacent segments (SEG2, SEG3) include the length in the first direction (D1) and/or the length in the second direction (D2). For example, as illustrated in FIG. 9, when the adjacent segment (SEG2 or SEG2) is composed of a component in the first direction (D1) and a component in the second direction (D2), each of the component in the first direction (D1) and the component in the second direction (D2) may independently serve as a factor for determining the hash value.

When calculating the hash value of the first segment (SEG1), the above-described factors can be comprehensively considered to calculate the hash value. In other words, the slave device can calculate the hash value of the first segment (SEG1) through a hash function that uses the above-described factors as independent variables.

Figure 10 conceptually illustrates the elements that determine the hash value of a segment according to an embodiment of the present disclosure. Unlike the embodiment of Figure 9, this embodiment calculates a temporary hash value by considering only elements related to the segment itself. The final hash value is then calculated based on the distance between the temporary hash values and the segments.

As factors determining the temporary hash value of the first segment (SEG1), the length (L1) and the biasing direction (①) of the first segment (SEG1) can be adopted. Both the component of the length (L1) in the D1 direction and the component in the D2 direction can independently affect the hash value. The slave device (any one of 121 to 12n of FIG. 6) can calculate the temporary hash value of the first segment by considering the length of the first direction (D1) and/or the second direction (D2) of the first segment (SEG1) and the order (e.g., clockwise) in which the first segment (SEG1) is simulated in grid units by the OPC tool.

The length (L2) and biasing direction (②) of the second segment (SEG2) may be adopted as factors for determining the temporary hash value of the second segment (SEG2). The slave device may calculate the temporary hash value of the second segment by considering the length of the first direction (D1) and/or the second direction (D2) of the second segment (SEG2) and the order in which the second segment (SEG2) is simulated in grid units by the OPC tool (e.g., counterclockwise).

The length (L3) and biasing direction (③) of the third segment (SEG2) may be adopted as factors for determining the temporary hash value of the third segment (SEG3). The slave device may calculate the temporary hash value of the third segment by considering the length of the first direction (D1) and/or the second direction (D2) of the third segment (SEG3) and the order in which the third segment (SEG3) is simulated in grid units by the OPC tool (e.g., counterclockwise).

In calculating the final hash value of the first segment (SEG1), the hash values of the segments (SEG1, SEG2, SEG3), the distance (D12) between the first segment (SEG1) and the second segment (SEG2), and the distance (D13) between the first segment (SEG1) and the third segment (SEG3) may be taken into consideration. For example, the slave device may calculate the final hash value of the first segment (SEG1) by reflecting the temporary hash value of the second segment (SEG2), the temporary hash value of the third segment (SEG3), and the distances (D12, D13) to the temporary hash value of the first segment (SEG1).

However, when calculating the final hash value of the first segment (SEG1), if the distance between the first segment (SEG1) and the adjacent segment (SEG2 or SEG3) exceeds a threshold value, the corresponding hash value may not be reflected when calculating the final hash value of the first segment (SEG1). Here, the threshold value may be a distance that does not affect the simulation using the OPC tool.

FIG. 11 illustrates a method for performing optical proximity correction according to an embodiment of the present disclosure. By way of example, the embodiment of FIG. 11 illustrates in more detail the processing steps performed on the semiconductor chip (A) illustrated in FIG. 7.

At step S310, the master device (110) can divide the layout of the semiconductor chip (A) into a plurality of patches (PA1 to PAn). At step S320, as described with reference to FIG. 4, the master device (110) can assign the divided patches (PA1 to PAn) to a plurality of slave devices (121 to 12n), respectively. At steps S330 to S350, each slave device can process the assigned patches.

In an embodiment, the first slave device (121) can generate multiple segments from the first patch (PA1) (S331). The first slave device (121) can calculate a hash value for each of the generated segments (S341). For example, the first slave device (121) can calculate the hash value of each segment in various ways as described in FIG. 9 or FIG. 10. These operations will be similarly performed by the second slave device (122) to the n-th slave device (12n).

In step S351, the first slave device (121) can calculate a bias value for each segment. The bias value can be obtained based on simulation results for each of the grids, which are the minimum simulation units of the OPC tool. The second slave device (122) to the nth slave device (12n) can also calculate bias values for the segments of the assigned patch.

At step S360, the master device (110) can collect hash values and bias values calculated by the slave devices (121 to 12n).

At step S370, the master device (110) may generate a representative value for segments having the same hash value. For example, the representative value may be obtained from the bias values of segments having the same hash value. For example, the representative value may be the average of the bias values of segments having the same hash value, but is not limited thereto. For example, the representative value may be the median, mode, etc. of the bias values of segments having the same hash value.

At step S380, the library may be updated. For example, a representative value of the correction values of segments with identical hash values may be stored in the library. Furthermore, the correction values of segments with non-duplicate hash values may be stored in the library.

Figure 12 conceptually illustrates calculating a representative value from the bias values of segments of multiple patches. For ease of explanation, reference is also made to Figure 6.

The first slave device (121) generates segments (SEG1 to SEGi) from the first patch (PA1) and calculates hash values (HV1 to HVi) corresponding to each of the segments (SEG1 to SEGi). The second slave device (122) generates a plurality of segments (SEG1 to SEGj) from the second patch (PA2) and calculates hash values (HV1 to HVj) corresponding to each of the segments (SEG1 to SEGj). Similarly, the n-th slave device (12n) generates a plurality of segments (SEG1 to SEGn) from the n-th patch (PAn) and calculates hash values (HV1 to HVk) corresponding to each of the segments (SEG1 to SEGk).

The first slave device (121) can calculate bias values (BV1 to BVi) corresponding to each of the segments (SEG1 to SEGi). The second slave device (122) can calculate bias values (BV1 to BVj) corresponding to each of the segments (SEG1 to SEGj). Similarly, the nth slave device (12n) can calculate bias values (BV1 to BVk) corresponding to each of the segments (SEG1 to SEGk).

The master device (110) can collect the hash values and bias values of each patch, and calculate a representative value from the bias values of segments having the same hash values. For example, it can be assumed that the hash value (HV1) of the first segment (SEG1) of the first patch (PA1), the hash value (HV2) of the second segment (SEG2) of the second patch (PA2), and the hash value (HVk) of the k-th segment (SEGk) of the n-th patch (PAn) are the same. Here, the representative value may be, but is not limited to, the mean, median, mode, etc. The calculated representative value can be updated in the library, and can be commonly applied to segments having the same hash value.

According to the embodiments of FIG. 9 or 10, the first segment (SEG1) of the first patch (PA1), the second segment (SEG2) of the second patch (PA2), and the k-th segment (SEGk) of the n-th patch (PAn), which have the same hash value, can be expected to have the same ambient conditions. Accordingly, by applying the same correction value to segments having the same ambient conditions to maintain consistency between patches, the designed circuit can be operated normally according to the designer's intention.

FIG. 13 illustrates a method for performing optical proximity correction according to an embodiment of the present disclosure. By way of example, the embodiment of FIG. 13 illustrates in more detail the processing steps performed on the semiconductor chip (B) illustrated in FIG. 8.

At step S410, the master device (110) can divide the layout of the semiconductor chip (A) into a plurality of patches (PA1 to PAn). At step S420, as described with reference to FIG. 4, the master device (110) can assign the divided patches (PA1 to PAn) to a plurality of slave devices (121 to 12n), respectively. At steps S430 and S440, each slave device can process the assigned patch.

In an embodiment, the first slave device (121) can generate a plurality of segments from the first patch (PA1) (S431). The first slave device (121) can calculate a hash value for each of the generated segments (S441). For example, the first slave device (121) can calculate the hash value of each segment in various ways as described in FIG. 9 or FIG. 10. These operations will be similarly performed by the second slave device (122) to the n-th slave device (12n).

At step S450, the master device (110) can receive hash values from the slave devices (121 to 12n) and search a library based on the hash values. Here, the library can include a library for the semiconductor chip (A) (e.g., S380 of FIG. 11). The master device (110) can compare the hash values stored in the library with the hash values received from the slave devices (121 to 12n) to determine whether optical proximity correction is required for each segment of the semiconductor chip (B).

If the library contains a value matching the hash value received from the slave devices (121-12n), there is no need to calculate a bias value for the segment corresponding to the hash value. On the other hand, if the library does not contain a value matching the hash value received from the slave devices (121-12n), there is a need to calculate a bias value for the segment corresponding to the hash value.

At step S460, the master device (110) can transmit the search results at step S450 to the slave devices (121 to 12n). For example, the first slave device (121) can, with reference to the search results, calculate bias values for segments of the first patch (PA1) that are not stored in the library (S461). The remaining slave devices (122 to 12n) can similarly calculate bias values for their segments (S462 to S46n).

At step S470, the master device (110) can collect bias values calculated by the slave devices (121 to 12n).

At step S480, the master device (110) may generate a representative value for segments having the same hash value. For example, the representative value may be obtained from the bias values of segments having the same hash value. For example, the representative value may be the mean, median, mode, etc. of the bias values of segments having the same hash value.

At step S490, the library may be updated. For example, a representative value of the correction values of segments with identical hash values may be stored in the library, and a correction value of segments with non-duplicate hash values may be stored in the library.

To summarize the embodiments of FIGS. 12 to 14 described above, a library is generated by calculating bias values (including representative values) of segments for a semiconductor chip (A). Here, for segments having the same hash value, the representative value is commonly applied to maintain consistency between patches of the semiconductor chip (A). Furthermore, the representative value stored in the library is commonly applied to other semiconductor chips (B to Z) to maintain consistency between the semiconductor chips.

Meanwhile, since each slave calculates bias values for all segments of the corresponding patch, the time required to perform optical proximity correction may become excessively long. Therefore, another method can be adopted to reduce the time required to calculate bias values. This will be described with reference to FIGS. 14 and 15.

FIG. 14 illustrates a method for performing optical proximity correction according to an embodiment of the present disclosure. FIG. 15 conceptually illustrates tasks assigned by a master device.

First, referring to FIG. 14, the master device (110) can divide the layout of the semiconductor chip (A) into a plurality of patches (PA1 to PAn) (S510) and assign the divided patches (PA1 to PAn) to a plurality of slave devices (121 to 12n) (S520). Each slave device can generate segments from the corresponding patch (S531 to S53n) and calculate hash values for the generated segments (S541 to S54n). The slave devices (121 to 12n) can transmit the calculated hash values to the master device (110).

The master device (110) can assign tasks to each slave device based on hash values (S560). Here, the task may refer to obtaining bias values for segments with identical (i.e., overlapping) hash values. For a more detailed explanation of task assignment by the master device (110), reference is also made to FIG. 15 .

For example, a first slave device (121) generates segments (SEG1 to SEGi) from a first patch (PA1) and calculates hash values (HV1 to HVi) corresponding to each of the segments (SEG1 to SEGi). A second slave device (122) generates a plurality of segments (SEG1 to SEGj) from a second patch (PA2) and calculates hash values (HV1 to HVj) corresponding to each of the segments (SEG1 to SEGj). Similarly, an n-th slave device (12n) generates a plurality of segments (SEG1 to SEGn) from an n-th patch (PAn) and calculates hash values (HV1 to HVk) corresponding to each of the segments (SEG1 to SEGk).

Here, it is assumed that the hash values (HV1, HV3) of the first patch, the hash value (HV2) of the second patch (PA2), and the hash value (HVk) of the n-th patch (PAn) are the same (above, the first hash value). It is assumed that the hash value (HV2) of the first patch, the hash values (HV1, HVj) of the second patch (PA2), and the hash value (HV3) of the n-th patch (PAn) are the same (above, the second hash value). In addition, it is assumed that the hash value (HVi) of the first patch, the hash value (HV3) of the second patch (PA2), and the hash values (HV1, HV2) of the n-th patch (PAn) are the same (above, the third hash value).

According to the embodiment of FIG. 11, since each slave device calculates bias values for all segments, the time required to perform optical proximity correction may be long. However, according to the embodiment of FIG. 15, the master device (110) assigns a task to the slave device responsible for the patch with the largest number of segments having the same hash value. Here, the task may mean calculating bias values for segments having the same hash value and calculating a representative value based on the calculated bias values.

For example, since the patch with the largest number of segments having the first hash value is the first patch (PA1), the master device (110) may assign a task (Task A) to the first slave device (121) in charge of the first patch (PA1) to calculate bias values for the segments (SEG1, SEG2) of the first patch (PA1). In addition, the master device (110) may not assign the task of calculating the bias value for the second segment (SEG2) of the second patch (PA2) to the second slave device (122). Similarly, the master device (110) may not assign the task of calculating the bias value for the k-th segment (SEGk) of the n-th patch (PAn) to the n-th slave device (12n).

Similarly, since the patch with the largest number of segments having the second hash value is the second patch (PA2), the master device (110) can distribute a task (Task B) to the second slave device (122) to calculate bias values for the segments (SEG1, SEGj) of the second patch (PA2). The master device (110) will process the segments having the third hash value in a similar manner.

Referring back to FIG. 14, at step S570, the slave devices (121 to 12n) may calculate bias values for the segments. For example, calculating the bias values may include calculating a bias value associated with a task assigned from the master device (110). That is, the task assigned from the master device (110) may include calculating bias values for multiple segments having the same hash value. Furthermore, calculating the bias values may include calculating a bias value for a segment having a unique, non-duplicated hash value that is not associated with a task assigned from the master device (110). However, a slave device may not calculate a bias value associated with a task assigned to another slave device.

For example, as illustrated in FIG. 15, the first slave device (121) may calculate bias values for segments having the first hash value. However, the first slave device (121) may not calculate bias values related to a task assigned to the second slave device (122) (i.e., calculation of bias values of segments having the second hash value). The first slave device (121) may not calculate bias values related to a task assigned to the n-th slave device (12n) (i.e., calculation of bias values of segments having the third hash value). That is, the first slave device (121) does not calculate bias values of the segments (SEG2, SEGi). Of course, the first slave device (121) will calculate bias values related to tasks that are not assigned to other slave devices.

Similarly, the second slave device (122) will calculate the hash values of the segments (SEG1, SEGj) having the second hash value and will not calculate the hash values of the segments (SEG2, SEG3) assigned to other slave devices. The nth slave device (12n) will calculate the hash values of the segments (SEG1, SEG2) having the third hash value and will not calculate the hash values of the segments (SEG3, SEGk) assigned to other slave devices.

The master device (110) can collect bias values calculated by slave devices (121 to 12n) (S580) and calculate a representative value based on the collected bias values (S590).

For example, the master device (110) can calculate a representative value to be commonly applied to segments having a first hash value based on the bias values received from the first slave device (121). The master device (110) can calculate a representative value to be commonly applied to segments having a second hash value based on the bias values received from the second slave device (122). Similarly, the master device (110) can calculate a representative value to be commonly applied to segments having a third hash value based on the bias values received from the n-th slave device (12n).

The master device (110) can update the calculated representative value(s) in the library. Furthermore, the master device (110) can also update the bias values of segments with unique, non-duplicated hash values in the library. The updated representative value(s) and bias value(s) in the library can be applied not only to the patches (PA1 to PAn) but also to other semiconductor chips. As a result, the consistency of the corrected mask can be maintained.

FIG. 16 is a block diagram illustrating a device for manufacturing a mask generated by the optical proximity correction of the present disclosure. Referring to FIG. 16, the mask manufacturing device (2000) may include a processor (2100), memory/storage (2200), and a user interface (2300). The mask manufacturing device (2000) may be used to manufacture a mask (1400) according to the embodiments of the present invention described with reference to FIGS. 2 to 15.

The processor (2100) may include at least one of a general-purpose processor and a dedicated processor, such as a workstation processor. The processor (2100) may perform various mathematical operations and/or logical operations to perform layout division, segment generation, hash value calculation, bias value calculation, representative value calculation, update, etc., as described with reference to FIGS. 3 to 15 . For this purpose, the processor (2100) may include one or more processor cores. For example, the processor core of the processor (2100) may include a special purpose logic circuit, such as, for example, a field programmable gate array (FPGA), an application specific integrated chip (ASIC), etc.

The memory/storage (2200) can temporarily or semi-permanently store data processed or to be processed by the processor (2100). To this end, the memory/storage (2200) can include at least one of volatile memory such as dynamic random access memory (DRAM), static RAM (SRAM), synchronous DRAM (SDRAM), and/or non-volatile memory such as flash memory, phase-change RAM (PRAM), magneto-resistive RAM (MRAM), resistive RAM (ReRAM), ferro-electric RAM (FRAM), and the like.

According to the operation of the processor (2100) and the memory/storage (2200), the embodiments of the present invention described with reference to FIGS. 3 to 15 may be implemented. The mask manufacturing device (2000) may be used to manufacture a mask (1400) according to the operation of the processor (2100) and the memory/storage (2200).

The mask manufacturing device (2000) can execute software according to the operation of the processor (2100) and memory/storage (2200). For example, the software may include an operating system and/or an application. The operating system may provide one or more services to the application and may act as an intermediary device between the application and components of the mask manufacturing device (2000). For example, the application may include a program used to design a layout according to embodiments of the present invention described with reference to FIGS. 3 to 15.

The user interface (2300) may operate to provide the user (10) with results obtained by the operations of the processor (2100) and the memory/storage (2200). Furthermore, the user interface (2300) may be used to receive various data (e.g., data related to the design of the layout, etc.) from the user (10). For example, the user (10) may be a designer of the mask (1400) and the layout. For example, the user interface (2300) may include input/output interfaces such as a display device, a speaker, a keyboard, a mouse, etc.

The mask manufacturing device (2000) can output a final updated design layout (FU) according to the embodiments of the present invention described with reference to FIGS. 3 to 15. The mask manufacturing device (2000) can manufacture a mask (1400) based on the final updated design layout (FU). The mask (1400) can be manufactured including image patterns corresponding to the final updated design layout (FU).

The above-described embodiments are specific examples for practicing the present invention. The present invention will encompass not only the embodiments described above, but also embodiments that can be easily modified or modified. Furthermore, the present invention will encompass techniques that can be easily modified and implemented using the embodiments described above. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined not only by the claims set forth below, but also by equivalents of the claims of the present invention.

1000: Photolithography System
1200: Light source
1400: Mask
1600: Reduction projection device
1800: Wafer Stage

Claims (20)

In a computer-readable medium including a program code, when the program code is executed by a processor, the processor:
A step of dividing the layout of a semiconductor chip into multiple patches;
A step of generating a plurality of segments from the layout of each of the plurality of patches, wherein a first patch among the plurality of patches includes first segments and a second patch includes second segments;
A step of calculating hash values corresponding to each of the first segments and the second segments using a hash function;
A step of calculating bias values of segments having a first hash value among the first segments;
A step of calculating a representative value based on the above bias values; and
Among the first segments, a step of applying the representative value to segments having the first hash value is executed,
A computer-readable medium wherein the hash function depends on a first characteristic value of each segment, a second characteristic value of at least one segment adjacent to each segment, and a third characteristic value between each segment and the at least one segment. In the first paragraph,
A computer-readable medium in which the representative value is one of the average, median, and mode of the bias values of the segments having the first hash value. In the first paragraph,
When the above program code is executed by the processor, the processor:
A computer-readable medium further executing the step of updating the above representative value in the library. In the first paragraph,
When the above program code is executed by the processor, the processor:
A computer-readable medium further executing the step of calculating a bias value of a second segment having a second hash value that does not overlap with other hash values among the hash values of the first segments. In paragraph 4,
When the above program code is executed by the processor, the processor:
A computer-readable medium further executing the step of updating the bias value of the second segment in the library. In the first paragraph,
When the above program code is executed by the processor, the processor:
A computer-readable medium further executing a step of applying the representative value to segments having the first hash value among the second segments. In the first paragraph,
The first characteristic value includes at least one of the length and biasing direction of each segment,
wherein the second characteristic value comprises the length of at least one segment,
A computer-readable medium wherein the third characteristic value comprises a distance between each segment and the at least one segment. In paragraph 7,
A computer-readable medium in which each of the components of each segment in the first direction and each of the components of each segment in the second direction independently affects the hash function, when the length of each of the segments extends in the first direction and the second direction. In a computer-readable medium including a program code, when the program code is executed by a processor, the processor:
A step of generating a plurality of segments from a layout of a semiconductor device;
For each of the plurality of segments, a step of calculating a hash value using a hash function depending on a first characteristic value of each segment, a second characteristic value of at least one segment adjacent to each segment, and a third characteristic value between each segment and the at least one segment;
A step of calculating bias values for each of the plurality of segments;
A step of calculating a representative value based on the bias values of a plurality of segments having the same hash value among the calculated hash values; and
A computer-readable medium that executes a step of applying the representative value to the plurality of segments having the same hash value. In a method for manufacturing a semiconductor device:
A step of generating a plurality of segments from the layout of the semiconductor device;
For each of the plurality of segments, a step of calculating a hash value using a hash function depending on a first characteristic value of each segment, a second characteristic value of at least one segment adjacent to each segment, and a third characteristic value between each segment and the at least one segment;
A step of calculating bias values for each of the plurality of segments;
A step of calculating a representative value based on bias values of a plurality of segments having the same hash value among the calculated hash values;
A step of generating a mask corrected according to the above representative value; and
A method for manufacturing a semiconductor device, comprising a step of forming patterns on a substrate using the above mask. delete delete delete delete delete delete delete delete delete delete