KR102817259B1 - Transition metal chalcogen compound based semiconductor device and method of manufacturing the same - Google Patents

Abstract

The present invention provides a semiconductor device based on a transition metal chalcogenide, which can reduce contact resistance and improve performance by separately forming an electrode body composed of a semi-metallic 1T' phase and transferring it to a channel body composed of a semi-conductive 2H phase, and a method for manufacturing the same. A method for manufacturing a semiconductor device based on a transition metal chalcogenide according to an embodiment of the present invention includes the steps of: providing a first substrate having a first layer formed on a surface thereof, the first layer including a transition metal chalcogenide compound of a first phase and having a first region and a second region; providing a second substrate having a second layer including a transition metal chalcogenide compound of a second phase formed on a surface thereof; forming a metal pattern layer on the first region of the first layer; using the metal pattern layer as a mask layer, removing the second region of the first layer exposed by the metal pattern layer to form a pattern structure; separating the pattern structure from the first substrate; and transferring the pattern structure on a portion of the second layer.

Description

Transition metal chalcogen compound based semiconductor device and method of manufacturing the same

The technical idea of the present invention relates to a semiconductor device, and more specifically, to a semiconductor device based on a transition metal chalcogen compound and a method for manufacturing the same.

Transition metal dichalcogenides are one of the next-generation semiconductor materials and are widely used in many fields such as low-power electrical devices, thermoelectric materials, display devices, hydrogen production, and photovoltaics.

As semiconductor devices are miniaturized, the size of the active layer is reduced, and the contact resistance at the metal-semiconductor contact surface within the semiconductor device becomes an important factor that determines the performance of the semiconductor device. Therefore, a technology for fabricating a device with a clean interface is required in the study of transition metal chalcogenide-based transistor devices. In the direct deposition process of three-dimensional commercial metals used to fabricate conventional silicon-based field-effect transistor devices, defects occur at the interface between the metal and the semiconductor, resulting in high contact resistance values and limitations in fabricating low-power transistor devices. Therefore, an optimized process technique is required to lower the contact resistance in transition metal chalcogenide-based transistor devices.

Korean Patent Publication No. 10-2013-0103913

The technical problem to be achieved by the technical idea of the present invention is to provide a semiconductor device based on a transition metal chalcogenide compound and a method for manufacturing the same, which can reduce contact resistance and improve performance by separately forming an electrode body composed of a semi-metallic 1T' phase and transferring it to a channel body composed of a semi-conductive 2H phase.

However, these tasks are exemplary and the technical idea of the present invention is not limited thereto.

According to the technical idea of the present invention for achieving the above technical problem, a method for manufacturing a semiconductor device based on a transition metal chalcogenide comprises the steps of: providing a first substrate having a first layer formed on a surface thereof, the first layer including a first phase transition metal chalcogenide compound and having a first region and a second region; providing a second substrate having a second layer including a second phase transition metal chalcogenide compound formed on a surface thereof; forming a metal pattern layer on the first region of the first layer; using the metal pattern layer as a mask layer, removing the second region of the first layer exposed by the metal pattern layer to form a pattern structure; separating the pattern structure from the first substrate; and transferring the pattern structure onto a portion of the second layer.

In one embodiment of the present invention, the step of providing the first substrate may include the steps of forming a first metal layer including a first transition metal on a surface of the first substrate using sputtering or electron beam evaporation; providing a chalcogen material to the first metal layer; heating the chalcogen material; and the steps of reacting the first transition metal of the first metal layer with the chalcogen material to form a chalcogenide to form a transition metal chalcogen compound of the first phase.

In one embodiment of the present invention, the step of providing the second substrate may include the steps of: providing a second substrate including a target layer having a first phase transition metal chalcogen compound including a second transition metal formed thereon; providing a seed layer having a second phase transition metal chalcogen compound including the second transition metal formed thereon; disposing the seed layer on at least a portion of the target layer; providing a chalcogen material on the target layer; heating the chalcogen material; and, as the second phase transition metal chalcogen compound of the seed layer is transferred as a seed, the first phase transition metal chalcogen compound of the target layer reacts with the chalcogen material, thereby causing the first phase transition metal chalcogen compound of the target layer to phase-change into a second phase transition metal chalcogen compound to form a phase-change layer.

In one embodiment of the present invention, the step of providing a chalcogen material to the target layer may include the step of forming a preliminary metal layer including a third transition metal on a surface of a preliminary substrate; the step of providing the chalcogen material to the preliminary metal layer and heating it to form a compound layer of the third transition metal and the chalcogen material by preliminary chalcogenization of the third transition metal; and the step of providing the compound layer as the chalcogen material.

In one embodiment of the present invention, the step of providing the chalcogen material may be accomplished by providing the chalcogen material in a solid state, a liquid state, a gaseous state, or a mixed state thereof.

In one embodiment of the present invention, the step of providing the chalcogen material can be accomplished by providing a eutectic alloy of the chalcogen material and a transition metal.

In one embodiment of the present invention, the step of heating the chalcogen material may be such that the chalcogen material is heated and vaporized, and the vaporized chalcogen material may be provided to the transition metal chalcogen compound of the first phase of the target layer by a carrier gas composed of an inert gas or a mixed gas of a hydrogen-containing gas and an inert gas.

In one embodiment of the present invention, in the step of forming the phase change layer, the phase change to the second phase transition metal chalcogen compound can be achieved by lateral epitaxial growth from the seed layer.

In one embodiment of the present invention, in the step of providing the seed layer, the seed layer can be formed by the steps of: forming a metal layer including the second transition metal on a surface of a substrate using sputtering or electron beam evaporation; providing a chalcogen material to the metal layer and heating it to a temperature in a range of from 600° C. to less than 750° C.; and reacting the metal layer with the chalcogen material to form a chalcogenide to form a transition metal chalcogen compound of the second phase.

In one embodiment of the present invention, in the step of providing the seed layer, the seed layer can be formed by performing mechanical exfoliation from a second phase transition metal chalcogenide compound mother crystal.

In one embodiment of the present invention, the step of separating the pattern structure may include the step of forming a transfer assistant to cover the pattern structure on the first substrate; the step of attaching an adhesive on the transfer assistant; and the step of separating the transfer assistant containing the pattern structure from the first substrate using the adhesive.

In one embodiment of the present invention, the step of transferring the pattern structure may include the step of arranging the transfer assistant receiving the pattern structure on the second layer of the second substrate; and the step of removing the transfer assistant so that the pattern structure remains on the second layer.

In one embodiment of the present invention, the transition metal chalcogenide compound of the first phase may have a crystal structure arranged in a 1T phase or a 1T' phase, and the transition metal chalcogenide compound of the second phase may have a crystal structure arranged in a 2H phase.

In one embodiment of the present invention, the first transition metal constituting the first phase transition metal chalcogenide compound or the second transition metal constituting the second phase transition metal chalcogenide compound may include at least one of molybdenum (Mo), tungsten (W), titanium (Ti), vanadium (V), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), yttrium (Y), zirconium (Zr), niobium (Nb), technetium (Tc), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), and cadmium (Cd).

In one embodiment of the present invention, the first chalcogen material constituting the first phase transition metal chalcogen compound or the second chalcogen material constituting the second phase transition metal chalcogen compound may include at least one of sulfur (S), selenium (Se), and tellurium (Te).

In one embodiment of the present invention, the metal pattern layer may include gold, platinum, silver, palladium, copper, aluminum, tungsten, molybdenum, titanium, ruthenium, iridium, or a combination thereof.

In one embodiment of the present invention, the transfer assistant may include at least one of polymethyl methacrylate (PMMA), polyimide, polyvinyl alcohol (PVA), acrylic, polybutadiene, polybenzoxazole, benzocyclo butene (BCB), polyphenylene benzobisoxazole (PBO), epoxy resin, and silicone resin.

In one embodiment of the present invention, the third transition metal may include at least one of scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), yttrium (Y), zirconium (Zr), niobium (Nb), molybdenum (Mo), technetium (Tc), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), and cadmium (Cd).

According to the technical idea of the present invention for achieving the above technical task, a semiconductor device based on a transition metal chalcogenide is manufactured by the method for manufacturing a semiconductor device based on a transition metal chalcogenide described above, and includes an electrode portion formed by stacking a first phase transition metal chalcogenide compound layer and a metal pattern layer; and a channel layer formed of a second phase transition metal chalcogenide compound layer and electrically connected to the electrode portion, wherein the first phase transition metal chalcogenide compound layer and the second phase transition metal chalcogenide compound layer can form a van der Waals bond.

In one embodiment of the present invention, the first phase transition metal chalcogenide compound may include 1T' MoTe ₂ , the second phase transition metal chalcogenide compound may include 2H MoTe ₂ , and the metal pattern layer may include gold.

According to a method for manufacturing a semiconductor device based on a transition metal chalcogenide compound according to the technical idea of the present invention, a seed layer including a semiconducting 2H phase transition metal chalcogenide compound is used to cause a metallic 1T' phase transition metal chalcogenide compound to undergo a phase transformation into a 2H phase transition metal chalcogenide compound at a low temperature compatible with a post-process, thereby forming a large area of a second phase transition metal chalcogenide compound having excellent crystal quality.

In addition, by separately forming an electrode body composed of a semi-metallic 1T' phase and transferring it to a channel body composed of a semi-conductive 2H phase, a semiconductor device based on a transition metal chalcogenide compound can be provided with improved performance by reducing contact resistance.

The attempt at on-chip fabrication of ultra-high quality, ultra-clean van der Waals metal semiconductor junction transistor arrays of the present invention has significant implications in realizing a minimum contact barrier for improved p-type mobility. The significance of the present invention is the low contact resistance (R _c ) of about 0.7 kΩ μm between the two-dimensional semiconductor and the two-dimensional semimetal. The R _c is the lowest value reported for p-type two-dimensional transistors with less than 10 layers based on 2H-MoTe ₂ and WSe ₂ . Therefore, by combining materials synthesis, device fabrication, and interface engineering, the present invention has significant potential to expand the scope of two-dimensional electronic device applications.

The effects of the present invention described above are described as examples, and the scope of the present invention is not limited by these effects.

FIG. 1 is a flow chart showing a method for manufacturing a semiconductor device based on a transition metal chalcogen compound according to one embodiment of the present invention.
FIG. 2 is a schematic diagram exemplifying a method for manufacturing a semiconductor device based on a transition metal chalcogen compound according to an embodiment of the present invention.
FIG. 3 is a flow chart showing a step of providing a first substrate including a first phase transition metal chalcogen compound in a method for manufacturing a semiconductor device based on a transition metal chalcogen compound according to one embodiment of the present invention.
FIG. 4 is a flow chart showing a step of providing a second substrate including a second phase transition metal chalcogen compound in a method for manufacturing a semiconductor device based on a transition metal chalcogen compound according to one embodiment of the present invention.
FIG. 5 is an optical microscope photograph showing a MoTe ₂ phase transition by a method for manufacturing a semiconductor device based on a transition metal chalcogen compound according to an embodiment of the present invention.
FIG. 6 is a scanning transmission electron microscope photograph of a seed layer and a phase change layer formed by a method for manufacturing a semiconductor device based on a transition metal chalcogen compound according to an embodiment of the present invention.
FIG. 7 is a schematic diagram showing the band structures of 1T' MoTe ₂ phase and 2H MoTe ₂ phase formed using a method for manufacturing a semiconductor device based on a transition metal chalcogen compound according to an embodiment of the present invention.
FIG. 8 is an optical microscope photograph of a semiconductor device formed by a method for manufacturing a semiconductor device based on a transition metal chalcogen compound according to an embodiment of the present invention.
FIG. 9 is a scanning transmission electron microscope photograph showing the microstructure of a semiconductor device formed by a method for manufacturing a semiconductor device based on a transition metal chalcogen compound according to an embodiment of the present invention.
FIG. 10 is a graph showing X-ray photoelectron spectra of layers constituting a semiconductor device formed by a method for manufacturing a semiconductor device based on a transition metal chalcogen compound according to an embodiment of the present invention.
FIGS. 11 to 13 are graphs showing electrical characteristics of a semiconductor device formed by a method for manufacturing a semiconductor device based on a transition metal chalcogen compound according to an embodiment of the present invention.
FIG. 14 shows the band structure of a transition metal chalcogen compound applied in a method for manufacturing a semiconductor device based on a transition metal chalcogen compound according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. The embodiments of the present invention are provided to more completely explain the technical idea of the present invention to those skilled in the art, and the following embodiments may be modified in various different forms, and the scope of the technical idea of the present invention is not limited to the following embodiments. Rather, these embodiments are provided to more faithfully and completely convey the technical idea of the present invention to those skilled in the art. Like reference numerals throughout this specification denote like elements. Furthermore, various elements and areas in the drawings are schematically drawn. Therefore, the technical idea of the present invention is not limited by the relative sizes or intervals drawn in the attached drawings.

Throughout the specification, it is noted that the term "electrically connected" includes components being in direct contact, components being in contact with each other through other components, and includes various ways in which components are electrically connected.

Extensive research is being conducted on novel transistor nanomaterials, such as two-dimensional van der Waals semiconductors. However, most two-dimensional semiconductors are n-type or bipolar, and the lack of unipolar p-type two-dimensional semiconductors limits the widespread use of CMOS inverters for energy-efficient circuits with low power-per-bit delay in two-dimensional electronic devices. Research on two-dimensional semiconductors that can be grown directly at low temperatures, below 550 °C, or easily transferred onto desired substrates and have high electrical performance is important for device fabrication targeting CMOS back-end-of-line (BEOL) compatible processes. Among transition metal dichalcogenides (TMDs), two-dimensional 2H phase molybdenum ditelluride (MoTe ₂ ) has the lowest valence band maximum energy (E _VBM ) in the range of 4.9–5.1 eV, which enables the fabrication of unipolar p-type semiconductors with suppressed electron mobility compared to other transition metal dichalcogenides. Therefore, the development of a reliable and scalable method for fabricating high-quality p-type 2H-MoTe ₂ with several layers can enable next-generation two-dimensional electronic devices for upstream and downstream processes.

However, the formation of single-crystal 2H-MoTe ₂ polymorph with 100% wafer-scale coverage by chemical vapor deposition (CVD) growth has not been achieved yet. This is because 2H-MoTe ₂ is formed only within a narrow growth window, and the uncontrolled Te flux (low equilibrium vapor pressure) during the growth hinders the polymorph control between the metallic 1T' structure and the semiconducting 2H structure due to the small free energy difference of about 35 meV per molecular weight. The partial 1T' residual products generated by CVD along with oxygen-related impurities, Te vacancies, and grain boundaries of 2H-MoTe ₂ on the surface can increase the sheet resistance of electronic devices, cause improper functioning, and thus lead to deterioration of their electrical properties. Recently, pioneering studies have been performed to synthesize 2H-MoTe ₂ using solid-solid phase transition or two-dimensional seed growth methods. However, the practical applications of these methods have limitations, such as the use of powder-based horizontal CVD or the requirement of an AlO _x passivation layer, and it is difficult to produce uniform and high-quality 2H-MoTe ₂ thin films at high speed and on a large scale. In addition, the electrical conductivity of 2H-MoTe ₂ synthesized using these methods is limited. For example, the on-state surface conductivity is less than about 10 μS, and the on-off current ratio is about 10 ⁴ . Therefore, a new growth technique is required.

When fabricating electrical contacts, the formation of interface defects such as vacancy defects, glassy layers, and alloys in 2H-MoTe ₂ -based heterojunctions can increase during the 3D metallization process due to the small electronegativity difference between Mo and Te, which further weakens the bonding. These defects cause the Fermi level (E _F ) to be pinned at a specific energy level to form a new interface state, so that the contact properties or Schottky barrier height (SBH) cannot be effectively controlled by selecting metals with different work functions. In this regard, the p-type mobility performance of conventional 2H-MoTe ₂ field-effect transistors (FETs) is mainly limited by the on/off current ratio (I _on /I _off < 10 ⁴ ), the on-state current (I _on < 1 μA/μm at V _ds = -1 V), and the field-effect hole mobility (μ _h < 10 cm ² V ^-1 s ^-1 ), even when using high-work-function three-dimensional metal contact electrodes such as Pd and Pt. Alternatively, the vdW integration of 1T'-phase MoTe ₂ as a two-dimensional polymorphic metal electrode can provide a very sharp and pristine interface in vertical 2D/2D metal-semiconductor junctions (MSJs). However, although all 2D devices require 3D contact pads, there has been no systematic study on the effect of 3D metallization on the 2D metal, which is located opposite the 2D semiconductor in 2D/2D metal-semiconductor junctions. This is very important because 2D metals are increasingly used as electronic components in all 2D circuits. For example, graphene, VSe ₂ , NbSe ₂ , etc. are relevant 2D (semi)metal materials and can be used as contact electrodes in WSe ₂ transistors. However, the work function of 2D semimetals tuned to 3D metals is often overlooked. In addition, most van der Waals-integrated 2D metals have been fabricated using irregular flakes grown mechanically or CVD-grown, which are not practical for high-yield manufacturing. In addition, significant differences in performance metrics or field-effect transistor switching polarity raise questions about the reproducibility of polymorphic junctions using 1T'-MoTe ₂ .

FIG. 1 is a flow chart showing a method for manufacturing a semiconductor device based on a transition metal chalcogen compound according to one embodiment of the present invention.

Referring to FIG. 1, a method for manufacturing a semiconductor device based on a transition metal chalcogenide (S100) includes the steps of: providing a first substrate having a first layer formed on a surface thereof, which includes a first phase transition metal chalcogenide compound and has a first region and a second region; providing a second substrate having a second layer formed on a surface thereof, which includes a second phase transition metal chalcogenide compound; forming a metal pattern layer on the first region of the first layer (S130); using the metal pattern layer as a mask layer, removing the second region of the first layer exposed by the metal pattern layer to form a pattern structure (S140); separating the pattern structure from the first substrate (S150); and transferring the pattern structure onto a portion of the second layer (S160).

The step (S110) of providing the first substrate may be performed by providing a first substrate having a first layer formed on a surface thereof, the first layer including a first phase transition metal chalcogen compound and having a first region and a second region.

The step (S120) of providing the second substrate can be performed by providing a second substrate having a second layer including a second phase transition metal chalcogen compound formed on a surface thereof.

The first substrate, the second substrate, or both of them may be configured by forming a silicon insulating layer on silicon. The silicon may be a silicon wafer. The silicon insulating layer may function as a reaction prevention film that prevents a reaction between the formed transition metal chalcogenide and the silicon. The silicon insulating layer may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the first substrate, the second substrate, or both of them may have a structure of SiO ₂ /Si in which a silicon oxide layer is formed on silicon.

Additionally, the first substrate, the second substrate, or both of them may be configured to include hexagonal boron nitride (h-BN) or mica. Additionally, the first substrate, the second substrate, or both of them may be configured as layered substrates.

The above first phase transition metal chalcogen compound may be composed of a first transition metal and a first chalcogen material. The above second phase transition metal chalcogen compound may be composed of a second transition metal and a second chalcogen material. The first transition metal and the second transition metal may be the same material or different materials. The first chalcogen material and the second chalcogen material may be the same material or different materials.

The first transition metal constituting the first phase transition metal chalcogenide compound or the second transition metal constituting the second phase transition metal chalcogenide compound may include at least one of, for example, molybdenum (Mo), tungsten (W), titanium (Ti), vanadium (V), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), yttrium (Y), zirconium (Zr), niobium (Nb), technetium (Tc), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), and cadmium (Cd). However, this is exemplary, and the first transition metal or the second transition metal may include all transition metal groups capable of forming a layered structure with chalcogen elements.

The first chalcogen material constituting the transition metal chalcogen compound of the first phase or the second chalcogen material constituting the transition metal chalcogen compound of the second phase may include, for example, at least one of sulfur (S), selenium (Se), and tellurium (Te).

The transition metal chalcogen compound of the first phase may be a crystalline compound represented by the chemical formula MX ₂ . Here, M is a transition metal, and X is a chalcogen. Alternatively, the transition metal chalcogen compound of the first phase may include a transition metal chalcogen compound having a ratio of a chalcogen element to a transition metal element of 5:1 to 1:5. When the chalcogen material is sulfur (S) or selenium (Se), the crystal structure of the transition metal chalcogen compound of the first phase may be a 1T phase. When the chalcogen material is tellurium (Te), the crystal structure of the transition metal chalcogen compound of the first phase may be a 1T' phase. The crystal structure of the 1T phase or the 1T' phase is a thermodynamically metastable state, and the transition metal chalcogen compound of the first phase strongly exhibits metallic characteristics. The above first phase transition metal chalcogen compound may have semi-metal properties.

In addition, the transition metal chalcogenide compound of the second phase may be a crystalline compound represented by the chemical formula MX ₂ . Here, M is a transition metal, and X is a chalcogen. Alternatively, the transition metal chalcogenide compound of the second phase may include a transition metal chalcogenide compound having a ratio of the transition metal element to the chalcogen element of 5:1 to 1:5. The transition metal chalcogenide compound of the second phase may have a crystal structure arranged in a 2H phase. The crystal structure of the 2H phase is a thermodynamically stable structure, and the transition metal chalcogenide compound of the second phase may strongly exhibit semiconductor properties and may have a relatively high band gap energy compared to the 1T phase or the 1T' phase.

For example, the first transition metal and the second transition metal may include molybdenum (Mo). The chalcogen material may include tellurium (Te). The transition metal chalcogen compound of the first phase may include 1T' MoTe ₂ . The transition metal chalcogen compound of the second phase may include 2H MoTe ₂ . However, this is exemplary and the technical idea of the present invention is not limited thereto.

The step (S130) of forming the metal pattern layer can be performed by forming a metal pattern layer on the first region of the first layer.

The step (S130) of forming the metal pattern layer may include forming a metal layer on the first layer by using sputtering or electron beam evaporation, and patterning the metal layer to form the metal pattern layer. The patterning may be implemented by using a photolithography method using photoresist, a lift-off method, or the like. The first region of the first layer may be overlapped and covered by the metal pattern layer, and the second region of the first layer may be exposed by the metal pattern layer. The metal pattern layer may include, for example, gold, platinum, silver, palladium, copper, aluminum, tungsten, molybdenum, titanium, ruthenium, iridium, or a combination thereof. However, this is exemplary and the technical idea of the present invention is not limited thereto.

The step (S140) of forming the pattern structure can be performed by using the metal pattern layer as a mask layer to remove the second region of the first layer exposed by the metal pattern layer to form the pattern structure.

The removal of the second region can be performed using plasma etching or reactive ion etching. The first substrate can be exposed between the metal pattern layers by the removal of the second region. Accordingly, the pattern structure composed of the first pattern layer in which the first layer is patterned and the metal pattern layer can be formed.

The step (S150) of separating the above pattern structure can be performed by separating the pattern structure from the first substrate.

The step (S150) of separating the pattern structure may include a step of forming a transfer assistant to cover the pattern structure on the first substrate; a step of attaching an adhesive on the transfer assistant; and a step of separating the transfer assistant containing the pattern structure from the first substrate using the adhesive.

The above transfer assistant may be a solid material that is hardened after coating a liquid. The above transfer assistant may be formed using at least one of spin coating, drop coating, spray coating, screen printing, offset printing, inkjet printing, and gravure printing, for example.

The above-described transcriptional assistant may include a polymer, and may include, for example, at least one of polymethyl methacrylate (PMMA), polyimide, polyvinyl alcohol (PVA), acrylic, polybutadiene, polybenzoxazole, benzocyclo butene (BCB), polyphenylene benzobisoxazole (PBO), epoxy resin, and silicone resin.

The adhesive may be composed of a material capable of temporary adhesion and detachment, and may be, for example, a solid material that is hardened after coating a liquid, or an adhesive film. The adhesive may be composed of a base film composed of PET (polyethylene terephthalate), PP (polypropylene), PE (polyethylene), PVC (polyvinyl chloride), PI (polyimide), PEN (polyethylene naphthalene), PTFE (polytetrafluoro ethylene), ETFE (ethylene terafluoroethylene), PEEK (polyether ether keton), PPS (polyphenylene sulfide), PES (polyether sulfone), or the like, and a silicone resin or acrylic resin may be applied as an adhesive.

The above adhesive may be a thermal release tape.

The step (S160) of transferring the above pattern structure can be performed by transferring the pattern structure onto a portion of the second layer.

The step (S160) of transferring the pattern structure may include a step of arranging the transfer assistant receiving the pattern structure on the second layer of the second substrate; and a step of removing the transfer assistant so that the pattern structure remains on the second layer.

In the step (S160) of transferring the pattern structure, after performing the step of arranging the transfer assistant, a step of heating at a temperature in the range of 100° C. to 200° C. for 1 minute to 30 minutes may be further included. By this heating, the second phase transition metal chalcogen compound of the second layer and the first phase transition metal chalcogen compound of the pattern structure can form a van der Waals bond. The heat dissipating tape of the adhesive can transfer heat for the van der Waals bond.

The step of removing the above-mentioned transcriptional assistant can be performed using water or an organic solvent. The organic solvent can include alcohol, acetone, or the like.

FIG. 2 is a schematic diagram exemplifying a method for manufacturing a semiconductor device based on a transition metal chalcogen compound according to an embodiment of the present invention.

Molybdenum (Mo) was selected as the first transition metal and the second transition metal, tellurium (Te) was selected as the chalcogen material, gold (Au) was selected as the material constituting the metal pattern layer, and PMMA was selected as the transfer assistant. This is exemplary, and the technical idea of the present invention is not limited thereto.

Referring to (a) of FIG. 2, a first substrate (210) composed of SiO 2 /Si is provided, on the surface of which a first layer (220) is formed, which is composed of 1T' MoTe ₂ as a first phase transition metal chalcogen compound and has a first region ( ₂₂₁ ) and a second region (222).

Referring to (b) of Fig. 2, a metal pattern layer (230) composed of gold (Au) is formed on the first region (221) of the first layer (220), and the first region (222) of the first layer (220) is exposed.

Referring to (c) of Fig. 2, the first region (222) of the exposed first layer (220) is removed using plasma etching.

Referring to (d) of Fig. 2, the first substrate (210) is exposed in the portion where the first region (222) is removed. The first pattern layer (240) in which the metal pattern layer (230) and the first layer (220) are patterned forms a pattern structure (250).

Referring to (e) of Fig. 2, a transfer auxiliary body (260) made of PMMA is formed to cover a pattern structure (250) on a first substrate (210).

Referring to (f) of FIG. 2, after attaching an adhesive on a transfer assistant (260), the transfer assistant (260) containing a pattern structure (250) is separated from the first substrate (210) using the adhesive.

Referring to (g) of FIG. 2, a second substrate (310) is provided having a second layer (320) formed on a surface thereof, which is composed of 2H MoTe ₂ as a second phase transition metal chalcogen compound. A transfer assistant (260) containing a pattern structure (250) is placed on the second layer (320). Subsequently, the entire structure is heated to cause van der Waals bonding between the 2H MoTe ₂ of the second layer (320) and the 1T' MoTe ₂ of the pattern structure (250).

Referring to (h) of Fig. 2, the transfer assistant (260) is removed using a detergent such as water or an organic solvent.

Referring to (i) of FIG. 2, the second layer (320) includes a third region (323) and a fourth region (324). A pattern structure (250) composed of a metal pattern layer (230) and a first pattern layer (240) is arranged on the third region (323). The fourth region (324) is exposed with the pattern structure (250) interposed therebetween. Accordingly, a semiconductor device based on a transition metal chalcogenide compound is completed.

In the semiconductor device based on the above transition metal chalcogenide compound, the pattern structure (250) including the first pattern layer (240) composed of 1T' MoTe ₂ and the metal pattern layer (230) located on the fourth region (324) of the second layer (320) can function as an electrode, for example, can function as a source/drain electrode. The fourth region (324) of the second layer (320) composed of 2H MoTe ₂ can function as a channel layer.

Hereinafter, a method for forming the transition metal chalcogen compound of the first phase and the transition metal chalcogen compound of the second phase will be exemplarily described.

FIG. 3 is a flow chart showing a step of providing a first substrate including a first phase transition metal chalcogen compound in a method for manufacturing a semiconductor device based on a transition metal chalcogen compound according to one embodiment of the present invention.

Referring to FIG. 3, the step of providing the first substrate (S110) may include the step of forming a first metal layer including the first transition metal on the surface of the first substrate using sputtering or electron beam evaporation (S111); the step of providing a chalcogen material to the first metal layer (S112); the step of heating the chalcogen material (S113); and the step of forming a first phase transition metal chalcogen compound by reacting the first transition metal of the first metal layer with the chalcogen material to form a chalcogenide (S114).

The step (S111) of forming the first metal layer on the surface can be performed by forming a first metal layer including the first transition metal on the surface of the first substrate using sputtering or electron beam evaporation.

The step (S112) of providing the above chalcogen material can be performed by providing the chalcogen material to the first metal layer.

The step (S112) of providing the chalcogen material may include: a step of forming a preliminary metal layer including a third transition metal on a surface of a preliminary substrate; a step of providing the chalcogen material to the preliminary metal layer and heating it to form a compound layer of the third transition metal and the chalcogen material by preliminary chalcogenization of the third transition metal; and a step of providing the compound layer as the chalcogen material. However, this This is exemplary and the technical idea of the present invention is not limited thereto.

The above preliminary chalcogenidation can be performed, for example, at a temperature in the range of 400°C to 600°C for 1 minute to 60 minutes.

The third transition metal may include at least one of, for example, scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), yttrium (Y), zirconium (Zr), niobium (Nb), molybdenum (Mo), technetium (Tc), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), and cadmium (Cd). The third transition metal may include a material that forms a eutectic alloy with the chalcogen material.

For example, the third transition metal may include nickel (Ni), the chalcogen material may include tellurium (Te), and the compound may include a nickel-tellurium eutectic alloy (Ni _x Te _y ). Here, x and y are numbers that change corresponding to the oxidation number of nickel, and the ratio between x and y may be, for example, a number in the range of 1 to 10.

The step (S112) of providing the chalcogen material can be performed by placing the chalcogen material in a reactor so that it faces the first metal layer.

The step of heating the above chalcogen material (S113) can be performed by heating the above chalcogen material.

In the step (S113) of heating the chalcogen material, the heating may be performed, for example, at a temperature in the range of 400° C. to 600° C. for a period of 1 minute to 60 minutes. By the heating, the chalcogen material and the first metal layer may be heated together.

The chalcogen material may include, for example, at least one of sulfur (S), selenium (Se), and tellurium (Te). The chalcogen material may be the same as the chalcogen material constituting the transition metal chalcogen compound of the first phase and the transition metal chalcogen compound of the second phase.

The chalcogen material may be provided in a solid state, a liquid state, a gaseous state, or a mixed state thereof. The chalcogen material may be provided, for example, as a eutectic alloy of the chalcogen material and a transition metal.

The above-described vaporized chalcogen material can be provided to the first metal layer by a carrier gas, and the carrier gas can perform a function of uniformly transferring the vaporized chalcogen material to the first metal layer.

The carrier gas may be composed of an inert gas or a mixture of a hydrogen-containing gas and an inert gas. The hydrogen-containing gas reacts with the chalcogen material to form a chalcogenide hydrogen gas, thereby enabling effective transport of the chalcogen material. The hydrogen-containing gas may include, for example, hydrogen gas and ammonia gas, or both. The inert gas may include, for example, nitrogen gas and argon gas, or both.

In the above mixed gas, the hydrogen-containing gas may be provided at a flow rate ranging from, for example, 50 sccm to 2,000 sccm, and the inert gas may be provided at a flow rate ranging from, for example, 300 sccm to 7,000 sccm. The ratio of the hydrogen-containing gas and the inert gas in the above mixed gas may be in a volume ratio ranging from 1:10 to 10:1.

The step (S114) of forming the transition metal chalcogen compound of the first phase can be performed by allowing the first metal layer to react with the chalcogen material to be chalcogenized, thereby forming the transition metal chalcogen compound of the first phase.

The first metal layer and the chalcogen material may be disposed so as to face each other or have a gap that can minimize the escape of the vaporized chalcogen material to the outside. For example, the first metal layer and the pre-metal layer may be disposed with a gap that can be minimized. Accordingly, most of the vaporized chalcogen material can reach the first metal layer and react with the transition metal chalcogen compound of the first phase, and a chalcogen deficiency phenomenon can be prevented during the reaction. This method may be referred to as a vertical tellurization process.

FIG. 4 is a flow chart showing a step of providing a second substrate including a second phase transition metal chalcogen compound in a method for manufacturing a semiconductor device based on a transition metal chalcogen compound according to one embodiment of the present invention.

Referring to FIG. 4, the step of providing the second substrate (S120) includes the steps of: providing a second substrate including a target layer on which a first phase transition metal chalcogenide compound including a second transition metal is formed (S121); providing a seed layer on which a second phase transition metal chalcogenide compound including the second transition metal is formed (S122); arranging the seed layer on at least a portion of the target layer (S123); providing a chalcogen material to the target layer (S124); heating the chalcogen material (S125); and forming a phase change layer by reacting the first phase transition metal chalcogenide compound of the target layer with the chalcogen material while the second phase transition metal chalcogenide compound of the seed layer is transferred as a seed, thereby transforming the first phase transition metal chalcogenide compound of the target layer into a second phase transition metal chalcogenide compound to form a phase change layer (S126).

The step (S121) of providing the second substrate can be performed by providing a second substrate including a target layer on which a first phase transition metal chalcogen compound including a second transition metal is formed.

The step (S122) of providing the seed layer can be performed by providing a seed layer on which a second phase transition metal chalcogen compound including the second transition metal is formed.

The step (S123) of placing the seed layer can be performed by placing the seed layer on at least a portion of the target layer.

The area of the seed layer may be small compared to the area of the target layer. The target layer and the seed layer may be arranged facing each other so as to directly contact a portion of the transition metal chalcogen compound of the first phase and a portion of the transition metal chalcogen compound of the second phase.

The step (S124) of providing the chalcogen material may be performed by providing the chalcogen material to the target layer. For example, the step (S124) of providing the chalcogen material may be performed by placing the chalcogen material in the reactor so as to face the target layer. Additionally, the chalcogen material may be placed so as to face the seed layer.

The step (S124) of providing the chalcogen material can utilize the method described with reference to FIG. 3 for providing the chalcogen material to the target layer, for example, by forming a preliminary metal layer or using a carrier gas, and therefore, for the sake of brevity, it will be omitted.

The step of heating the chalcogen material (S125) can be performed by heating the chalcogen material.

The step of heating the chalcogen material (S125) may further include a step of heating the chalcogen material to vaporize and provide it to the transition metal chalcogen compound of the first phase of the target layer. The target layer and the seed layer may be heated together by the heating. The heating may be performed at a temperature in the range of, for example, 400° C. to less than 600° C., for example, at a temperature in the range of, for example, 400° C. to 550° C., for a period of 1 minute to 4 hours. The heating may be performed by a heating unit disposed in the reactor.

The step (S126) of forming the phase change layer may be performed by forming a phase change layer by causing the transition metal chalcogen compound of the first phase of the target layer to phase-change into a transition metal chalcogen compound of the second phase as the transition metal chalcogen compound of the second phase is transferred as a seed and the transition metal chalcogen compound of the first phase of the target layer reacts with the chalcogen material.

The target layer and the chalcogen material may be disposed so as to face each other so as to contact each other, or may be disposed with a gap that can minimize the escape of the vaporized chalcogen material to the outside. For example, the target layer and the preparatory metal layer may be disposed with a gap that can be minimized. Accordingly, most of the vaporized chalcogen material can reach the target layer and react with the transition metal chalcogen compound of the first phase, and a chalcogen deficiency phenomenon can be prevented during the reaction. This method may be referred to as a vertical tellurization process.

In the step (S126) of forming the above phase change layer, the phase change to the second phase transition metal chalcogen compound can be achieved by lateral epitaxial growth from the seed layer.

The above seed layer and the above phase change layer may have a 2H MoTe ₂ phase having a (0001) aggregate structure formed equiangularly in the [0001] direction.

The above seed layer can be formed by performing mechanical exfoliation from a second phase transition metal chalcogenide compound mother crystal.

Alternatively, the seed layer may be formed in the same or similar manner as the above-described method of forming the target layer. The seed layer may be formed by: forming a metal layer including the second transition metal on a surface of a substrate using sputtering or electron beam evaporation; providing a chalcogen material to the metal layer and heating the metal layer to a temperature in a range of from 600° C. to less than 750° C.; and reacting the metal layer with the chalcogen material to form a chalcogenide to form a transition metal chalcogen compound layer of the second phase. The heating may be performed, for example, at a temperature in a range of from 400° C. to 600° C. for from 1 minute to 4 hours.

The provision of the above chalcogen material can be carried out in the same or similar manner as the method of providing the chalcogen material to the preparatory metal layer as described above. However, this is exemplary and the technical idea of the present invention is not limited thereto.

According to one embodiment of the present invention, a semiconductor device based on a transition metal chalcogenide is provided, which is manufactured by the method for manufacturing a semiconductor device based on a transition metal chalcogenide described above, and includes an electrode portion formed by stacking a first phase transition metal chalcogenide layer and a metal layer; and a channel layer formed of a second phase transition metal chalcogenide layer and electrically connected to the electrode portion, wherein the first phase transition metal chalcogenide layer and the second phase transition metal chalcogenide layer form van der Waals bonds.

In the semiconductor device based on the above transition metal chalcogenide, the first phase transition metal chalcogenide may include 1T' MoTe ₂ , the second phase transition metal chalcogenide may include 2H MoTe ₂ , and the metal layer may include gold.

Experimental example

Below, experimental examples are described to help understand the present invention. The following experimental examples are presented to help understand the invention, and the present invention is not limited to the following experimental examples.

According to the technical idea of the present invention, wafer-scale and polymorph-controlled synthesis for high-performance field-effect transistor arrays can be realized by layer-by-layer integration of semimetal 1T' MoTe ₂ and semiconductor 2H MoTe ₂ .

Preparation of transition metal chalcogenides

MoTe ₂ was selected as the transition metal chalcogen compound. Ni _x Te _y eutectic alloy was used as the tellurium source.

A nickel layer having a thickness of about 65 nm was formed on a SiO ₂ /Si substrate using DC magnetron sputtering. Then, tellurization was performed based on tellurium powder at 500° C. for 10 minutes to form a Ni _x Te _y eutectic alloy. Accordingly, a first preform in which Ni _x Te _y was formed on a SiO ₂ /Si substrate was formed.

A molybdenum (Mo) precursor layer having a thickness of 1 nm to 20 nm was formed on a SiO ₂ /Si substrate using DC magnetron sputtering. Accordingly, a second preform in which a molybdenum precursor layer was formed on the SiO ₂ /Si substrate was formed.

The first and second preforms were placed facing each other so that the Ni _x Te _y layer and the molybdenum layer faced each other, thereby forming a sandwich structure. At this time, no powder precursor was used. The sandwich structure was placed in a 4-inch quartz tube as a hot-wall furnace. The sandwich structure was heated at about 500° C. at atmospheric pressure for 1 hour, thereby forming 1T' MoTe ₂ .

The substrate on which the above 1T' MoTe ₂ was formed was used as a first substrate having a first layer including a first phase transition metal chalcogenide formed on its surface for manufacturing a semiconductor device.

In addition, the substrate on which the 1T' MoTe ₂ was formed was additionally manufactured and used as a second substrate including the 1T' MoTe ₂ target layer.

An adhesive tape was attached to a bulk MoTe ₂ mother crystal obtained from high-quality graphene, and then removed to transfer the single crystal flake onto the adhesive tape, thereby forming a mechanically exfoliated 2H MoTe ₂ seed layer.

The 2H MoTe ₂ seed layer was placed so as to face the 1T' MoTe ₂ target layer of the second substrate. Another first preform was placed on the 1T' MoTe ₂ target layer to cover the 2H MoTe ₂ seed layer, and heated at about 500° C. for 1 hour at atmospheric pressure. By this heating, tellurium from the Ni _x Te _y eutectic alloy of the first preform vaporizes to form tellurium vapor, and the tellurium vapor continuously evaporates and is fixed in the space between the first preform and the 1T' MoTe ₂ target layer, thereby phase-changing the 1T' MoTe ₂ of the 1T' MoTe ₂ target layer to form a 2H MoTe ₂ phase-change layer. In the process, a mixed gas including 100 sccm of hydrogen gas (H ₂ ) and 500 sccm of argon gas (Ar) was used as a carrier gas.

According to the present invention, tellurium is uniformly evaporated from the surface of the Ni _x Te _y process alloy and uniformly provided to molybdenum, so that a phase transition from the 1T' MoTe ₂ to the 2H MoTe ₂ can occur uniformly, which is currently limited by the conventional powder-based horizontal chemical vapor synthesis method.

Manufacturing of semiconductor devices

To fabricate the vertical 1T' MoTe ₂ /2H MoTe ₂ heterostructure, large-area growth was performed at various growth temperatures and times for each phase. For example, the formation of 1T' MoTe ₂ was performed at 500 °C for 30 min, and the formation of 2H MoTe ₂ was performed at 700 °C for 60 min.

In order to form the Au/1T' MoTe ₂ pattern structure as the above pattern structure, a gold (Au) pattern was deposited on the 1T' MoTe ₂ with a thickness of 40 nm using photolithography and an electron beam evaporator (Temescal FC-2000). In order to reduce material damage and interface deterioration during the high-energy deposition process, the deposition rate was reduced to 0.1 Å/s in an ultra-high vacuum (10 ^-9 Torr). Using the gold pattern as a mask layer, a reactive ion etching (RIE) technique of SF ₆ and O ₂ plasma was used to leave the 1T' MoTe ₂ disposed under the gold pattern and remove the exposed 1T'-MoTe ₂ to form the pattern structure. 0.4 M PMMA was coated and cured as the transfer assistant on the pattern structure, and a single-sided heat-dissipating tape was attached on the transfer assistant.

The above structure was separated from the substrate by applying a mechanical force from the side. Then, it was transferred onto the substrate on which the 2H MoTe ₂ phase was formed. Then, a weight of about 300 g was applied onto the pattern structure. Then, it was heated at about 150° C. for 5 to 10 minutes. By this heating, van der Waals (vdW) adhesion was formed between the 1T'-MoTe ₂ layer and the 2H-MoTe ₂ layer. In order to prevent the heat budget effect, heat treatment at a temperature higher than 150° C. was not performed during the transfer.

After performing the transcription, the PMMA was removed by immersing it in acetone solution (CMOS grade, J.T. Baker) for about 20 minutes and cleaned using isopropanol alcohol.

This dry transfer method enabled the formation of Au/1T' MoTe ₂ /2H MoTe ₂ junctions, and defined the channel width composed of 2H-MoTe ₂ .

Measurement of the properties of transition metal chalcogenides

X-ray diffraction patterns were acquired using an X-ray equipment (Bruker AXS D8) with a Cu K source. Atomic force microscopy images were acquired using an atomic force microscope (Bruker Dimension AFM) in tapping mode. High-resolution scanning transmission electron microscopy images, SAED patterns, and EDS were acquired with aberration correction (FEI Titan3 G2 60-300) at an acceleration voltage of 200 kV. High-resolution scanning transmission electron microscopy images were acquired using a high-angle annular dark-field (HAADF) detector with a half-angle collection in the range of 50.5 to 200 mrad. Noise in the high-resolution scanning transmission electron microscopy images was removed using a Wiener filter. Simulations of multi-slice scanning transmission electron microscopy images were performed using the commercial software TEMPAS (Total Resolution). Transmission electron microscopy images and diffraction patterns were acquired using an accelerating voltage of 200 kV (using a Tecnai G2 F20 X-Twin system). Single-crystal MoTe ₂ thin films were observed by scanning transmission electron microscopy (FEI Verios 460) and electron backscatter diffraction (EBSD) (AMTEK, Inc., Hikari).

X-ray photoelectron spectroscopy (XPS) and ultraviolet photoelectron spectroscopy (UPS) measurements were performed using a fine-focus monochromatic Al X-ray source (ESCALAB 250XI system) (Thermo Fisher, K-alpha). X-ray photoelectron spectroscopy calibration was performed by aligning the binding energy for the C 1s line at 284.5 eV.

Measurement of electrical characteristics of semiconductor devices

The electrical characterization of semiconductor devices (field-effect transistors) was performed using a low-temperature probe station (Lakeshore CRX-4K) equipped with a detector (Keithley 4200-SCS) at temperatures ranging from 138 K to 300 K and a ^high vacuum of 10 -6 torr. The back gate voltage was applied to the semiconductor devices through a 300 nm thick SiO ₂ layer on the silicon layer of the substrate.

n _2D was calculated using the following equation: n _2D = C _ox (V _g -V _th )/q, where C _ox is the capacitance of the oxide dielectric. The average device-to-device variation (C _v = σ/μ, where σ is the standard deviation and μ represents the mean) was estimated to be about 11 ± 5% for Transfer Length Method (TLM) devices. Non-uniformities of the 2D material, contact and dielectric interfaces, or localized charge impurities can cause device-to-device variation. The error bars in Fig. 4i are the regression standard errors resulting from a linear fit of the graph, scaled by the square root of the reduced chi-square statistic for at least five different sets. All statistically estimated values in the present invention are presented as 'mean ± standard deviation', excluding the fitted values ('mean ± standard error').

Results and Analysis

FIG. 5 is an optical microscope photograph showing a MoTe ₂ phase transition by a method for manufacturing a semiconductor device based on a transition metal chalcogen compound according to an embodiment of the present invention.

Figure 5 (a) shows a state in which a 2H MoTe ₂ seed layer is arranged on a 1T' MoTe ₂ target layer, and Figure 5 (b) shows a state after telluride treatment by heating at 500°C while providing tellurium. Figures 5 (c) and (d) show a state after telluride treatment by heating at 700°C in (a).

Referring to (a) and (b) of FIG. 5, when the telluride treatment was performed by heating to 500°C, an optically distinct shape appeared along the periphery of the 2H MoTe ₂ seed layer, and accordingly, it can be seen that the 1T' MoTe ₂ phase of the target layer was transformed into the 2H MoTe ₂ phase.

Referring to (c) and (d) of Fig. 5, when telluride treatment was performed by heating to 700°C, 2H MoTe ₂ was randomly formed in areas other than the periphery of the seed layer, as indicated by the arrow.

Therefore, it can be seen that when the telluride treatment is performed by heating to 500°C, the 2H MoTe ₂ phase transition layer is formed by transfer only in the peripheral area of the 2H MoTe ₂ seed layer, and the random nucleation of the 2H phase MoTe ₂ is suppressed. Therefore, when grown in a seed growth mode at a temperature of 500°C or lower, it is possible to control the synthesis location of a two-dimensional chalcogenide semiconductor having a 2H phase by accelerating the phase transition from the 1T' phase to the 2H phase. In this way, the growth in which the 2H MoTe ₂ phase preferentially nucleates and grows in the peripheral area of the seed layer and random nucleation and growth are suppressed can be referred to as "abnormal crystal growth."

According to the Raman spectrum analysis results, the Raman spectra of the 2H MoTe ₂ phase change layer after the 2H MoTe 2 seed layer and the 1T' MoTe ₂ target layer were phase changed appeared to have the same shape. Therefore, the 2H MoTe ₂ phase change layer is analyzed to be composed of the 2H MoTe ₂ phase _, similar to the 2H MoTe ₂ seed layer.

According to the inventors' previous study, when no seed layer was used, the minimum temperature for forming the 2H MoTe ₂ phase from the 1T' MoTe ₂ phase was 550°C. However, when the 2H MoTe ₂ seed layer was used, the 2H MoTe ₂ phase can be formed from the 1T' MoTe ₂ phase at a lower temperature of 500°C.

FIG. 6 is a scanning transmission electron microscope photograph of a seed layer and a phase change layer formed by a method for manufacturing a semiconductor device based on a transition metal chalcogen compound according to an embodiment of the present invention.

Referring to Fig. 6(a), an atomic-resolution high-angle annular dark-field (HAADF) image and a selected-area electron diffraction (SAED) pattern are shown for a 2H MoTe ₂ seed layer and a 2H MoTe ₂ phase transition layer after tellurization treatment by heating to 500°C. The 2H-MoTe ₂ seed layer and the 2H MoTe ₂ phase transition layer are analyzed to be composed of single crystals having the same plane. In addition, the 2H MoTe ₂ phase transition layer is analyzed to have been formed by lateral grain growth from the 2H MoTe ₂ seed layer. For reference, since the 2H MoTe ₂ phase seed layer has a larger thickness than the 2H MoTe ₂ phase transition layer, it appears as a brighter area. Analysis of the above-described selected area electron diffraction pattern shows that the 2H MoTe ₂ phase transition layer has a set of triple symmetry planes that are well aligned with the single crystal of the 2H MoTe ₂ seed layer and exhibits the same crystal orientation. This suggests that solid-state epitaxial and abnormal grain growth have occurred.

Referring to Fig. 6(b), as a comparative example, an atomic-resolution high-angle annular dark-field image and a selected area electron diffraction pattern are shown for the 1T' MoTe ₂ target layer and the 2H MoTe ₂ phase transition layer after tellurization treatment by heating at 700°C. The 1T' MoTe ₂ target layer shows a ring formation, and therefore, it is analyzed to be a polycrystal. In addition, the inner image shows the corresponding fast Fourier transform (FFT) pattern showing random arrangement between polymorphs, and therefore, the 1T' MoTe ₂ target layer and the 2H MoTe ₂ phase transition layer are analyzed to have random orientations. It is analyzed that these results are due to the phase transition caused by random nucleation and growth from the 1T' phase to the 2H phase at 700°C as described above.

According to the technical idea of the present invention, the 2H MoTe ₂ has a growth temperature of 500°C or less, and exhibits a minimum thickness in the range of 1 nm to 2 nm. Therefore, the present invention can form a 2H MoTe ₂ thin film with a relatively low growth temperature and a thin thickness. In addition, since the temperature at which the BEOL process of the present invention is possible is 550°C or less, it can be directly integrated with the post-process and performed. On the other hand, when the conventional horizontal chemical vapor deposition (CVD) method was used, it had a growth temperature of 600°C and a minimum thickness of 3 nm or more. When the conventional metalorganic chemical vapor deposition (MOCVD) method was used, it had a growth temperature of 400°C and a minimum thickness of 2 nm or more.

FIG. 7 is a schematic diagram showing the band structures of 1T' MoTe ₂ phase and 2H MoTe ₂ phase formed using a method for manufacturing a semiconductor device based on a transition metal chalcogen compound according to an embodiment of the present invention.

Referring to Fig. 7, the 1T' MoTe ₂ phase constituting the target layer has a work function (WF) of about 4.51 eV and is shown to be a semimetal with no energy band gap.

The 2H MoTe ₂ phase constituting the above phase change layer was shown to be a semiconductor with a work function (WF) of approximately 4.44 eV and an energy band gap (E _g ). This is similar to the work function (4.35 to 4.42 eV) of the 2H MoTe ₂ phase formed by conventional mechanical exfoliation.

The Fermi energy level (E _F ) of the above 2H MoTe _{2 phase} is higher than the half position of the energy band gap since the valence band offset (E _F - E _VBM ) is about 0.57 eV, which means that the 2H MoTe ₂ phase is not doped as p-type. The valence band offset showed a relatively low value compared to the 2H MoTe ₂ phase formed by conventional mechanical exfoliation, and therefore, it is predicted to be advantageous for carrier movement such as electrons or holes.

FIG. 8 is an optical microscope photograph of a semiconductor device formed by a method for manufacturing a semiconductor device based on a transition metal chalcogen compound according to an embodiment of the present invention.

Fig. 8(a) shows a field effect transistor (FET) array as a semiconductor element formed on a SiO ₂ /Si substrate having a size of 1 x 1 cm ² . Fig. 8(b) shows a transfer length method (TLM) pattern of the semiconductor element. Fig. 8(c) shows 2H MoTe ₂ arranged between Au/1T' MoTe ₂ of the semiconductor element.

Compared with recent studies on van der Waals integration using mechanically exfoliated flakes for recent 2D/2D metal-semiconductor junction field-effect transistors, the present invention enables the fabrication of field-effect transistor arrays with higher yield by combining two different types of synthetic 2D thin films. For example, the number of field-effect transistors per chip was increased by about 490%.

FIG. 9 is a scanning transmission electron microscope photograph showing the microstructure of a semiconductor device formed by a method for manufacturing a semiconductor device based on a transition metal chalcogen compound according to an embodiment of the present invention.

Referring to FIG. 9, (a) is a 1T' MoTe ₂ layer, (b) is a 2H-MoTe ₂ layer, (c) is a bonding interface between the 2H-MoTe ₂ layer and the 1T' MoTe ₂ layer, and (d) is a comparative example in which the 3D metal layer and the 2H-MoTe ₂ layer form an interface as a metal contact without the 1T' MoTe ₂ layer. The heterostructure composed of the 2H-MoTe ₂ layer and the 1T' MoTe ₂ layer exhibited a very clean and sharp interface. In addition, according to the EDS analysis, the 2H MoTe ₂ exhibited a Te/Mo of 2.14 at%, and the 1T' MoTe ₂ exhibited a Te/Mo of 2.11 at%, and no tellurium vacancies were found. Therefore, the heterostructure composed of 2H-MoTe ₂ layers and 1T' MoTe ₂ layers has excellent interface quality and no signs of degradation were observed after the device fabrication process.

FIG. 10 is a graph showing X-ray photoelectron spectra of layers constituting a semiconductor device formed by a method for manufacturing a semiconductor device based on a transition metal chalcogen compound according to an embodiment of the present invention.

Referring to Fig. 10(a) and (b), the binding energies between the metal and the 1T' MoTe ₂ phase for the Mo 3d core level and the Te 3d core level, respectively, are shown. Each peak position is indicated by a dotted line. Compared with the pristine 1T' MoTe ₂ , the binding energies of Au/1T' MoTe ₂ and Ag/1T' MoTe ₂ decreased, and those of Pt/1T' MoTe ₂ increased. It is analyzed that these changes are unrelated to the stoichiometric change and unrelated to the chemical interaction between tellurium and three-dimensional metals such as gold, silver, and platinum. It is analyzed that these changes are due to the formation of three-dimensional metals with high carrier density on the 1T' MoTe ₂ semimetal phase affecting the electronic properties, and the change in carrier mobility due to doping shifts the Fermi level. For example, the UV photoelectron driven work function of Au/1T' MoTe ₂ was found to be 5.0 eV, which is different from the work function of 4.45 eV of the as-grown layer. In addition, it was analyzed that no intermetallic compound AuTe _x or intermetallic compound AgTe _x was formed.

Referring to Fig. 10(c) and (d), the binding energy between the 2H MoTe ₂ phase and the metal or 1T' MoTe ₂ phase for the Mo 3d core level and the Te 3d core level, respectively, is shown. Compared with the pristine 1T' MoTe ₂ , the binding energy between the 2H MoTe ₂ phase and the 1T' MoTe ₂ phase showed a greater decrease than in the case of the 2H MoTe ₂ phase and the metal.

In forming a metal layer constituting an electrode layer, etc. in a semiconductor device, a two-dimensional semi-metal layer mechanically fixed by a thicker three-dimensional metal can prevent the formation of large defects such as wrinkles or cracks during the transfer process, so that the integration of the three-dimensional metal and the two-dimensional metal can ensure a high-yield process. Accordingly, a semiconductor device array can be manufactured at a high density on a centimeter-scale chip. Here, the two-dimensional metal is 1T' MoTe ₂ , and the three-dimensional metal refers to a metal formed on the 1T' MoTe ₂ , for example, gold (Au).

The manufacturing method according to the present invention has a great advantage over the existing deposition method of three-dimensional metals, such as titanium (Ti) or platinum (Pt), for forming a MoTe ₂ -based metal-semiconductor junction. Platinum (Pt) has a high work function of 5.64 eV and is expected to have high p-type mobility within the Pt contact metal-semiconductor junction, and therefore can be selected as a contact electrode. Titanium (Ti) has a work function of 4.4 eV and therefore can be applied to an n-type contact. However, due to the high-energy process for deposition and the chemical interaction with the two-dimensional MoTe ₂ , defects, such as vacancy defects, alloy formation, and glass layer formation, may occur.

Gold can be the best three-dimensional contact pad for 1T'-MoTe ₂ . It can also prevent oxidation of the underlying layers during the fabrication process. In addition, gold can introduce more charges to enhance carrier transport to the semimetal, and prevent the formation of intermetallic compounds AuTe _x or non-stoichiometric MoTe _2-x .

FIGS. 11 to 13 are graphs showing electrical characteristics of a semiconductor device formed by a method for manufacturing a semiconductor device based on a transition metal chalcogen compound according to an embodiment of the present invention.

Referring to (a) to (c) of FIG. 11, the output characteristics (I _ds - V _ds ) of a field effect transistor having a 2H MoTe ₂ channel layer according to an embodiment of the present invention are shown. As for the electrode layer in contact with the channel layer, (a) is an Au/1T' MoTe ₂ van der Waals contact electrode according to an embodiment of the present invention, (b) is a three-dimensional platinum (Pt) contact electrode, and (c) is a three-dimensional titanium (Ti) contact electrode. The Au/1T' MoTe ₂ van der Waals contact electrode exhibited excellent linearity in the output characteristics (I _ds - V _ds ), and therefore, it is analyzed that a p-type ohmic contact was achieved. On the other hand, the three-dimensional platinum (Pt) contact electrode and the three-dimensional titanium (Ti) contact electrode exhibited nonlinearity, and this is analyzed that there is a significant contact barrier at the metal-semiconductor junction interface of the three-dimensional metal and the two-dimensional semiconductor.

Referring to Fig. 11(d), the relationship of V g versus I ds measured at V _ds = -1 V for 50 field-effect transistors having a channel length of 5 μm to 9 μm and having a 2H MoTe ₂ channel _layer according to an embodiment of the present _invention . The inner figure shows a histogram of hole conduction (μ _h ) of 50 different field-effect transistors having 1T' MoTe ₂ contacts.

Referring to FIG. 11(e) and (f), histograms of the on-state current density (I on ) and on-off current ratio (I _on /I _off ) for 50 field-effect transistors having Au/1T' _{MoTe 2} contact electrodes according to an embodiment of the present invention are shown.

Referring to _FIGS . 11(d) to (f), it can be seen that the field-effect transistors according to the embodiments of the present invention have high reproducibility as p-type semiconductor devices. In addition, the field-effect transistors have an on-state current density (I _on ) of 7,820 ± 1,405 (nA/μm) at V ds = -1 V, an on-off current ratio (I _on /I _off ) at room temperature of 1.3 x 10 ⁵ , and a field-effect hole mobility (μ _h ) of 21.0 ± 3.3 cm ² V ^-1 s ^{-1 ,} which are larger values than those of previously reported semiconductor devices, and thus it is analyzed that the performance is improved.

For reference, in the graphs below, the results for the field-effect transistor according to the embodiments of the present invention are indicated as "vdW Au/1T'-MoTe ₂ " or "vdW Au/1T'".

Referring to (a) of FIG. 12, it can be seen that, compared to the case where a three-dimensional metal such as platinum (Pt) or titanium (Ti) is used, a field-effect transistor having an Au/1T' MoTe ₂ contact electrode according to an embodiment of the present invention has higher switching performance from the I _ds -V _g relationship due to the effect of a disorder-free interface.

Fig. 12(b) shows the change in the on-state current density (I _on ) when the channel length is changed in the range of 2 μm to 9 μm in the field-effect transistor according to the embodiment of the present invention, Fig. 12(c) shows the I _ds -V _g relationship at V _ds = -1 V, and Fig. 12(d) shows the I _ds -V _ds relationship at V _g = -100 V.

Referring to FIG. 12 (b) to (d), the field-effect transistor according to the embodiment of the present invention exhibited an inverse relationship in which the on-state current density (I _on ) increased as the channel length (L) decreased, and exhibited ohmic behavior. At a channel length of 2 μm, the on-state current density (I _on ) was close to about 7.8 ± 1.4 μAμm ^-1 . For reference, V _ds = -1 V. Compared to a case formed by a conventional chemical vapor deposition method or a case formed by a mechanical exfoliation method, the field-effect transistor of the present invention exhibited a higher on-state current density (I _on ) in all ranges of channel length.

Fig. 12(e) shows the on-state current density (I _on ) versus the carrier density (n _2D ) of the field-effect transistor according to an embodiment of the present invention, and Fig. 12(f) shows the field-effect hole mobility (μ _FE ) versus the number of layers.

Referring to (e) and (f) of FIG. 12, the field effect transistor according to the embodiment of the present invention and the comparative example exhibited a relatively high on-state current density (I _on ) in the carrier density (n _2D ) of the two-dimensional channel induced by the gate voltage. In addition, more effective hole movement can be implemented as it has a high field effect hole mobility (μ _FE ).

In addition, the on-state current density (I _on ) of the field-effect transistor formed according to the embodiment of the present invention was higher than that of the WSe ₂ channel layer grown by the CVD method as a comparative example, and was similar to that of the mechanically exfoliated WSe ₂ multilayer-based channel layer as another comparative example. Therefore, it can be seen that the field-effect transistor according to the embodiment of the present invention exhibits high channel conductivity. Theoretically, compared to other VI-group two-dimensional transition metal chalcogenides, 2H MoTe ₂ can behave as a better unipolar p-type channel for CMOS devices and suppress n-type mobility. This result is based on the band alignment of the valence band maximum energy (E _VBM ) with respect to the Fermi energy (E _F ) of the metal contact.

Referring to FIG. 13(a), the field-effect hole mobility (μ _h ) and the on-off current ratio (I _on /I _off ) of the field-effect transistor according to the embodiment of the present invention are shown. The field-effect transistor according to the embodiment of the present invention has a high field-effect hole mobility (μ _h ) of 5.1 ± 2.8 cm ² V ^-1 s ^-1 and a high on-off current ratio (I _on /I _off ) of 10 ⁴ or more. This is considerably superior to the mechanically exfoliated device indicated by the black circle as a comparative example, and is analyzed to be because defects related to the oxidation of MoTe ₂ do not occur. For reference, oxidation increases the off current density (I _off ) and reduces the on-off current ratio (I _on /I _off ) to 10 ³ or less.

In addition, as another comparative example, when an amorphous structure and a non-stoichiometric 2H MoTe ₂ layer were formed, the performance was almost similar to that of the field effect transistor according to the embodiment of the present invention.

Since the local residual 1T' MoTe ₂ phase within the 2H MoTe ₂ can reduce the on-off current ratio (I _on /I _off ), the channel layer needs to undergo a complete phase transformation to 2H MoTe ₂ to obtain better device performance. In addition, the abnormally grown 2H MoTe ₂ single crystal can prevent the grain boundary scattering mechanism of carriers, so that the high conductivity of the active layer can be maintained, and thus has an advantage over polycrystalline MoTe ₂ . In addition, the high hole mobility (μ _h ) of 29.5 cm ² V ^-1 s ^-1 of the six-layer 2H MoTe ₂ was found to be higher than that of the same or thicker thickness, which is analyzed to be due to the high crystal quality.

In the field-effect transistor according to the embodiment of the present invention, the 2H MoTe ₂ and 1T' MoTe ₂ phases exhibited a low sheet resistance (R _sh ) of 7.0 kΩ sq ^-1 , which is comparable to or similar to that of mechanically exfoliated specimens. This suggests that carriers were effectively injected through the semiconductor layer.

Referring to Fig. 13(b), the total resistance (RW) with respect to the channel length of the field-effect transistor according to the embodiment of the present invention is shown. It can be seen that the total resistance (RW) has a linear relationship with respect to the channel length ( _L ) with the transfer length method (TLM) pattern of the 1T' _{MoTe 2} /2H MoTe ₂ junction field-effect transistor at various gate voltages (V g ). The error bars are obtained from the average of at least five different transfer length method (TLM) patterns. Since 2R _c is obtained from the y-intercept of the graph, the contact resistance (R _c ) can be calculated.

The above-mentioned transfer length method pattern is difficult to implement by a layer-by-layer assembly method using conventional two-dimensional (semi)metallic transition metal chalcogenide flakes, so the method according to the present invention is improved in terms of size increase and reproducibility.

The inner photograph is an optical micrograph showing the transfer length method pattern of a 2H MoTe ₂ field-effect transistor with vdW Au/1T' MoTe ₂ contact electrodes according to an embodiment of the present invention, and the scale bar is 20 μm.

Referring to FIG. 13(c), the contact resistance (R _c ) according to the carrier concentration (n _2D ) induced by the applied gate voltage (V _g ) of the field effect transistor according to the embodiment of the present invention is shown. Red is the contact resistance of 1T' MoTe ₂ and 2H MoTe ₂ according to the embodiment of the present invention, blue is the contact resistance of platinum (Pt) and 2H MoTe ₂ as a comparative example, and black is the contact resistance in the case of growth by CVD as a comparative example. The main carrier was holes. At this time, the contact resistance (R _c ) of the 2H MoTe ₂ metal-semiconductor junction field effect transistor contacted with three-dimensional platinum (Pt) corresponding to the vdW Au/1T' MoTe ₂ contact according to the embodiment of the present invention was evaluated. This is because hole transport through platinum (Pt) exhibits the best characteristics among three-dimensional metal contacts. When the gate voltage (V _g ) was -100 V and the calculated carrier concentration (n _2D ) was 7.4 x 10 ¹² cm ^-2 , the Au/1T' MoTe ₂ /2H MoTe ₂ field-effect transistor according to the embodiment of the present invention exhibited a low 2R _c of about 2.4 ± 1.0 kΩ μm, which was much lower than that of the Pt/2H MoTe ₂ field-effect transistor of the comparative example, which was 660 ± 82 kΩ μm at the carrier concentration (n _2D ) of 7.8 x 10 ¹² cm ^-2 .

Since such 2R _c also includes R _c of about 0.5 kΩ μm at the 3D/2D metal pad/1T' MoTe ₂ interface, the contact resistance (R _c ) at the actual interface between the 2H MoTe ₂ semiconductor and the 1T' MoTe ₂ semimetal is analyzed to be close to 0.7 ± 0.5 kΩ μm at a carrier concentration (n _2D ) of 7.4 x 10 ¹² cm ^-2 .

Referring to FIG. 13(d), the relationship of the contact resistance (R _c ) to the sheet resistance (R _sh ) of the field effect transistor according to the embodiment of the present invention is shown. Red is Au/1T' MoTe ₂ /2H MoTe ₂ according to the embodiment of the present invention, blue is Pt/2H MoTe ₂ as a comparative example, and black is a case grown by CVD as a comparative example. For effective switching of the transistor, it is desirable that the sheet resistance (R _sh ) is high for a low contact resistance (R _c ). The field effect transistor according to the embodiment of the present invention satisfies this requirement. The field effect transistor according to the embodiment of the present invention exhibited the smallest sheet resistance (R _sh ) of 44.3 ± 2.3 kΩ sq ^-1. This result indicates that the channel exhibits higher quality, because the sheet resistance (R _sh ) exhibits a material-dependent characteristic excluding the size and contact characteristics of the device. Despite the low contact resistance (R _c ), a low on-off current ratio (I _on /I _off ) or high sheet resistance (R _sh ) are analyzed as important factors for a high-quality active layer to achieve high performance.

FIG. 14 shows the band structure of a transition metal chalcogen compound applied in a method for manufacturing a semiconductor device based on a transition metal chalcogen compound according to an embodiment of the present invention.

Referring to Fig. 14, considering the band structure, MoTe ₂ can operate as a better p-type channel than other group VI two-dimensional transition metal chalcogenides in CMOS. Typical group VI two-dimensional transition metal chalcogenides, except for MoTe ₂ , have difficulty in suppressing electron transport because their valence band maximum energy (E _VBM ) is higher than 5.0 eV. Therefore, the Schottky band height (SBH) of holes increases, which limits the hole conductivity. On the other hand, MoTe ₂ has a high valence band maximum energy (E _VBM ), so that the Schottky band height (SBH) increases the hole conductivity. In particular, the ratio of the thermionic barrier height for holes (Φ _hole ) to the thermionic barrier height for electrons (Φ _electron ) of MoTe ₂ is also the smallest among the group VI two-dimensional transition metal chalcogenides. Therefore, _MoTe2 tends to exhibit unipolar p-type, which results in smaller off-state current in p-type MOS, higher efficiency in high-to-low and low-to-high transitions, and thus lower power-delay product per bit in CMOS.

The above 2H MoTe ₂ thin film formed by seed transfer has great potential to be used in optical communication devices such as saturable absorbers, modulators, and photodetectors. In particular, a field-effect transistor using the above 2H MoTe ₂ thin film can be applied to a high-performance photodetector in the near-infrared range, which cannot be achieved with other two-dimensional transition metal dichalcogenides with a wider bandgap. The photosensitivity of the transistor can be improved by the optical gating effect under the near-infrared. In addition, the asymmetric contact barrier formed by using different emission-source electrodes can further improve the rectification ratio. The 1T'-MoTe ₂ with the controlled Fermi level can provide an efficient van der Waals contact for hole transport, and a fast photoresponse can be secured because of less charge trapping at the metal-semiconductor junction interface.

The difference in grain size between the above 1T' MoTe ₂ phase and the 2H MoTe ₂ phase is analyzed to be about 1000 times or more. This difference in grain size is analyzed to have occurred through recrystallization and atomic rearrangement during the phase transition from the 1T' MoTe ₂ phase to the 2H MoTe ₂ phase during growth. For example, some of the junctions between the 1T' MoTe ₂ phase and the 2H MoTe ₂ phase share an atomic orientation with the [2-1-10] _2H //[020] _1T' interface, which may be the energetically most favorable interface for the phase transition. However, not all in-plane junctions of the 1T' MoTe ₂ phase and the 2H MoTe ₂ phase exhibit similar orientations.

It means that the growth mode of 2H MoTe ₂ phase according to the present invention can help to overcome the energy barrier of arranging random crystallographic orientation of polycrystals, resulting in grain growth of 2H-MoTe ₂ . This can be generally referred to as "abnormal grain growth", in contrast to "normal grain growth" where the formation of single crystals exhibits a relatively uniform grain size distribution.

Previous studies on MoTe ₂ synthesis have shown that the amount of tellurium is an important factor in determining the MoTe ₂ phase during growth. When a large amount of tellurium is present, the 2H MoTe ₂ phase is thermodynamically stable. However, a lack of tellurium leads to the formation of nonstoichiometric MoTe _2-x , which can lead to the formation of metastable 1T' MoTe ₂ phase.

The tellurium-limited growth method according to the present invention can promote uniform growth and abnormal grain growth of 2H MoTe ₂ phase across the wafer by providing a constant and significant amount of tellurium vapor flow to the molybdenum precursor. This is in contrast to tellurium sources using powder-based horizontal CVD in which tellurium is supplied non-uniformly horizontally, which inevitably leads to a compositional gradient across the substrate and limits growth scaling.

According to the technical idea of the present invention, phase-controlled growth and position-controlled growth of 2H MoTe ₂ single crystals and three-dimensional metal-assisted Werner Waals (vdW) integration of two polymorphs were implemented to fabricate large-area high-performance p-type metal-semiconductor junction field-effect transistor (MSJ FET) arrays.

An atmosphere sufficiently supplying tellurium promoted the synthesis of high-quality _MoTe2 and enabled the phase transition from 1T' _MoTe2 to 2H _MoTe2 . Here, the 2H _MoTe2 single-crystal domain was able to cover a 4-inch _SiO2 /Si wafer through abnormal grain growth. This growth technique could be extended to form large-sized two-layer _MoTe2 thin films of about 20 mm without noticeable microcavities or impurities, which were the thinnest films attainable using the CVD mode with a size of several meters. In addition, the energetically favorable spatial arrangement of the 2H _MoTe2 seed layer enabled the lateral solid-state epitaxy of single-crystal 2H _MoTe2 patterns, which enabled the controllable crystal orientation of the two-dimensional semiconductor on all amorphous substrates at a low temperature of about 500°C.

Furthermore, high-performance van der Waals (vdW) integrated MOSFET arrays were fabricated via standard photolithography patterning and transfer of the two-dimensional 1T' MoTe ₂ structure onto which the three-dimensional metal was deposited. Compared with the conventional ones, the single-crystal 2H MoTe ₂ MOSFETs in the present invention exhibited better performance in terms of I _on /I _off of about 1.3 x 10 ⁵ and μ _h of about 29.5 cm ² V ^-1 s ^-1 . The considerably high on-state conductivity (i.e., I _on is about 7.8 μA μm ^-1 ) is attributed to the high crystallinity of MoTe ₂ , i.e., the absence of oxides, metallic impurities, and amorphous or non-stoichiometric structures.

Furthermore, the formation of an ultraclean and atomically precise interface between the 1T' MoTe ₂ and 2H MoTe ₂ prevented the formation of gap states and formed an interface without Fermi level pinning (FLP). Through this, the height of the thermionic emission barrier can be controlled based on the electronic states of various 3D metals on the 2D semimetal. For example, the metallization of the 1T' MoTe ₂ semimetal with gold provided a high work function value of the van der Waals metal electrode, about 5.0 eV, and significantly suppressed the barrier height for hole transport at the contact interface, that is, about 14 meV at V _FB .

Considering the relative ease of forming n-type two-dimensional transistors, the present invention represents a significant advance toward the scalable fabrication of p-type two-dimensional transistors with enhanced hole mobility. For example, two-dimensional semiconductors are vulnerable to external n-type doping by chalcogen vacancies and dielectric layers, but the present approach may help to avoid this.

The synthesis of p-type two-dimensional selenide and telluride often requires a high growth temperature of about 700°C or higher. This is because selenium (Se) and tellurium (Te) have lower vapor pressures than sulfur (S). Accordingly, they can deteriorate the quality of two-dimensional channels and form chalcogen vacancies due to heat. The vacancies of selenium (Se) and tellurium (Te) are considered as n-type dopants in two-dimensional chalcogenides, and can cause Fermi level pinning (FLP) near the conduction band when two-dimensional semiconductors come into contact with metal electrodes. In addition, widely used dielectric layers such as silicon oxide (SiO ₂ ) and aluminum oxide (AlO _x ) can cause n-doping of the two-dimensional active layer. In this respect, the present invention can prevent undesired n-type doping effects by growing high-quality two-dimensional single crystal semiconductors on random amorphous substrates at a low temperature of about 500°C.

In addition, conventional p-type high work function 3D metal electrodes, for example, Au, Pt, and Pd, have high melting points of 1064°C to 1768°C, which require high energy deposition processes, which may damage the 2D metal-semiconductor junction interface and increase the contact resistance (R _c ). This is in contrast to indium (In) or bismuth (Bi) for n-type ohmic metal contacts of MoS ₂ , which have low melting points of 157°C to 271°C, which create defect-free contact interfaces.

Therefore, the attempt to fabricate on-chip ultra-high quality, ultra-clean van der Waals metal semiconductor junction transistor arrays of the present invention is significant in implementing a minimum contact barrier for improved p-type mobility. The significance of the present invention is that it has a low contact resistance (R _c ) of about 0.7 kΩ μm between the two-dimensional semiconductor and the two-dimensional semimetal. Here, the contact resistance (R _c ) is obtained by excluding the R _c of the three-dimensional metal/two-dimensional semimetal. The contact resistance (R _c ) is the lowest value in p-type two-dimensional transistors with less than 10 layers based on 2H-MoTe ₂ and WSe ₂ . Therefore, by combining material synthesis, device fabrication and interface engineering, the present invention has significant potential to expand the scope of two-dimensional electronic device applications.

It will be apparent to a person skilled in the art that the technical idea of the present invention described above is not limited to the above-described embodiments and the attached drawings, and that various substitutions, modifications, and changes are possible within a scope that does not depart from the technical idea of the present invention.

Claims (20)

A step of providing a first substrate having a first layer formed on a surface thereof, the first layer comprising a first phase transition metal chalcogen compound and having a first region and a second region;
A step of providing a second substrate having a second layer formed on a surface thereof, the second layer comprising a second phase transition metal chalcogen compound;
A step of forming a metal pattern layer on the first region of the first layer;
A step of forming the first layer as a first pattern layer by using the metal pattern layer as a mask layer and removing the second area of the first layer exposed by the metal pattern layer, thereby forming a pattern structure having a structure in which the first pattern layer and the metal pattern layer are laminated;
a step of separating the pattern structure from the first substrate; and
Comprising a step of transferring the pattern structure onto a portion of the second layer;
A method for manufacturing a semiconductor device based on a transition metal chalcogen compound. In claim 1,
The step of providing the first substrate comprises:
A step of forming a first metal layer including a first transition metal on the surface of the first substrate using sputtering or electron beam evaporation;
A step of providing a chalcogen material to the first metal layer;
a step of heating the above chalcogen material; and
A step of forming a transition metal chalcogen compound of the first phase by reacting the first transition metal of the first metal layer with the chalcogen material to form a chalcogenide.
A method for manufacturing a semiconductor device based on a transition metal chalcogen compound. In claim 1,
The step of providing the second substrate is:
A step of providing a second substrate including a target layer formed with a first phase transition metal chalcogenide compound including a second transition metal;
A seed layer arrangement step of arranging a seed layer formed with a second phase transition metal chalcogen compound including the second transition metal so as to face at least a portion of the target layer;
A step of providing a chalcogen material so as to face the target layer;
a step of heating the above chalcogen material; and
A step of forming a phase change layer by transferring the second phase transition metal chalcogen compound of the seed layer as a seed, and the first phase transition metal chalcogen compound of the target layer reacts with the chalcogen material, thereby causing the first phase transition metal chalcogen compound of the target layer to phase change into the second phase transition metal chalcogen compound.
A method for manufacturing a semiconductor device based on a transition metal chalcogen compound. In claim 3,
The step of providing a chalcogen material to the above target layer is:
A step of forming a preliminary metal layer including a third transition metal on a surface of a preliminary substrate;
A step of providing the chalcogen material to the above preparatory metal layer and forming a compound layer of the third transition metal and the chalcogen material by heating the third transition metal by preparatory chalcogenidation; and
Comprising a step of providing the compound layer as the chalcogen material,
A method for manufacturing a semiconductor device based on a transition metal chalcogen compound. In claim 3,
The step of providing the above chalcogen material is:
The above chalcogen material is provided in a solid state, a liquid state, a gaseous state, or a mixed state thereof.
A method for manufacturing a semiconductor device based on a transition metal chalcogen compound. In claim 3,
The step of providing the above chalcogen material is:
It is made by providing a process alloy of the above chalcogen material and a transition metal.
A method for manufacturing a semiconductor device based on a transition metal chalcogen compound. In claim 3,
The step of heating the above chalcogen material is:
The above chalcogen material is heated and vaporized,
The above-mentioned vaporized chalcogen material is provided to the transition metal chalcogen compound of the first phase of the target layer by a carrier gas composed of an inert gas or a mixed gas of a hydrogen-containing gas and an inert gas.
A method for manufacturing a semiconductor device based on a transition metal chalcogen compound. In claim 3,
In the step of forming the above-mentioned phase change layer,
The phase transition to the second phase transition metal chalcogenide compound is achieved by lateral epitaxial growth from the seed layer.
A method for manufacturing a semiconductor device based on a transition metal chalcogen compound. In claim 3,
In the above seed layer placement step,
The above seed layer is,
A step of forming a metal layer including the second transition metal on the surface of a third substrate using sputtering or electron beam evaporation;
A step of providing a chalcogen material to the metal layer and heating it to a temperature in the range of 600°C to less than 750°C; and
The metal layer is formed by a step of reacting with the chalcogen material to form a chalcogenide, thereby forming a transition metal chalcogen compound of the second phase.
A method for manufacturing a semiconductor device based on a transition metal chalcogen compound. In claim 3,
In the step of providing the seed layer,
The above seed layer is formed by performing mechanical exfoliation from a second phase transition metal chalcogen compound mother crystal.
A method for manufacturing a semiconductor device based on a transition metal chalcogen compound. In claim 1,
The step of separating the above pattern structure is:
A step of forming a transfer assistant to cover the pattern structure on the first substrate; A step of attaching an adhesive on the transfer assistant; and
A step of separating the transfer assistant containing the pattern structure from the first substrate using the adhesive,
A method for manufacturing a semiconductor device based on a transition metal chalcogen compound. In claim 11,
The step of transferring the above pattern structure is:
A step of placing the transfer assistant body containing the pattern structure on the second layer of the second substrate; and
A step of removing the transfer assistant so that the pattern structure remains on the second layer,
A method for manufacturing a semiconductor device based on a transition metal chalcogen compound. In claim 12,
After performing the step of placing the above warrior auxiliary body,
By heating to a temperature in the range of 100°C to 200°C, the transition metal chalcogen compound of the second phase of the second layer and the transition metal chalcogen compound of the first phase of the pattern structure form a van der Waals bond.
A method for manufacturing a semiconductor device based on a transition metal chalcogen compound. In claim 1,
The above first phase transition metal chalcogen compound has a crystal structure arranged in a 1T phase or a 1T' phase,
The above second phase transition metal chalcogen compound has a crystal structure arranged in a 2H phase.
A method for manufacturing a semiconductor device based on a transition metal chalcogen compound. In claim 1,
The first transition metal constituting the transition metal chalcogenide compound of the first phase or the second transition metal constituting the transition metal chalcogenide compound of the second phase includes at least one of molybdenum (Mo), tungsten (W), titanium (Ti), vanadium (V), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), yttrium (Y), zirconium (Zr), niobium (Nb), technetium (Tc), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), and cadmium (Cd).
The first chalcogen material constituting the transition metal chalcogen compound of the first phase or the second chalcogen material constituting the transition metal chalcogen compound of the second phase contains at least one of sulfur (S), selenium (Se) and tellurium (Te).
A method for manufacturing a semiconductor device based on a transition metal chalcogen compound. In claim 1,
The above metal pattern layer comprises gold, platinum, silver, palladium, copper, aluminum, tungsten, molybdenum, titanium, ruthenium, iridium, or a combination thereof.
A method for manufacturing a semiconductor device based on a transition metal chalcogen compound. In claim 11,
The above-mentioned transfer assistant comprises at least one of polymethyl methacrylate (PMMA), polyimide, polyvinyl alcohol (PVA), acrylic, polybutadiene, polybenzoxazole, benzocyclo butene (BCB), polyphenylene benzobisoxazole (PBO), epoxy resin, and silicone resin.
A method for manufacturing a semiconductor device based on a transition metal chalcogen compound. In claim 4,
The third transition metal comprises at least one of scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), yttrium (Y), zirconium (Zr), niobium (Nb), molybdenum (Mo), technetium (Tc), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), and cadmium (Cd).
A method for manufacturing a semiconductor device based on a transition metal chalcogen compound. An electrode part formed by laminating a first phase transition metal chalcogen compound layer and a metal pattern layer; and
A second phase transition metal chalcogenide compound layer is formed, and a channel layer electrically connected to the electrode portion is included.
The first phase transition metal chalcogen compound layer and the second phase transition metal chalcogen compound layer form van der Waals bonds.
Semiconductor devices based on transition metal chalcogenide compounds. In claim 19,
The above first phase transition metal chalcogen compound comprises 1T' MoTe ₂ ,
The above second phase transition metal chalcogen compound comprises 2H MoTe ₂ ,
The above metal pattern layer comprises gold,
Semiconductor devices based on transition metal chalcogenide compounds.