KR102816863B1 - Methods of manufacturing a vertical memory device - Google Patents

Abstract

In a method for manufacturing a vertical memory device, an insulating film and a sacrificial film can be alternately and repeatedly formed on a substrate to form a mold. A channel hole penetrating the mold can be formed. A channel can be formed in the channel hole. An opening penetrating the mold can be formed. The sacrificial films can be removed through the opening to form gaps. The method may include forming gate electrodes in the gaps, respectively. Each of the sacrificial films can include silicon nitride doped with hydrogen (H), oxygen (O), and carbon (C). Concentrations of hydrogen, oxygen, and carbon doped in sacrificial films formed in an upper layer among the sacrificial films can be different from concentrations of hydrogen, oxygen, and carbon doped in sacrificial films formed in a lower layer among the sacrificial films.

Description

{METHODS OF MANUFACTURING A VERTICAL MEMORY DEVICE}

The present invention relates to a method for manufacturing a vertical memory device.

Recently, as data usage has increased dramatically in various technological fields, the demand for VNAND flash memory capable of storing large amounts of data has increased. Accordingly, the number of insulating and sacrificial layers included in a mold may increase in order to increase the storage capacity of a VNAND flash memory device. However, as the number of insulating and sacrificial layers increases, it may be difficult to form channel holes and openings that penetrate them and expose the upper surface of the substrate.

The object of the present invention is to provide a method for manufacturing a vertical memory device having improved characteristics.

In order to achieve the above-described object of the present invention, in a method for manufacturing a vertical memory device according to exemplary embodiments, an insulating film and a sacrificial film may be alternately and repeatedly formed on a substrate to form a mold. A channel hole penetrating the mold may be formed. A channel may be formed in the channel hole. An opening penetrating the mold may be formed. The sacrificial films may be removed through the opening to form gaps. The method may include forming gate electrodes in the gaps, respectively. Each of the sacrificial films may include silicon nitride doped with hydrogen (H), oxygen (O), and carbon (C). The concentrations of hydrogen, oxygen, and carbon doped in the sacrificial films formed in an upper layer among the sacrificial films may be different from the concentrations of hydrogen, oxygen, and carbon doped in the sacrificial films formed in a lower layer among the sacrificial films.

In order to achieve the above-described object of the present invention, in a method for manufacturing a vertical memory device according to other exemplary embodiments, an insulating film and a sacrificial film may be alternately and repeatedly formed on a substrate to form a mold including insulating films and sacrificial films respectively formed in a plurality of layers. A channel hole penetrating the mold may be formed. A channel may be formed in the channel hole. An opening penetrating the mold may be formed. The sacrificial films may be removed through the opening to form gaps. The method may include forming gate electrodes respectively in the gaps. Each of the sacrificial films may include silicon nitride doped with impurities including hydrogen (H), oxygen (O), and carbon (C). Concentrations of the impurities doped in the sacrificial films respectively formed in at least two or more layers among the sacrificial films may be different from each other.

In a method for manufacturing a vertical memory device according to exemplary embodiments, by doping impurities such as hydrogen, oxygen, and carbon into sacrificial films forming a mold formed on a substrate and appropriately controlling the doping concentration of each of the impurities, each channel hole and opening formed to penetrate the mold and expose an upper surface of the substrate can have a constant width along a vertical direction, thereby preventing a defect in which they do not expose the upper surface of the substrate.

FIGS. 1 to 5, 8 to 12, and 15 to 19 are plan views and cross-sectional views for explaining steps of a method for manufacturing a vertical memory device according to exemplary embodiments, and FIGS. 6 to 7 and 13 to 14 are cross-sectional views for explaining steps of a method for manufacturing a vertical memory device according to a comparative example.

Hereinafter, a vertical memory device and a manufacturing method thereof according to exemplary embodiments will be described in detail with reference to the attached drawings. Hereinafter, a direction perpendicular to a top surface of a substrate is defined as a first direction, and two directions parallel to the top surface of the substrate and intersecting each other are defined as second and third directions, respectively. In exemplary embodiments, the second and third directions may be orthogonal to each other.

FIGS. 1 to 5, 8 to 12, and 15 to 19 are plan views and cross-sectional views for explaining steps of a method for manufacturing a vertical memory device according to exemplary embodiments, and FIGS. 6 to 7 and 13 to 14 are cross-sectional views for explaining steps of a method for manufacturing a vertical memory device according to a comparative example.

Specifically, FIGS. 1, 4, 8, 11, and 18 are plan views, and FIGS. 2-3, 5, 9-10, 12, 15-17, and 19 are cross-sectional views taken along the line A-A' of the corresponding plan views, respectively. At this time, FIG. 3 is a conceptual diagram explaining the formation of a sacrificial film doped with hydrogen (H), oxygen (O), and carbon (C), and FIG. 10 is an enlarged cross-sectional view of the X region of FIG. 9. Meanwhile, FIGS. 6-7 and FIGS. 13-14 are also cross-sectional views taken along the line A-A' of the corresponding plan views, respectively.

Referring to FIGS. 1 to 3, a mold can be formed by alternately and repeatedly forming an insulating film (110) and a sacrificial film (120) on a substrate (100).

The substrate (100) may include a semiconductor material such as silicon, germanium, silicon-germanium, or a III-V group compound such as GaP, GaAs, GaSb, etc. According to some embodiments, the substrate (100) may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

The insulating film (110) and the sacrificial film (120) can be formed, for example, through a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition (ALD) process, etc.

The insulating film (110) may include an oxide such as silicon oxide, for example.

The sacrificial film (120) may include, for example, silicon nitride doped with impurities such as hydrogen, oxygen, and carbon.

In exemplary embodiments, the sacrificial film (120) may be formed to include silicon nitride by performing a deposition process using a silicon source gas and a nitrogen source gas, and then the sacrificial film (120) including the silicon nitride may be formed to include silicon nitride doped with an impurity by, for example, doping the impurity into the sacrificial film (120) including the silicon nitride through an ion implantation process.

Alternatively, the sacrificial film (120) may be formed to include silicon nitride doped with the impurities by supplying impurity source gases, such as hydrogen source gas, oxygen source gas, and carbon source gas, together while performing a deposition process using silicon source gas and nitrogen source gas.

When performing the above ion implantation process or supplying the impurity source gas, the impurity concentration doped into each of the sacrificial films (120) may vary. Accordingly, the impurity concentrations, i.e., the hydrogen concentration, the oxygen concentration, and the carbon concentration, of the sacrificial films (120) formed in at least two layers among the sacrificial films (120) formed in each of the plurality of layers may be different from each other.

In exemplary embodiments, the concentrations of hydrogen, oxygen, and carbon doped in the sacrificial films (120) formed in the upper layer among the sacrificial films (120) may be different from the concentrations of hydrogen, oxygen, and carbon doped in the sacrificial films (120) formed in the lower layer among the sacrificial films (120).

In exemplary embodiments, the concentration of the impurity doped into the sacrificial films (120) may gradually decrease from a lower layer to an upper layer. Accordingly, each of the hydrogen concentration, oxygen concentration, and carbon concentration doped into the sacrificial films (120) may gradually decrease from a lower layer to an upper layer.

In exemplary embodiments, the carbon concentration within each of the sacrificial films (120) may be lower than the hydrogen concentration and the oxygen concentration.

Referring to FIGS. 4 and 5, after forming a first interlayer insulating film (130) on the top insulating film (110), a channel hole (140) that penetrates the first interlayer insulating film (130) and the mold to expose the upper surface of the substrate (100) can be formed. At this time, the channel hole (140) may be formed to penetrate up to a portion of the upper portion of the substrate (100).

The first interlayer insulating film (130) may include an oxide such as silicon oxide, for example.

The channel hole (140) can be formed, for example, through a dry etching process.

The above dry etching process can be performed using an etching gas containing, for example, hydrofluoric acid (HF).

FIGS. 6 and 7 are cross-sectional views illustrating a dry etching process for forming a channel hole (140) in a comparative example having a sacrificial film (120) including silicon nitride that is not doped with hydrogen, oxygen, and carbon.

Referring to FIGS. 6 and 7, in the dry etching process, the etching speed of the sacrificial film (120) including silicon nitride that is not doped with hydrogen and oxygen may be slower than the etching speed of the insulating film (110) including silicon oxide, and a polymer including, for example, carbon-nitrogen may be generated on the inner wall of the channel hole (140). Accordingly, the width of the channel hole (140) may decrease from the top to the bottom of the mold or may locally increase or decrease, so that the channel hole (140) may be formed so as not to expose the upper surface of the substrate (100).

On the other hand, referring back to FIGS. 4 and 5, in the exemplary embodiment, as the dry etching process is performed, hydrogen, oxygen, and carbon doped in the sacrificial film (120) may be discharged. The discharged hydrogen may increase the etching rate, and the discharged oxygen may oxidize the polymer formed on the inner wall of the channel hole (140) to suppress its production. Accordingly, the width of the channel hole (140) may be suppressed from decreasing at the lower portion of the mold, and the channel hole (140) may be formed to have a uniform width at the upper and lower portions of the mold.

In particular, as described above, since the concentrations of the impurities doped in the sacrificial films (120), i.e., the concentrations of hydrogen, oxygen, and carbon, can gradually increase from the upper layer to the lower layer, the phenomenon in which the width of the channel hole (140) gradually decreases from the upper layer to the lower layer of the mold can be effectively suppressed.

In exemplary embodiments, after forming the channel hole (140), a cleaning process for the channel hole (140) may be additionally performed. The cleaning process may be performed, for example, through a wet etching process using an etchant containing hydrofluoric acid (HF).

As the above wet etching process is performed, hydrogen, oxygen, and carbon doped in the sacrificial film (120) may also be discharged, and the discharged hydrogen and oxygen may react with the etchant to increase the etching rate. As a result, the sacrificial film (120) may be over-etched, but the discharged carbon may play a role in preventing this. To this end, the carbon concentration doped in each of the sacrificial films (120) may be adjusted to have an appropriate value corresponding to the hydrogen concentration and oxygen concentration doped therein.

In exemplary embodiments, a plurality of channel holes (140) may be formed along each of the second and third directions, thereby defining a channel hole array.

Referring to FIGS. 8 to 10, a charge storage structure film and a channel film are sequentially formed along a sidewall of a channel hole (140), an upper surface of the exposed substrate (100), and an upper surface of a first interlayer insulating film (130), and a filling film is formed to fill the remaining portion of the channel hole (140), and then the filling film, the channel film, and the charge storage structure film can be flattened until the upper surface of the first interlayer insulating film (130) is exposed, and thus a charge storage structure (165), a channel (175), and a filling pattern (185) can be sequentially formed within the channel hole (140).

In exemplary embodiments, the planarization process may be performed via a chemical mechanical polishing (CMP) process and/or an etch back process.

The charge storage structure film may include a first blocking film, a charge storage film, and a tunnel insulating film sequentially laminated from a sidewall of a channel hole (140), and accordingly, the charge storage structure (165) may include a first blocking pattern (162), a charge storage pattern (163), and a tunnel insulating pattern (164) sequentially laminated.

The first blocking pattern (162) may include an oxide, such as silicon oxide, for example, the charge storage pattern (163) may include a nitride, such as silicon nitride, for example, and the tunnel insulating pattern (164) may include an oxide, such as silicon oxide, for example.

The channel film may include, for example, polysilicon or amorphous silicon that is doped or undoped with impurities. However, after forming the channel film, it may be converted into single-crystal silicon or polysilicon by heat treatment or laser beam irradiation, and thus the channel (175) may include crystalline silicon. In addition, the filling pattern (185) may include, for example, an insulating material such as silicon oxide or silicon nitride.

In exemplary embodiments, each charge storage structure (165) and channel (175) may have a cup shape, and the filling pattern (185) may have a pillar shape. According to other embodiments, the channel (175) may have a pillar shape that completely fills the inside of the channel hole (140), in which case the formation of the filling pattern (185) may be omitted.

Thereafter, a recess is formed by removing the upper portion of the charging pattern (185) and the channel (175), and a capping film filling the recess is formed on the charge storage structure (165) and the first interlayer insulating film (130), and then the capping film is planarized until the upper surface of the first interlayer insulating film (130) is exposed, thereby forming a capping pattern (190) inside the recess. The capping pattern (190) may include, for example, polysilicon doped with impurities.

Referring to FIGS. 11 and 12, after forming a second interlayer insulating film (200) on the first interlayer insulating film (130) and the capping pattern (190), an opening (210) may be formed to penetrate the second interlayer insulating film (200) and the mold to expose the upper surface of the substrate (100). At this time, the opening (210) may be formed to penetrate up to a portion of the upper portion of the substrate (100).

The second interlayer insulating film (200) may include an oxide such as silicon oxide, for example.

The formation of the opening (210) may be substantially the same as or similar to the process of forming the channel hole (140) described with reference to FIGS. 4 and 5. Accordingly, the opening (210) may be formed, for example, through a dry etching process using an etching gas including hydrofluoric acid (HF), and after the dry etching process, a process of cleaning the opening (210) through, for example, a wet etching process may be additionally performed.

As described above, during the dry etching process for forming the opening (210), hydrogen and oxygen doped in the sacrificial film (120) can be discharged to increase the etching speed of the sacrificial film (120). In particular, the concentration of hydrogen and oxygen doped in the sacrificial films (120) respectively formed in a plurality of layers can gradually increase from the upper layer to the lower layer within the mold, thereby effectively preventing the phenomenon in which the width of the opening (210) gradually decreases from the upper layer to the lower layer. Meanwhile, during the cleaning process for the opening (210), carbon doped in the sacrificial film (120) can prevent over-etching due to hydrogen and oxygen discharge.

FIGS. 13 and 14 are cross-sectional views illustrating a dry etching process for forming an opening (210) in a comparative example having a sacrificial film (120) including silicon nitride that is not doped with hydrogen, oxygen, and carbon.

Referring to FIGS. 13 and 14, as described with reference to FIGS. 6 and 7, in the dry etching process, the etching speed of the sacrificial film (120) including silicon nitride that is not doped with hydrogen and oxygen may be slower than the etching speed of the insulating film (110) including silicon oxide, and a polymer including, for example, carbon-nitrogen may be generated on the inner wall of the channel hole (140). Accordingly, the width of the opening (210) may decrease from the top to the bottom of the mold or may locally increase or decrease, so that the opening (210) may be formed so as not to expose the upper surface of the substrate (100).

In exemplary embodiments, the opening (210) may extend in the second direction and may be formed in multiple numbers along the third direction. As the opening (210) is formed, the insulating film (110) may be separated into insulating patterns (115) extending in the second direction, and the sacrificial film (120) may be separated into sacrificial patterns (125) extending in the second direction.

Referring to FIG. 15, by removing the sacrificial patterns (125) exposed by the opening (210), a gap (220) can be formed between the insulating patterns (115) formed in each layer, and a part of the outer wall of the first blocking pattern (162) included in the charge storage structure (165) can be exposed by the gap (220).

According to exemplary embodiments, the sacrificial patterns (125) can be removed through a wet etching process using an etchant containing phosphoric acid or sulfuric acid.

Referring to FIG. 16, a second blocking film (240) may be formed on the outer wall of the exposed first blocking pattern (165), the inner wall of the gaps (220), the surface of the insulating patterns (115), the upper surface of the substrate (100), the side wall of the first interlayer insulating film (130), and the side wall and upper surface of the second interlayer insulating film (200), and a gate electrode film may be formed on the second blocking film (240).

The second blocking film (240) may include, for example, a metal oxide such as aluminum oxide. The gate electrode film may include a gate barrier film and a gate conductive film that are sequentially laminated. The gate electrode film may include, for example, a metal having low electrical resistance such as tungsten, titanium, tantalum, or platinum, and the gate barrier film may include, for example, a metal nitride such as titanium nitride or tantalum nitride.

Thereafter, by partially removing the gate electrode film, a gate electrode can be formed inside each of the gaps (220). According to exemplary embodiments, the gate electrode film can be partially removed through a wet etching process, and the gate electrode thus formed can be formed to fill part or all of each of the gaps (220).

The above gate electrodes may extend in the second direction and may be formed in multiple pieces along the third direction. That is, the gate electrodes extending in the second direction may be spaced apart from each other by the opening (210).

In exemplary embodiments, the gate electrode may be formed in a plurality of layers spaced apart from each other along the first direction, and the gate electrodes formed in the plurality of layers may form a gate electrode structure. The gate electrode structure may include one or more first gate electrodes (232), a plurality of second gate electrodes (234), and one or more third gate electrodes (236) sequentially stacked from an upper surface of a substrate (100) along the first direction. The number of layers on which each of the first to third gate electrodes (232, 234, 236) is formed may vary depending on the number of layers of the sacrificial patterns (125).

Referring to FIG. 17, after forming a separator filling the opening (210) on the second blocking film (240), the separator and the second blocking film (240) can be flattened until the upper surface of the second interlayer insulating film (200) is exposed, and accordingly, a separating pattern (250) can be formed within the opening (210), and the second blocking film (240) can be separated into second blocking patterns (245).

The separation pattern (250) may include an oxide, such as silicon oxide, for example.

Referring to FIGS. 18 and 19, after forming a third interlayer insulating film (270) on the second interlayer insulating film (200), the separation pattern (250), and the second blocking pattern (245), a contact plug (280) that penetrates the second and third interlayer insulating films (200, 270) and contacts the upper surface of the capping pattern (190) can be formed. Thereafter, after forming a fourth interlayer insulating film (290) on the third interlayer insulating film (270) and the contact plug (280), a bit line (300) that penetrates the fourth interlayer insulating film (290) and contacts the upper surface of the contact plug (280) can be formed.

The contact plug (280) and bit line (300) may include metal, metal nitride, metal silicide, or polysilicon doped with impurities.

In exemplary embodiments, the bit line (300) may extend in the third direction and may be formed in multiple pieces spaced apart from each other along the second direction.

By performing the above-described processes, a vertical memory device can be completed.

As described above, each of the sacrificial films (120) constituting the mold may include silicon nitride doped with hydrogen, oxygen, and carbon. During a dry etching process for forming a channel hole (140) and an opening (210) penetrating the mold, hydrogen may increase the etching rate of the sacrificial film (120), and oxygen may oxidize a polymer formed on the inner wall of the channel hole (140) and the opening (210) to suppress its production. Meanwhile, during an additional cleaning process for the channel hole (140) and the opening (210) penetrating the mold, carbon may prevent over-etching of the sacrificial film (120) due to hydrogen and oxygen emissions.

Accordingly, by appropriately controlling the concentrations of hydrogen, oxygen, and carbon doped into the sacrificial films (120), each channel hole (140) and opening (210) penetrating the mold can be formed to have a constant width along the first direction, and a defect in which they do not expose the upper surface of the substrate (100) can be prevented. For example, the concentrations of hydrogen, oxygen, and carbon doped into each of the sacrificial films (120) formed in a plurality of layers can gradually decrease from a lower layer to an upper layer.

Below, the structural characteristics of the vertical memory manufactured through the aforementioned processes are described.

The vertical memory device may include a pillar structure formed on a substrate (100) and gate electrodes (232, 234, 236) each surrounding the pillar structure. The vertical memory device may further include insulating patterns (115), a second blocking pattern (245), a separation pattern (250), a contact plug (280), a bit line (300), and first to third interlayer insulating films (130, 200, 290).

In exemplary embodiments, the pillar structure may include a pillar-shaped charging pattern (185) extending in the first direction, a channel (175) having a cup shape and surrounding a sidewall and a bottom surface of the charging pattern (185), a charge storage structure (165) having a cup shape and surrounding an outer sidewall and a bottom surface of the channel (175), and a capping pattern (190) formed on the charging pattern (185) and the channel (175) and contacting an upper inner wall of the charge storage structure (165). In exemplary embodiments, a width of the pillar structure may be constant along the first direction, and a bottom surface of the pillar structure may contact an upper surface of the substrate (100).

Each of the gate electrodes (232, 234, 236) may extend in the second direction, and the gate electrodes (232, 234, 236) may be arranged on the substrate (100) to be spaced apart from each other along the first direction to form a gate electrode structure. In exemplary embodiments, the gate structures may be arranged in multiple pieces along the third direction, and may be spaced apart from each other in the third direction by a separation pattern (250) extending in the second direction.

In exemplary embodiments, the separation pattern (250) may be in contact with the upper surface of the substrate (100) and may extend in the first direction. At this time, the width of the separation pattern (250) in the third direction may be constant along the first direction.

Although the present invention has been described with reference to preferred embodiments thereof as described above, it will be understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims.

100: Substrate
110: Insulating film 115: Insulating pattern
120: Sacrifice Curtain 125: Sacrifice Pattern
130, 200, 270, 290: 1st to 4th interlayer insulating film
140: Channel hole
162: 1st blocking pattern 163: Charge storage pattern
164: Tunnel insulation pattern 165: Charge storage structure
175: Channel 185: Charging Pattern
190: Capping pattern 210: Opening
220: Gap
232, 234, 236: First to third gate electrodes
240: Second blocking curtain 245: Second blocking pattern
250: Separation pattern 280: Contact plug
300: bit line

Claims (10)

A mold is formed by alternately and repeatedly forming an insulating film and a sacrificial film on a substrate;
Forming a channel hole penetrating the above mold;
Forming a channel within the above channel hole;
forming an opening penetrating the mold;
forming gaps by removing the sacrificial films through the above openings; and
Including forming gate electrodes within the above gaps, respectively;
Each of the above sacrificial films comprises silicon nitride doped with hydrogen (H), oxygen (O), and carbon (C).
Among the above sacrificial films, the concentrations of hydrogen, oxygen and carbon doped in the sacrificial films formed in the upper layer are different from the concentrations of hydrogen, oxygen and carbon doped in the sacrificial films formed in the lower layer among the above sacrificial films.
A method for manufacturing a vertical memory device, wherein the carbon concentration within each of the above sacrificial films is lower than the hydrogen concentration and the oxygen concentration. A method for manufacturing a vertical memory device in accordance with claim 1, wherein the concentrations of hydrogen, oxygen and carbon doped in the sacrificial films gradually decrease from a lower layer to an upper layer. In the first paragraph, each of the sacrificial films is formed through a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process,
A method for manufacturing a vertical memory device in which each of the above sacrificial films is doped with hydrogen, oxygen, and carbon through an ion implantation process. delete A method for manufacturing a vertical memory device in accordance with claim 1, wherein forming the channel hole penetrating the mold includes a dry etching process. In the fifth paragraph, a method for manufacturing a vertical memory device further includes cleaning an inner wall of the channel hole through a wet etching process using hydrofluoric acid (HF) after performing the dry etching process, forming the channel hole penetrating the mold. Forming a mold including insulating films and sacrificial films alternately and repeatedly formed on a substrate, each formed in a plurality of layers;
Forming a channel hole penetrating the above mold;
Forming a channel within the above channel hole;
forming an opening penetrating the mold;
forming gaps by removing the sacrificial films through the above openings; and
Including forming gate electrodes within the above gaps, respectively;
Each of the above sacrificial films comprises silicon nitride doped with impurities including hydrogen (H), oxygen (O), and carbon (C).
Among the above sacrificial films, the concentrations of the doped impurities in each of the sacrificial films formed in at least two layers are different from each other,
A method for manufacturing a vertical memory device, wherein the carbon concentration within each of the above sacrificial films is lower than the hydrogen concentration and the oxygen concentration. In the 7th paragraph, each of the sacrificial films is formed through a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process,
A method for manufacturing a vertical memory device in which each of the above sacrificial films is doped with the impurities through an ion implantation process. delete A method for manufacturing a vertical memory device in accordance with claim 7, wherein the concentrations of the impurities doped within the sacrificial films gradually decrease from a lower layer to an upper layer.